JPS6418308A - Phase difference control device - Google Patents
Phase difference control deviceInfo
- Publication number
- JPS6418308A JPS6418308A JP62175051A JP17505187A JPS6418308A JP S6418308 A JPS6418308 A JP S6418308A JP 62175051 A JP62175051 A JP 62175051A JP 17505187 A JP17505187 A JP 17505187A JP S6418308 A JPS6418308 A JP S6418308A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- input signal
- stage
- phase shift
- accuracy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 abstract 4
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To apply phase shift control to the phase of an input signal in the accuracy of <=1 bit simply with high accuracy by connecting directly a phase difference control module comprising a voltage controlled phase shifter and a buffer amplifier, etc., in one-stage or multi-stage. CONSTITUTION:The phase difference control module 2 is basically made up of a voltage controlled phase shifter 3 shifting the phase of an input clock signal in response to the control signal, a buffer amplifier 4 waveform-shaping the output signal, a phase comparator 5 and an operational amplifier (feedback control circuit) 6. Since the phase shift with respect to the input signal is controlled via the voltage controlled phase shifter 3, the stable phase control is applied regardless of the temperature change or dispersion in the device components and independently of the frequency of the input signal. As a result, even if a delay of the accuracy less than one bit time is given to the input signal, the delay (phase shift quantity) is controlled simply with high accuracy. Moreover, the modules 2 are connected in multi-stage directly, then the phase shift is set programmably with high accuracy and high stability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62175051A JPS6418308A (en) | 1987-07-14 | 1987-07-14 | Phase difference control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62175051A JPS6418308A (en) | 1987-07-14 | 1987-07-14 | Phase difference control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6418308A true JPS6418308A (en) | 1989-01-23 |
Family
ID=15989375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62175051A Pending JPS6418308A (en) | 1987-07-14 | 1987-07-14 | Phase difference control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6418308A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0410629A2 (en) * | 1989-07-26 | 1991-01-30 | Nortel Networks Corporation | Automatic signal parameter control |
-
1987
- 1987-07-14 JP JP62175051A patent/JPS6418308A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0410629A2 (en) * | 1989-07-26 | 1991-01-30 | Nortel Networks Corporation | Automatic signal parameter control |
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