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JPS6414660A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS6414660A
JPS6414660A JP17153087A JP17153087A JPS6414660A JP S6414660 A JPS6414660 A JP S6414660A JP 17153087 A JP17153087 A JP 17153087A JP 17153087 A JP17153087 A JP 17153087A JP S6414660 A JPS6414660 A JP S6414660A
Authority
JP
Japan
Prior art keywords
data
main storage
cpu
access
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17153087A
Other languages
Japanese (ja)
Inventor
Toshiyuki Nakada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17153087A priority Critical patent/JPS6414660A/en
Publication of JPS6414660A publication Critical patent/JPS6414660A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To transfer data between processors at a higher speed than a cycle time of a main storage, by constituting the titled system so that the own central processing unit can access the main storage through a random access port, even while the processing unit is transferring the data to the other processors. CONSTITUTION:A processor 1 contains a CPU 5, a main storage 4,and a memory address register 9, and even while the processing unit 1 is transferring data to the other processors through an access port and a data transfer bus 2 successively under control by a data transfer device, the CPU 5 can execute an access to the main storage 4 through a random access port 26. In such a way, when the CPU 5 has tried to access the main storage 4, while the data is being transferred through the data transfer bus 2, the CPU 5 is allowed to wait for data access, only when the data is transferred between a memory cell and a shift register 28.
JP17153087A 1987-07-08 1987-07-08 Multiprocessor system Pending JPS6414660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17153087A JPS6414660A (en) 1987-07-08 1987-07-08 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17153087A JPS6414660A (en) 1987-07-08 1987-07-08 Multiprocessor system

Publications (1)

Publication Number Publication Date
JPS6414660A true JPS6414660A (en) 1989-01-18

Family

ID=15924831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17153087A Pending JPS6414660A (en) 1987-07-08 1987-07-08 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS6414660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5547018A (en) * 1993-12-10 1996-08-20 Fujitsu General Limited Air conditioner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5547018A (en) * 1993-12-10 1996-08-20 Fujitsu General Limited Air conditioner

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