JPS639971A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS639971A JPS639971A JP15449286A JP15449286A JPS639971A JP S639971 A JPS639971 A JP S639971A JP 15449286 A JP15449286 A JP 15449286A JP 15449286 A JP15449286 A JP 15449286A JP S639971 A JPS639971 A JP S639971A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring layer
- alloy
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 229910045601 alloy Inorganic materials 0.000 claims description 15
- 239000000956 alloy Substances 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 86
- 239000007789 gas Substances 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910008332 Si-Ti Inorganic materials 0.000 description 1
- 229910006749 Si—Ti Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 125000006413 ring segment Chemical group 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
半導体素子間を接続する配線層の構造、およびその配線
層を構成する成分元素の組成であって、前記配線構造が
三層構造で形成され、該三層構造の中間層がＴｔ、Ｔａ
等の金属層、或いはＴｉＮの合金層で形成され、前記中
間層を挟む上下層が鳩とＳｔとＴＬから成る合金層で形
成され、エレクトロマイグレーションやボイドによる断
線等の不良が発生しないようにした配線層が得られるよ
うにしたもの。[Detailed Description of the Invention] [Summary] A structure of a wiring layer connecting semiconductor elements and a composition of component elements constituting the wiring layer, wherein the wiring structure is formed in a three-layer structure, and the three-layer The intermediate layer of the structure is Tt, Ta
or a TiN alloy layer, and the upper and lower layers sandwiching the intermediate layer are formed of alloy layers consisting of St, St, and TL to prevent defects such as electromigration and disconnection due to voids. A device that allows a wiring layer to be obtained.
本発明は半導体装置、特に半導体装置に用いる配線層の
構造、及びその組成に関する。The present invention relates to a semiconductor device, and particularly to the structure and composition of a wiring layer used in a semiconductor device.
ＩＣ，ＬＳＩ等の半導体装置を形成する場合、Ｓｉ等の
半導体基板に形成された半導体素子間を接続するために
、〜等の配線層が用いられている。When forming semiconductor devices such as ICs and LSIs, wiring layers such as . . . are used to connect semiconductor elements formed on semiconductor substrates such as Si.
このらな配線層に於いては、半導体装置の動作中にエレ
クトロマイグレーションや、ボイド等による不良が発生
しないようにした、高信頼度の半導体装置が要望されて
いる。In these interconnection layers, there is a demand for a highly reliable semiconductor device that is free from defects due to electromigration or voids during operation of the semiconductor device.
従来、このような半導体素子を接続する配線層として、
ＭＯ５型半導体装置では、Ｓｔが１原子％混合された蔵
とＳｉの合金層が配線層として用いられている。然しこ
のような配線層は、高電流密度の電流を流した場合、エ
レクトロマイグレーション及びボイド成長等の現象が発
生して配線層が断線する問題がある。Conventionally, as a wiring layer for connecting such semiconductor elements,
In the MO5 type semiconductor device, an alloy layer of carbon dioxide and Si mixed with 1 atomic % of St is used as a wiring layer. However, when a high current density current is passed through such a wiring layer, phenomena such as electromigration and void growth occur, resulting in disconnection of the wiring layer.
そこでバイポーラ型半導体装置では、この〜とＳｉの合
金よりなる配線層に対して許容電流密度が１０〜５０倍
となる〜と銅（Ｃｕ）合金、及び〜とＣｕとＳｔ金合金
りなる配線層が用いられている。Therefore, in a bipolar semiconductor device, the allowable current density is 10 to 50 times higher than that of a wiring layer made of an alloy of ~ and Si, and a wiring layer made of a copper (Cu) alloy and a Cu and St gold alloy. is used.
またその他に上下に〜を用い、その〜の間にチタン（Ｔ
ｉ） 、クロム（Ｃｒ）及びタンタル（Ｔａ）等の遷移
金属元素を挟んだ三層構造の配線層も検討されている。In addition, ~ is used above and below, and titanium (T) is used between ~.
i) A three-layer wiring structure in which transition metal elements such as chromium (Cr) and tantalum (Ta) are sandwiched is also being considered.
然し、上記した〜とＣｏよりなる合金の内、Ｃｕ原子は
責金族原子であるために、この合金よりなる配線層を所
定のパターンに形成するためのドライエツチングのエツ
チングガスである塩素（α２）ガス等に対してエツチン
グされ難く、配線層が所定パターンに形成するのにエツ
チング時間がかかり過ぎたり、或いは所定のパターンに
精度良くエツチングできない問題を生じる。However, in the above-mentioned alloy consisting of ~ and Co, Cu atoms are metal group atoms, so chlorine (α2 ) It is difficult to be etched by gas etc., resulting in the problem that it takes too much etching time to form a wiring layer into a predetermined pattern, or it is not possible to precisely etch into a predetermined pattern.
また前記した〜−遷移金泥元素−〜の三層構造の配線層
では、エレクトロマイグレーションの現象が少なくなる
効果はあるものの、配線層に於ける〜原子の移動速度は
、従来の％−Ｓｉ合金の配線層よりも大となり、配線層
にボイド、及び突起が発生する不都合が生じる。Furthermore, although the above-described three-layer wiring layer of ~-transition gold mud element~ has the effect of reducing the electromigration phenomenon, the movement speed of ~ atoms in the wiring layer is lower than that of the conventional %-Si alloy. It becomes larger than the wiring layer, resulting in the inconvenience that voids and protrusions are generated in the wiring layer.
この他の配線層としては、エレクトロマイグレーション
に対する耐性を大にし、かつドライエツチングも短時間
でかつ高精度に行い得る配線層として〜−５ｉ−Ｔｉ合
金がある。Other wiring layers include -5i-Ti alloys, which have high resistance to electromigration and can be dry etched in a short time and with high precision.
然し、本発明者は、このような／％１７− Ｓｉ−Ｔｉ
合金のみで、一層構造として形成した配線層は、素子を
１００〜２００℃の温度で長時間放置した後、素子の特
性を検査する信頼度試験に於いて、断線が発生しやすい
問題を生じることを実験的に確かめた。However, the inventor has determined that such /%17-Si-Ti
A wiring layer formed as a single-layer structure using only an alloy can easily cause wire breakage in reliability tests that inspect the characteristics of the device after the device is left at a temperature of 100 to 200°C for a long time. was experimentally confirmed.
本発明は上記した問題点を解決し、エレクトロマイグレ
ーション、ボイド、断線等の不都合な現象が生じないよ
うにした配線層の提供を目的とする。An object of the present invention is to solve the above-mentioned problems and provide a wiring layer that does not cause inconvenient phenomena such as electromigration, voids, and disconnections.
本発明の半導体装置は、半導体素子間を接続する配線層
がアルミニウム＜Ａｇ＞とシリコン（Ｓｔ）とチタン（
Ｔｉ）の合金層で形成され、該合金層の間にチタン（Ｔ
ｉ） 、タンタル（Ｔａ）よりなる金属層、或いは窒化
チタン（ＴｉＮ）よりなる合金層が挟まれた三層構造で
形成されている。In the semiconductor device of the present invention, the wiring layer connecting the semiconductor elements is made of aluminum <Ag>, silicon (St), and titanium (
Ti), and between the alloy layers, titanium (T) is formed.
i) It has a three-layer structure in which a metal layer made of tantalum (Ta) or an alloy layer made of titanium nitride (TiN) are sandwiched.
本発明の半導体装置は、配線層として抵抗値が３〜３．
５μΩ−ロの〜−５ｉ−Ｔｉ合金層の間に、抵抗値が５
０〜１００μΩ−ロのＴｔＳＴａの金属層、或いはＴｉ
Ｎよりなる合金層を挟んで三層構造に形成することで配
線層を形成し、この三層構造の金属層が同時にエレクト
ロマイグレーション等の不都合が起こる確率は少ないこ
とを用いて、高信頼度の配線層を得るようにしたもので
ある。In the semiconductor device of the present invention, the wiring layer has a resistance value of 3 to 3.
Between the ~-5i-Ti alloy layers of 5μΩ-B, the resistance value is 5
0 to 100 μΩ-Ro metal layer of TtSTa or Ti
The wiring layer is formed by forming a three-layer structure with an alloy layer made of N sandwiched in between, and the metal layer of this three-layer structure has a low probability of causing problems such as electromigration at the same time. This is to obtain a wiring layer.
以下、図面を用いて本発明の一実施例に付き詳細に説明
する。Hereinafter, one embodiment of the present invention will be described in detail using the drawings.
第１図に示すように本発明の半導体装置は、Ｓｉ基板１
に形成された半導体素子領域２上が開口されたＳｉＯ２
膜よりなる絶縁膜３に所定パターンの配線層４が形成さ
れている。As shown in FIG. 1, the semiconductor device of the present invention includes a Si substrate 1
SiO2 with an opening above the semiconductor element region 2 formed in the
A wiring layer 4 having a predetermined pattern is formed on an insulating film 3 made of a film.
この配線層４の最下層５は、Ｓ＋環原子２Ｍ量％以下で
Ｔｉ原子が０．０５〜０．１５重量％の範囲で残りが〜
原子よりなる組成の成分で形成され、その厚さは０．３
〜０．７μｌである。The lowest layer 5 of this wiring layer 4 has S+ ring atoms of 2M% by weight or less, Ti atoms in the range of 0.05 to 0.15% by weight, and the remainder ~
It is formed of components with a composition consisting of atoms, and its thickness is 0.3
~0.7 μl.
この最下層５上に形成されている中間層６はＴｉ、Ｔａ
の金属層、またはＴｉＮの合金層で形成され、その厚さ
は５００〜１０００人で形成されている。The intermediate layer 6 formed on this bottom layer 5 is made of Ti, Ta.
It is formed of a metal layer or a TiN alloy layer, and its thickness is 500 to 1000.
またこの中間層上には、前記した最下層５で用いられた
ものと同一材料で、同一組成のＴｉｓ Ｓｉ、〜よりな
る合金よりなる配線層が最上層７の配線層として、０．
３〜０．７μｍの厚さで形成されている。Further, on this intermediate layer, a wiring layer made of the same material as that used for the bottom layer 5 described above and an alloy of Tis-Si, .
It is formed with a thickness of 3 to 0.7 μm.
このような配線層を形成するには、前記絶縁層３を形成
したＳｉ基板１をスパッタ装置の反応容器内に導入し、
該反応容器を１０ 以下の真空度に成る迄排気する。To form such a wiring layer, the Si substrate 1 with the insulating layer 3 formed thereon is introduced into a reaction vessel of a sputtering device, and
The reaction vessel is evacuated to a vacuum of 10° or less.
次いでＳｉ原子が２重量％以下、Ｔｉ原子が０．０５〜
０．１５重量％、残りが〜原子より形成されているター
ゲットを用い、かつアルゴン（Ａｒ）ガスをスパッタ用
ガスとして用いてターゲットをスパッタし、基板上に上
記した組成の金属膜を最下層５の金属膜として形成する
。Next, Si atoms are 2% by weight or less, and Ti atoms are 0.05 to 2% by weight.
A metal film having the above composition is deposited on the substrate as the bottom layer 5 by sputtering the target using a target containing 0.15% by weight and the remainder being atoms and using argon (Ar) gas as the sputtering gas. Formed as a metal film.
次いでターゲットにＴｌ５ＴａＳＴｉＨのターゲットを
用いて、前記した条件でＡｒガスをスパッタガスとして
用いて該ターゲットをスパッタし、最下層５上に厚さが
５００〜１０００人の中間層６を形成する。Next, using a Tl5TaSTiH target, the target is sputtered under the conditions described above using Ar gas as a sputtering gas to form an intermediate layer 6 having a thickness of 500 to 1000 layers on the bottom layer 5.
尚、ＴｉＮの形成に際しては、反応性スパッタリング法
を用い、ＴｉをＡｒガスと窒素ガスとの混合ガス中でス
パッタして形成することを可能である。Note that when forming TiN, it is possible to form Ti by sputtering in a mixed gas of Ar gas and nitrogen gas using a reactive sputtering method.
次いでＳｉ原子が２重量％以下、Ｔｉ原子が０．０５〜
０．１５重量％、残りが〜原子より形成されているター
ゲットを用い、かつアルゴン（Ａｒ）ガスをスパッタ用
ガスとして用いてターゲットをスパッタし、最上層７の
金属層を形成する。Next, Si atoms are 2% by weight or less, and Ti atoms are 0.05 to 2% by weight.
A metal layer as the uppermost layer 7 is formed by sputtering the target using a target containing 0.15% by weight and the remainder being atoms and using argon (Ar) gas as a sputtering gas.
その後、該配線層４上にホトレジスト膜を形成した後、
該ホトレジスト膜を所定パターンに形成後、該パターン
形成されたホトレジスト膜をマスクとして用いて塩Ｓ
（ＣＲ２）ガスを主とし、その他塩素の化合物ガスを混
合した混合ガスをエツチングガスとして用いて配線層４
を所定のパターンにエツチング形成して半導体装置を形
成する。After that, after forming a photoresist film on the wiring layer 4,
After forming the photoresist film into a predetermined pattern, using the patterned photoresist film as a mask, salt S
(CR2) The wiring layer 4 is etched using a mixed gas consisting mainly of gas and other chlorine compound gases as an etching gas.
A semiconductor device is formed by etching into a predetermined pattern.
このようにすれば、配線層の中間層が最上層、および最
下層より抵抗値が、遥かに高い金属層、或いは合金層で
形成されているので、３層共、同一箇所でエレクトロマ
イグレーション等の事故が発生する確率が少な（なり、
高信頼度の半導体装置が得られる。In this way, since the intermediate layer of the wiring layer is formed of a metal layer or an alloy layer with a much higher resistance value than the top layer and the bottom layer, electromigration etc. can occur at the same location in all three layers. The probability of an accident occurring is low.
A highly reliable semiconductor device can be obtained.
尚、本発明者は実験の結果、エレクトロマイグレーショ
ンの事故発生率は〜−３ｉ合金の一層構造の配線層に比
較して１／１００以下に低下していることを確かめた。As a result of experiments, the inventor of the present invention has confirmed that the electromigration accident rate is reduced to 1/100 or less compared to a wiring layer having a single layer structure of ~-3i alloy.
またこのような配線層を用いた半導体装置を、１５０℃
の窒素ガス雰囲気内で長時間放置する信頼度試験を行っ
た結果、配線層に断線、或いはボイドが発生する事故は
皆無であった。Furthermore, a semiconductor device using such a wiring layer can be heated to 150°C.
As a result of a reliability test in which the device was left in a nitrogen gas atmosphere for a long period of time, there were no incidents of disconnection or voids occurring in the wiring layer.
以上述べたように、本発明の三層構造で、最上層、中間
層、最下層に前記した組成の合金層、或いは金属層を用
いた配線層を用いると、エレクトロマイグレーション、
ボイド等の現象が発生しない高信頼度の半導体装置が得
られる効果がある。As described above, in the three-layer structure of the present invention, when the uppermost layer, the intermediate layer, and the lowermost layer are used as wiring layers using an alloy layer or a metal layer having the composition described above, electromigration,
This has the effect of providing a highly reliable semiconductor device in which phenomena such as voids do not occur.
第１図は本発明の配線層を用いた半導体装置の要部を示
す断面図である。
図に於いて、
ｌはＳｔ基板、２は半導体素子、３は絶縁膜、４は配線
層、５は最下層、６は中間層、７は最上層を示す。FIG. 1 is a sectional view showing a main part of a semiconductor device using the wiring layer of the present invention. In the figure, 1 is an St substrate, 2 is a semiconductor element, 3 is an insulating film, 4 is a wiring layer, 5 is a bottom layer, 6 is an intermediate layer, and 7 is a top layer.
Claims (1)
定パターンの配線層（４）で接続された装置であって、 前記配線層（４）が最下層（５）と中間層（６）と最上
層（７）の三層構造で形成され、 前記最下層（５）と最上層（７）が、アルミニウム（Ａ
ｌ）とシリコン（Ｓｉ）とチタン（Ｔｉ）の合金層で形
成され、前記中間層（６）がチタン（Ｔｉ）、タンタル
（Ｔａ）よりなる金属層、或いは窒化チタン（ＴｉＮ）
よりなる合金層で形成されていることを特徴とする半導
体装置。[Scope of Claims] A device in which semiconductor elements (2) formed on a semiconductor substrate (1) are connected by a wiring layer (4) having a predetermined pattern, the wiring layer (4) being a bottom layer (5). ), an intermediate layer (6), and a top layer (7), and the bottom layer (5) and top layer (7) are made of aluminum (A
l) is formed of an alloy layer of silicon (Si) and titanium (Ti), and the intermediate layer (6) is a metal layer made of titanium (Ti), tantalum (Ta), or titanium nitride (TiN).
A semiconductor device characterized in that it is formed of an alloy layer consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15449286A JPS639971A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15449286A JPS639971A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639971A true JPS639971A (en) | 1988-01-16 |
Family
ID=15585427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15449286A Pending JPS639971A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639971A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747361A (en) * | 1991-05-01 | 1998-05-05 | Mitel Corporation | Stabilization of the interface between aluminum and titanium nitride |
| US5773917A (en) * | 1993-10-27 | 1998-06-30 | Fujitsu Limited | Surface acoustic wave device and production process thereof |
-
1986
- 1986-06-30 JP JP15449286A patent/JPS639971A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747361A (en) * | 1991-05-01 | 1998-05-05 | Mitel Corporation | Stabilization of the interface between aluminum and titanium nitride |
| US5773917A (en) * | 1993-10-27 | 1998-06-30 | Fujitsu Limited | Surface acoustic wave device and production process thereof |
| US5774962A (en) * | 1993-10-27 | 1998-07-07 | Fujitsu Limited | Process for producing a surface acoustic wave device |
| USRE38002E1 (en) * | 1993-10-27 | 2003-02-25 | Fujitsu Limited | Process for providing a surface acoustic wave device |
| USRE38278E1 (en) * | 1993-10-27 | 2003-10-21 | Fujitsu Limited | Surface acoustic wave device and production process thereof |
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