JPS6390172A - Field effect transistor and manufacture thereof - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a high-speed field effect transistor that utilizes a two-dimensional electron channel at a heterojunction interface and a method for manufacturing the same.

[Conventional technology]

A high-speed field effect transistor (hereinafter referred to as FET) that utilizes a two-dimensional electron channel at the hetero interface between GaAs and Ae GaAs is a GaAs transistor that is already widely used today.
It is expected to have faster and higher performance characteristics than Schottky junction FETs using As, and will be used as low-noise devices and high-speed ICs.
Applications are being actively researched.

The third is a schematic cross-sectional view of an example of a conventional FET.

In this example, a semiconductor layer 2 made of high-purity GaAs, a semiconductor layer 4 made of high-purity ke GaAs containing no donor impurity atoms, and a high-concentration n-type GaAs semiconductor layer 2 formed sequentially on a high-resistance substrate 1 made of G and xAs are formed. The so-called 5IS (semiconductor/insulator) is provided with a gate of an impurity layer 5 consisting of material/semiconductor)
It is a FET with a structure like this.

Moreover, in this example, regardless of the thickness of the semiconductor layer 4, due to the difference in electron affinity between the semiconductor layer 2 and the gate of the impurity layer 5,
Since the threshold voltage is determined, the threshold voltage value can be determined by appropriately selecting both, and the controllability of the threshold voltage value is good.

Further, in this example, since there is no deep energy level due to impurity atoms in the semiconductor layer 4 made of kl GaAs, the characteristics are also stable.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional field effect transistor, the thickness of the semiconductor layer 4 made of high-purity AffGaAs is as thin as several hundred angstroms, so that such a thin part and the surface part of the underlying semiconductor layer 2 made of undoped GaAs are However, it is difficult to form a highly concentrated impurity layer 7' by implanting high-dose ions, and therefore it is difficult to obtain a low source resistance with a small sheet resistance.

On the other hand, if ions are implanted deep into the semiconductor layer 2 in order to reduce the sheet resistance, in a short channel device where the distance between the source and drain impurity layers 7' is short, the depletion layers extending from both sides will connect and become undoped. Ga
I sob = 9ε3μ as a space charge limited current l5ub due to electrons injected into the semiconductor layer 2 made of As. A V o 2/8 L
3...A current expressed as <1) flows. Here, ε3 is the dielectric constant of the semiconductor, μ. is the electron mobility, A is the area of the n+ type impurity layer into which electrons are injected, VD is the drain voltage, and L is the gate length. Therefore, characteristic deterioration occurs due to the so-called short channel effect, such as an increase in drain conductance and a change in threshold voltage.

[Means for solving problems]

The field effect transistor of the present invention includes a high-purity first semiconductor layer deposited on a high-resistance substrate, and a semiconductor layer deposited on the first semiconductor layer and having a lower electron affinity than the first semiconductor layer. A second semiconductor layer having a predetermined pattern, a gate I- formed on the second semiconductor layer, and a high concentration semiconductor layer selectively deposited on the first semiconductor layer with the second semiconductor layer in between. It includes a source and a drain made of impurity layers.

A method for manufacturing a field effect transistor according to the present invention includes a first semiconductor layer of high purity sequentially deposited on a high resistance substrate and a first semiconductor layer of high purity deposited on a high resistance substrate;
A second semiconductor layer including a semiconductor layer having a lower electron affinity than the semiconductor layer of
forming a gate with a predetermined pattern on the semiconductor layer; removing the second semiconductor layer using the gate as a mask to expose the surface of the first semiconductor layer; The method includes a step of forming a source and a drain made of a high concentration impurity layer on the exposed portion of the layer surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of the FET of the present invention.

In this embodiment, a high-resistance substrate 1 made of GaAs, a group III-V compound, is coated with a carrier density of I x 10''/CI!13 and a thickness of 1 by molecular beam epitaxial method.
A semiconductor layer 2 made of p-type GaAs of μm is provided, and a predetermined pattern is formed on the semiconductor layer 2 to a thickness of 300 people! . ,5GaO,
Semiconductor consisting of 5As N4 thickness 200 people carrier density 5
×10'8 pieces/An impurity layer 5 made of an n-type GaAs layer of C113 and a heat-resistant gate electrode made of WSi are provided on the exposed surface of the semiconductor layer 2 on both sides of the semiconductor layer 4 to a thickness of 10'.
00 people carrier density 1×101019l1/CIa3n
A highly concentrated impurity layer 7 made of GaAs type is provided, and a source electrode 8 and a drain electrode 9 are further provided thereon.

Here, electrons flow through a two-dimensional electron channel 3 in the channel region.

Therefore, the sheet resistance becomes extremely small due to the high concentration impurity layer 7 of n-type GaAs, which is 1000 thick, and the source resistance is also reduced. Furthermore, even if the device is miniaturized, the highly concentrated impurity layer 7 does not penetrate into the semiconductor layer 2 made of n-type GaAs, so the area A of the n'' layer into which electrons are injected becomes smaller, and the distance through which electrons flow becomes larger. Therefore, n-type GaA
The space charge limited current I mob, expressed by equation (1), flowing through the semiconductor layer 2 made of s decreases.

This allows the gate length to be set to 30μm, 10μm, 3μm.
Even when miniaturized to m, 1 μm, or 0.5 μm, characteristic deterioration due to the short channel effect appears only slightly, and moreover, the semiconductor layer 7 made of a highly doped n-type GaAs layer is in direct contact with the two-dimensional electron channel. , the source resistance becomes small and good characteristics can be obtained.

FIGS. 2(a) to 2(d) are schematic cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the FET manufacturing method of the present invention.

In this embodiment, as shown in FIG. 2(a), a carrier density of about 1×10'4/C1 is grown by molecular beam epitaxial growth on a high-resistance substrate 1 made of GaAs of the ■-V group.
13. After forming a semiconductor layer 2 made of n-type GaAs with a thickness of 1 μm, an undoped AI layer 2 with a thickness of 300 layers is formed on this layer. Semiconductor layer 4 made of g, 5Ga, ), 5As and a thickness of 200 carriers concentration x 1018 pieces/c
A semiconductor layer 5 made of n-type GaAs of ra' is sequentially formed, and a heat-resistant gate electrode 6 made of WSi having a thickness of 4000 nm in a predetermined pattern is further formed on top of the semiconductor layer 5. Then, using the gate electrode 6 as a mask, first NH40H-11
Only the semiconductor layer 5 made of n-type GaAs is removed using an etching solution No. 202-1120.

Next, as shown in Figure 2(b), the S
After covering the entire iO□ film 10, patterning is performed to form openings over the gate electrode 6, source and drain formation regions.

Next, as shown in FIG. 2(C), the gate electrodes 6 and 5
Using i02 film 10 as a mask ^lo, 5Gag, 5A
Only the semiconductor layer 4 made of s is removed using an etching solution of H3PO4-8202, taking advantage of the fact that the composition ratio of A2 is 0.4 or more, and the surface of the semiconductor layer 2 made of an n-type GaAs layer is exposed. do.

Next, as shown in FIG. 2(d), a heat-resistant gate electrode 6 and a SiO□ film 10 are selectively regrown on the semiconductor layer 2 at 600° C. with Se as an impurity. Thickness 1000, carrier concentration 1x 1 () 19 pieces/
A semiconductor layer 7 made of C112 n-type GaAs is formed.

Finally, an AuGe alloy layer with a predetermined pattern is deposited on the impurity layer 7 and the impurity layer 7 is alloyed with GaAs to form source and drain electrodes 8 and 9.
By forming this, an FET as shown in FIG. 1 can be obtained.

In this example, since the semiconductor layer 4 is removed by selective etching, the etching automatically stops at the surface of the semiconductor layer 2 and the reproducibility of the etching is very good.

〔Effect of the invention〕

As explained above, the present invention provides high concentration impurity layers 7 for the source and drain on the semiconductor layer 2.
This has the advantage that a high-performance FET can be realized with a fine structure that has a small source resistance and does not suffer from characteristic deterioration due to the short channel effect.

In addition, as a method for realizing this structure, the second semiconductor layer is etched using the selectivity of the semiconductor layer 2 and the semiconductor layer 4 with respect to the etching solution, and a highly concentrated impurity layer is formed by selective regrowth. Another advantage is that high-performance FETs with low source resistance can be manufactured with good reproducibility.

Furthermore, the present invention can be applied to Fe-doped InP as the high-resistance substrate 1 of the IV group compound, and high-purity ke as the semiconductor layer 2.
0.48caO-52As 5000 people and high purity G
ao, 471ng, 53As for 1000 people, semiconductor layer 4
As high purity A! ! 0.48”ao, 52As to 30.
0, 2×10 doped with Si as impurity layer 5
18cra-', n-type Gao, 471no, 53As and 4X1018cI doped with Si as impurity layer 7
Similar effects were observed when applied to FETs using 1-3, n-type Ga, ), 47In, ), and 53As.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an embodiment of the FET of the present invention, and FIGS. 2(a) to 2(d) are semiconductors shown in order of steps for explaining an embodiment of the FET manufacturing method of the present invention. A schematic cross-sectional view of the chip, FIG. 3 is a schematic cross-sectional view of an example of a conventional FET. DESCRIPTION OF SYMBOLS 1... High resistance substrate, 2... Semiconductor layer, 3... Two-dimensional electron channel, 4... Semiconductor layer, 5... Impurity layer, 6... Gate electrode, 7.7'. ... impurity layer, 8.
8'...source electrode, 9.9'...drain electrode,
10...SiO□ film. Figure 1 *3 times

Claims (2)

[Claims] (1) A first semiconductor layer of a predetermined pattern including a high-purity first semiconductor layer deposited on a high-resistance substrate and a semiconductor layer having a lower electron affinity than the first semiconductor layer deposited on the first semiconductor layer. a source and drain consisting of a second semiconductor layer, a gate formed on the second semiconductor layer, and a high concentration impurity layer selectively deposited on the first semiconductor layer with the second semiconductor layer in between. A field effect transistor comprising: (2) A gate in a predetermined pattern is formed on a high-purity first semiconductor layer and a second semiconductor layer including a semiconductor layer having a lower electron affinity than the first semiconductor layer, which are sequentially deposited on a high-resistance substrate. and using the gate as a mask.
the step of removing the semiconductor layer to expose the surface of the first semiconductor layer; and the step of forming a source and a drain made of a highly concentrated impurity layer on the exposed portion of the surface of the first semiconductor layer. A method for manufacturing a field effect transistor characterized by: