JP3633587B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to, for example, a semiconductor device in which charges are confined in a stacked structure of a plurality of semiconductor layers so as to be able to run at high speed, such as a high electron mobility transistor.OfIt relates to a manufacturing method.
[0002]
[Prior art]
In recent years, in mobile communication systems such as mobile phones, miniaturization of terminals and low power consumption have been strongly demanded. For this reason, similar demands have been made for devices such as transistors constituting the same.
For example, a digital cellular power amplifier that can be said to be a pillar of current mobile communication is required to be capable of operating a single positive power source and having a low voltage and high efficiency.
[0003]
One of the devices currently in practical use for power amplifiers is a high electron mobility transistor (HEMT) and a certain degree of lattice mismatch in the epitaxial structure, allowing higher electron mobility. Realized pseudo latticeAlignmentExamples include a high electron mobility transistor (PHEMT: Pseudomorphic HEMT).
In either case, current modulation is performed using a heterojunction structure.
[0004]
FIG. 10 shows a cross-sectional view of one configuration example of the above-described PHEMT.
The PHEMT shown in FIG. 10 includes a first barrier layer 33 made of AlGaAs on a substrate 31 made of semi-insulating single crystal GaAs and a buffer layer 32 made of GaAs to which no impurity is added, and InGaAs. A channel layer 34 and a second barrier layer 35 made of AlGaAs are sequentially stacked.
Each of the barrier layers 33 and 35 has a carrier supply layer 33a and 35a containing a first conductivity type, for example, an n-type impurity, and high resistance layers 33b and 33c and 35b and 35c, respectively.
[0005]
An insulating film 37 is formed on the second barrier layer 35 via an n-type GaAs layer 36 containing an n-type impurity.
An opening is formed in the insulating film 37, and a source electrode 39 a and a drain electrode 39 b are formed in the opening via an n-type GaAs layer 36.
A gate electrode 38 is formed in the other opening of the insulating film 37. When a voltage is applied to the gate electrode 38, the current flowing between the source electrode 39a and the drain electrode 39b is modulated. .
[0006]
In the above-described PHEMT, generally, as another configuration example, a recess structure in which the thickness of the second barrier layer 35 is thinned under the gate electrode is often used. In this case, a region in which carriers are depleted or a region having fewer carriers than other channel regions is formed.
[0007]
In the PHEMT having such a structure, carriers are accumulated in the channel layer 34 by applying a positive voltage to the gate electrode 38, and in principle, compared with a Schottky junction field effect transistor (MES-FET: Metal Semiconductor FET). Thus, the linearity of the mutual conductance Gm with respect to the gate voltage Vg is excellent. This is a great advantage in aiming at high efficiency of the power amplifier.
[0008]
On the other hand, for the single positive power supply operation, the first conductivity type semiconductor in the channel layer and the second conductivity type semiconductor directly under the gate are doped by doping a second conductivity type, for example, a p-type impurity, directly under the gate electrode. There is a junction field effect transistor (JFET: Junction FET) that can increase the Φbi (built-in potential) and the positive operating power supply.
At this time, in order to increase Φbi, there is a method of selecting a semiconductor having a band gap larger than that of the channel layer for the semiconductor layer immediately below the gate, in addition to the method of doping the impurity of the second conductivity type. The PHEMT shown in FIG. 10 adopts this method.
[0009]
Junction-pseudo lattice combining the advantages of JFET and PHEMTAlignmentOne structural example of a high electron mobility transistor (JPEMMT: Junction PHEMT) is shown in FIG.
[0010]
The JPHEMT shown in FIG. 11 includes a first barrier layer 43 made of AlGaAs on a substrate 41 made of semi-insulating single crystal GaAs and a buffer layer 42 made of GaAs to which no impurity is added, and InGaAs. A channel layer 44 and a second barrier wall 45 made of AlGaAs are sequentially stacked.
Each of the barrier layers 43 and 45 includes carrier supply layers 43a and 45a containing first conductivity type (n-type) impurities, and high resistance layers 43b and 43c and 45b and 45c, respectively.
[0011]
An insulating film 47 having an opening is formed on the second barrier layer 45, and a source electrode 49a and a drain electrode 49b are formed in the opening.
A gate electrode 48 is formed in the other opening of the insulating film 47, and a second conductivity type (p-type) impurity (Zn) is introduced into the second barrier layer 45 immediately below the gate. A gate impurity region 50 is formed.
Also in the JPHEMT configured as described above, when a voltage is applied to the gate electrode 48, the current flowing between the source electrode 49a and the drain electrode 49b is modulated.
[0012]
In the JPHEMT configured as described above, the smaller the distance d between the gate impurity region 50 and the channel layer 44, the larger the Φbi (built-in potential) between the semiconductor constituting the channel layer 44 and the gate impurity region 50 immediately below the gate. It is possible to use only a positive operating power supply.
[0013]
[Problems to be solved by the invention]
However, in the JPHEMT shown in FIG. 11, when AlGaAs is used for the second barrier layer 45 and a second conductivity type (p-type) impurity (Zn) is introduced by vapor phase diffusion directly under the gate, The diffusion coefficient of Zn is large and Zn diffuses quickly in the AlGaAs layer, and the bottom surface of the Zn diffusion region reaches the depth d from the channel layer 44 with a small amount of Zn. For this reason, compared with the case where GaAs is used for the second barrier layer 45, the concentration of the second conductivity type impurity (Zn) on the outermost surface of the second barrier layer 45 becomes about ½, which is good. There is a problem that an ohmic contact cannot be obtained. In this case, the gate resistance generally referred to is increased, which adversely affects the gain of the power amplifier.
[0014]
As described above, in order to increase the Φbi and enable the single positive power supply operation, the second barrier layer 45 is made of a semiconductor such as AlGaAs having a large band gap and has a good ohmic contact with the gate electrode. In order to realize this, it is desired to increase the second conductivity type impurity concentration on the outermost surface of the second barrier layer 45.
[0015]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of reducing gate resistance while enabling single positive power supply operation.SetIt is to provide a manufacturing method.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention includes a step of forming a channel layer, a step of forming a first semiconductor layer on the channel layer, and a step of forming on the first semiconductor layer.First conductivityForming a second semiconductor layer containing impurities; forming a mask layer having an opening in a part of the second semiconductor layer; and using the mask layer as a mask, the second and first semiconductor layersSecond conductive impurity of the same conductivity type as the first conductive impurityAnd forming a gate impurity region and forming a gate electrode on at least the second semiconductor layer exposed in the opening.
[0024]
Preferably, in the step of forming the second semiconductor layer,First conductive impurityIt is formed by an epitaxial growth method to which is added.
[0025]
Preferably, the second and first semiconductor layersSecond conductive impurityIn the process of introducing gas phase diffusion or ion implantationSecond conductive impurityIntroduce
[0026]
Preferably,First conductive impurity and second conductive impurityAre the same material.
For example,The first conductive impurity and the second conductive impurity areZn is contained.
[0028]
Preferably,After the step of forming the first semiconductor layer, a stopper layer having an etching selectivity with the second semiconductor layer is formed, and the second semiconductor layer is formed on the stopper layer,After the step of forming the gate electrode, using the gate electrode as a mask, the mask layer and the second semiconductor layer formed in other regions while leaving the mask layer and the second semiconductor layer formed under the gate electrode Is further removed by etching until the stopper layer is exposed.
[0029]
Preferably, after the step of removing the mask layer and the second semiconductor layer by etching, the method further includes the step of forming the source electrode and the drain electrode separately from each other on the stopper layer with the gate electrode interposed therebetween.
[0030]
For example, in the step of forming the channel layer, the channel layer is formed of InGaAs, and in the step of forming the first semiconductor layer, the first semiconductor layer is formed of AlGaAs.
[0031]
In the semiconductor device manufacturing method of the present invention, the first semiconductor layer is formed on the channel layer, and the first semiconductor layer is formed on the first semiconductor layer.First conductive impurityA second semiconductor layer containing the first semiconductor layer, a mask layer having an opening in a part of the second semiconductor layer, and the mask layer as a mask in the second and first semiconductor layersFirst conductive impurityTo form a gate impurity region, and a gate electrode is formed on at least the second semiconductor layer exposed in the opening.
And for example,First conductive impurityBy forming the second semiconductor layer by an epitaxial growth method to which is added, the second semiconductor layer has a concentration enough to reduce the contact resistance with the gate electrode.First conductive impurityCan be introduced.
After that, by introducing a second conductivity type impurity into the second and first semiconductor layers by vapor phase diffusion or ion implantation, to a desired depth.Second conductive impurityTo control the depth, thereby controlling the threshold value of the current flowing through the channel layer.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0033]
FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device according to the present embodiment.
The semiconductor device shown in FIG. 1 is made of, for example, a III-V compound semiconductor on a substrate 11 made of semi-insulating single crystal GaAs via a buffer layer 12 made of undoped GaAs to which no impurity is added. A first barrier layer 13, a channel layer 14, and a second barrier layer 15 are sequentially stacked.
[0034]
An etching stopper layer 16 to be described later is deposited on the second barrier layer 15 to a required thickness, for example, about 5 nm, and an island-like high-concentration gate impurity layer 17 is deposited on a part of the stopper layer 16. Has been.
[0035]
On the high-concentration gate impurity layer 17, an insulating film 18 is deposited to a required thickness, for example, about 300 nm. The insulating film 18 is provided with an opening 18a, and a gate electrode 21 is formed through the opening 18a.
[0036]
An insulating film 19 is deposited to a required thickness, for example, about 300 nm, covering the stopper layer 16 and the gate electrode 21. The insulating film 19 is provided with two openings 19a and 19b at appropriate intervals on the stopper layer 16, and a source electrode 22a and a drain electrode 22b are formed in the openings 19a and 19b.
[0037]
A gate impurity region 20 doped with an impurity of the second conductivity type is formed in the high-concentration gate impurity layer 17, the stopper layer 16, and the second barrier layer 15 below the gate electrode 21. For example, zinc (Zn) as a p-type impurity is doped by vapor phase diffusion.
[0038]
Hereinafter, each layer will be described in detail.
The barrier layers 13 and 15 are made of a semiconductor having a wider band gap than the semiconductor constituting the channel layer 14. For example, Al_xGa_1-xAs mixed crystals are preferable, and the composition ratio of aluminum (Al) is usually x = 0.2 to 0.3.
[0039]
The barrier layers 13 and 15 are basically high-resistance layers that do not contain impurities, but carriers containing high-concentration n-type impurities at a required distance from the channel layer 14, for example, about 2 to 4 nm. Supply layers 13a and 15a are provided.
[0040]
Here, the carrier supply layers 13a and 15a have a required thickness, for example, a thickness of about 4 nm, and silicon (Si) as the n-type impurity as a required dose, for example, 1.0 × 10.¹²~ 2.0 × 10¹²/ Cm²To some extent added. The high resistance layers 13b and 15b to which no impurities are added between the carrier supply layers 13a and 15a and the channel layer 14 are thinner than the carrier supply layers 13a and 15a, for example, a structure having a thickness of about 2 nm. have.
[0041]
The channel layer 14 is a current path between the source electrode 22 a and the drain electrode 22 b, and is made of a semiconductor having a narrower band gap than the semiconductor that forms the barrier layers 13 and 15.
For example, In_xGa_1-xAs is preferable, and is usually composed of an undoped-InGaAs mixed crystal to which an impurity having an In composition ratio of about x = 0.1 to 0.2 is not added. Thus, carriers supplied from the carrier supply layer 13 a of the first barrier layer 13 and the carrier supply layer 15 a of the second barrier layer 15 are accumulated in the channel layer 14.
[0042]
The stopper layer 16 serves to stop etching when the high concentration gate impurity layer 17 is selectively etched. For example, when the high-concentration gate impurity layer 17 is formed of AlGaAs, the stopper layer 16 is GaAs or AlGaAs having a composition ratio different from that of the high-concentration gate impurity layer 17 and further reduces the contact resistance with the gate electrode. In addition, when GaAs is used as the high-concentration gate impurity layer 17, the stopper layer 16 has an Al composition ratio x = about 0.5._xGa_1-xAs is preferred.
[0043]
The high concentration gate impurity 17 is composed of a semiconductor layer having a wider band gap than the semiconductor composing the channel layer 14. For example, Al_xGa_1-xAs is preferable, and the aluminum (Al) composition ratio is x = 0.2 to 0.3. The high-concentration gate impurity layer 17 has a p-type impurity, for example, zinc (Zn), which has a required impurity concentration, for example, about 2 × 10.¹⁹/ Cm³More than this is doped.
[0044]
The gate electrode 21 has a configuration in which titanium (Ti), platinum (Pt), and gold (Au) are sequentially stacked from the substrate side.
[0045]
The source electrode 22a and the drain electrode 22b are formed by sequentially laminating gold germanium (AuGe), nickel (Ni), and gold (Au) from the substrate side, and the barrier layer 15 and the stopper layer 16 are formed. Through ohmic contact.
[0046]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
[0047]
First, as shown in FIG. 2A, on a substrate 11 made of semi-insulating single crystal GaAs, undoped GaAs to which no impurities are added is formed by a MOCVD (Metal Organic Chemical Vapor Deposition) method, for example. The buffer layer 12 is formed by epitaxial growth with a thickness of, for example, about 3 to 5 μm.
[0048]
Next, as shown in FIG. 2B, the high resistance layer 13c is formed on the buffer layer 12 by epitaxially growing, for example, about 200 nm of undoped-AlGaAs to which no impurity is added, by MOCVD, for example.
[0049]
Next, as shown in FIG. 2C, n-type AlGaAs doped with silicon as an n-type impurity is epitaxially grown on the high resistance layer 13c by, for example, MOCVD, for example, by about 4 nm to form a carrier supply layer 13a. Form.
[0050]
Next, as shown in FIG. 3D, on the carrier supply layer 13a, for example, MOCVD is used to epitaxially grow, for example, about 2 nm of undoped AlGaAs to which no impurities are added, thereby forming the high resistance layer 13b. Thereby, the first barrier layer 13 including the high resistance layer 13c, the carrier supply layer 13a, and the high resistance layer 13b is formed.
[0051]
Next, as shown in FIG. 3E, channel layer 14 is formed on first barrier layer 13 by epitaxially growing, for example, about 10 nm of undoped InGaAs to which no impurity is added, by MOCVD, for example. .
[0052]
Next, as shown in FIG. 3F, the high resistance layer 15b is formed on the channel layer 14 by epitaxially growing, for example, about 2 nm of undoped AlGaAs to which no impurity is added, by MOCVD, for example.
[0053]
Next, as shown in FIG. 4G, n-type AlGaAs doped with silicon as an n-type impurity is epitaxially grown on the high resistance layer 15b by, eg, MOCVD, for example, by about 4 nm to form a carrier supply layer 15a. Form.
[0054]
Next, as shown in FIG. 4 (h), on the carrier supply layer 15a, undoped-AlGaAs to which no impurity is added is epitaxially grown, for example, by about 130 nm, for example, by MOCVD, to form a high resistance layer 15c.
Thus, the second barrier layer 15 including the high resistance layer 15c, the carrier supply layer 15a, and the high resistance layer 15b is formed.
[0055]
Next, as shown in FIG. 5I, the stopper layer 16 is formed on the second barrier layer 15 by epitaxially growing GaAs by about 130 nm, for example, by MOCVD.
[0056]
Next, as shown in FIG. 5J, on the stopper layer 16, for example, by MOCVD, for example 2 × 10¹⁹/ Cm³The p-type AlGaAs doped with the above high-concentration Zn as an impurity is epitaxially grown to form the high-concentration gate impurity layer 170.
Thereafter, element isolation is performed by removing the epitaxial layer other than the region where the transistor is formed by mesa etching.
[0057]
Next, as shown in FIG. 6K, a silicon nitride film SiN is deposited on the high-concentration gate impurity layer 170 by, eg, CVD (Chemical Vapor Deposition) to form an insulating film (mask layer) 180. . Thereafter, etching is performed using a resist of a predetermined pattern as a mask, and an opening 18a is formed in the insulating film 180 for forming a gate impurity region.
[0058]
Next, as shown in FIG. 6L, using the insulating film 180 as a mask, zinc Zn serving as a p-type impurity is diffused in a gas phase, and zinc is diffused from the opening 18a of the insulating film 180, thereby high concentration. Gate impurity regions 20 are formed in the gate impurity layer 170, the stopper layer 16, and the barrier layer 15.
Alternatively, the p-type impurity can be doped by ion implantation. In this case, since the doped impurity needs to be activated by high-temperature heat treatment, vapor phase diffusion is preferable. Here, when vapor phase diffusion is performed, the diffusion depth is controlled by time control.
[0059]
Next, as shown in FIG. 7 (m), Ti / Pt / Au is deposited as a gate metal on the entire surface including the opening 18a of the insulating film 180 by 100 nm / 50 nm / 220 nm, for example, to form a resist having a predetermined pattern. As a mask, the gate metal other than the gate electrode portion is sputter etched to form the gate electrode 21.
At this time, since the high concentration gate impurity layer 170 is formed in the contact portion with the gate electrode 21, good ohmic contact is realized in the metal / semiconductor of the gate portion of the transistor.
[0060]
Next, as shown in FIG. 7N, the insulating film 180 other than the gate electrode portion is etched to form the insulating film 18. This etching is performed until the high-concentration gate impurity layer 170 made of AlGaAs doped with p-type impurities is exposed.
[0061]
Next, as shown in FIG. 8 (o), using the gate electrode 21 and the insulating film 18 as a mask, the high-concentration gate impurity layer 170 is etched until the stopper layer 16 is exposed to form an island-shaped high-concentration gate. Impurity layer 17 is formed.
[0062]
Next, as shown in FIG. 8 (p), the gate electrode 21 and the stopper layer 16 are covered and a silicon nitride film SiN is deposited on the entire surface by, eg, CVD, to form an insulating film 19, and a resist is used. The openings 19a and 19b are provided in the source electrode formation region and the drain electrode formation region.
[0063]
As a subsequent process, for example, gold germanium alloy AuGe, nickel Ni, and gold Au are sequentially deposited on the entire surface of the insulating film 19 including the openings 19a and 19b to perform patterning. Subsequently, the source electrode 22a and the drain electrode 22b are formed by alloying, for example, by a heat treatment at about 400 ° C., and the semiconductor device shown in FIG. 1 can be manufactured.
[0064]
According to the semiconductor device and the manufacturing method thereof according to the above-described embodiment, the high-concentration gate impurity layer 17 is prepared in advance at the substrate preparation stage immediately below the gate electrode 21, so that the barrier layer 15 containing no impurities is obtained. The ohmic contact between the gate electrode 21 and the high-concentration gate impurity layer 17 is improved and the characteristics of the power amplifier device are improved as compared with the case where the p-type impurity is vapor-phase diffused and the gate electrode is formed thereon. I can do things.
[0065]
Further, the semiconductor constituting the channel layer 14 is formed by controlling the depth d of the gate impurity region 20 by vapor phase diffusion and directly controlling the distance d between the gate impurity region 20 and the channel layer 14 immediately below the gate electrode 21. Φbi (built-in potential) between the gate impurity region 20 directly below the gate and the gate impurity region 20 can be increased, and only a positive operating power source can be used.
[0066]
Further, since the high-concentration gate impurity layer 17 made of a semiconductor having a wider band gap than the semiconductor constituting the channel layer 14 is provided between the channel layer 14 and the gate electrode 21, the mutual conductance Gm and the gate / source are provided. The dependency of the inter-capacitance Cgs on the gate voltage Vg is small and the power added efficiency can be increased.
As described above, the controllability of the rising voltage Vth can be improved while maintaining the mutual conductance characteristics of the semiconductor device.
[0067]
FIG.A reference example of a semiconductor device, that is, a high-speed electron mobility transistor is shown. thisIn the semiconductor device, for example, a p-type semiconductor region 25 made of AlGaAs doped with p-type impurities is formed on the entire surface of the high-resistance layer 15c, and the p-type semiconductor region 25 and the high-resistance layer corresponding to the portion immediately below the gate electrode 21 are formed. A gate impurity region 20 is formed by vapor-phase diffusion of p-type impurity such as Zn in 15c. A gate electrode 21 connected to the surface of the gate impurity region 20 is formed, and a source electrode 22a and a drain electrode 22b are formed on the p-type semiconductor region 25 with the gate electrode 21 interposed therebetween. Here, the film thickness and impurity concentration of the p-type semiconductor region 25 are set so as to be depleted in the region between the source electrode 22a and drain electrode 22b and the gate electrode 21. Since the p-type semiconductor region is formed thin, it is alloyed immediately below the source electrode 22a and the drain electrode 22b. Since other configurations are the same as those in FIG. 1 described above, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted. The source electrode 22a and the drain electrode 22b can also be formed on the p-type semiconductor region 25 via an n-type GaAs layer.
In manufacturing, the p-type semiconductor region 25 is formed by epitaxial growth while doping with a p-type impurity. The other layers and electrodes are formed in the same manner as described above.
Also in the semiconductor device of FIG. 9, the gate resistance can be reduced while enabling a single positive power supply operation. In addition, the same effects as the semiconductor device of FIG.
[0068]
BookThe semiconductor device of the invention is not limited to the description of the above embodiment.
For example, the buffer layer 12, the high resistance layer 13c, and the carrier supply layer 13a may be omitted, and a single heterostructure may be formed.
As a p-type impurity for forming the gate impurity region 20, for example, carbon (C) can be used in addition to zinc (Zn).
[0069]
The present invention is applicable not only to GaAs substrates but also to InP substrates. For example, when the substrate 11 is made of InP, the buffer layer 12 is formed of InP to which no impurity is added, and the high resistance layers (13b, 13c, 15b, 15c) are Al to which no impurity is added._xIn_1-xAs (x = 0.4 to 0.5), the channel layer 14 is formed of undoped In_xGa_1-xThe carrier supply layers (13a, 15a) are made of As (x = 0.5 to 0.6) and are n-type Al._xIn_1-xWhat is necessary is just to form by As (x = 0.4-0.5). And Al_XIn_1-XAn AlInAs stopper layer 16 having a different In composition ratio is formed on the As high resistance layer 13c, and an AlInAs or InP island-like high-concentration gate impurity layer 17 containing, for example, a p-type impurity is formed thereon. Form. Thereafter, the gate impurity region 20 is formed by vapor phase diffusion of Zn or C as a p-type impurity, for example. A Ti / Pt / Au gate electrode 21 similar to that described above is formed in the island-like high-concentration gate impurity layer 17 of AlInAs or InP through the opening of the insulating film 18, and the same as described above on the stopper layer 16. A source electrode 22a and a drain electrode 22b are formed by a layer obtained by heat-treating a stacked film of AuGe, Ni, and Au.
In addition, various modifications can be made without departing from the scope of the present invention.
[0070]
According to the present invention, the gate resistance can be reduced while enabling a single positive power supply operation.A semiconductor device can be manufactured.
[Brief description of the drawings]
FIG. 1 embodimentObtained by the manufacturing methodIt is sectional drawing which shows the example of 1 structure of a semiconductor device.
FIG. 2 is a cross-sectional view after forming a carrier supply layer of a first barrier layer in manufacturing a semiconductor device according to the embodiment.
FIG. 3 is a cross-sectional view after the formation of the high resistance layer of the second barrier layer, continued from FIG. 2;
4 is a cross-sectional view after the formation of the second barrier layer, continued from FIG. 3;
5 is a cross-sectional view after the formation of the high concentration gate impurity layer, continued from FIG. 4; FIG.
6 is a cross-sectional view after the formation of the gate impurity region, continued from FIG. 5;
7 is a cross-sectional view after the formation of the gate electrode, continued from FIG. 6;
FIG. 8 is a cross-sectional view after the formation of the insulating film, continued from FIG. 7;
FIG. 9Reference exampleSemiconductor device according toStructureIt is sectional drawing which shows a composition example.
FIG. 10 is a cross-sectional view showing a configuration example of a PHEMT according to a conventional example.
FIG. 11 is a cross-sectional view showing a configuration example of a JPHEMT according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12 ... Buffer layer, 13 ... 1st barrier layer, 13a ... Carrier supply layer, 13b, 13c ... High resistance layer, 14 ... Channel layer, 15 ... 2nd barrier layer, 15a ... Carrier supply layer, 15b, 15c ... high resistance layer, 16 ... stopper layer, 17 ... high concentration gate impurity layer, 18 ... insulating film, 19 ... insulating film, 20 ... gate impurity region, 21 ... gate electrode, 22a ... source electrode, 22b ... drain Electrode 25 ... p-type semiconductor layer 31,41 ... substrate 32,42 ... buffer layer 33,43 ... first barrier layer 33a, 43a ... carrier supply layer 33b, 33c, 43b, 43c ... high resistance Layer, 34, 44 ... channel layer, 35, 45 ... second barrier layer, 35a, 45a ... carrier supply layer, 35b, 35c, 45b, 45c ... high resistance layer, 36 ... cap layer, 37, 47 ... insulation , 38 and 48 ... gate electrode, 39a, 49a ... Source electrode, 39 b, 49b ... drain electrode, 50 ... gate impurity region

Claims (8)

Forming a channel layer;
Forming a first semiconductor layer on the channel layer;
Forming a second semiconductor layer containing a first conductive impurity on the first semiconductor layer;
Forming a mask layer having an opening in a part of the second semiconductor layer;
Using the mask layer as a mask, introducing a second conductive impurity of the same conductivity type as the first conductive impurity into the second and first semiconductor layers to form a gate impurity region;
A method of manufacturing a semiconductor device, comprising: forming a gate electrode on at least the second semiconductor layer exposed in the opening. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed by an epitaxial growth method to which the first conductive impurity is added. In the second and introducing said second conductive impurity into the first semiconductor layer, according to claim 1, wherein introducing said second conductive impurity by vapor-phase diffusion or ion implantation Semiconductor device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive impurity and the second conductive impurity are made of the same material. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the first conductive impurity and the second conductive impurity contain Zn. After the step of forming the first semiconductor layer, a stopper layer having an etching selectivity with respect to the second semiconductor layer is formed, and the second semiconductor layer is formed on the stopper layer,
After the step of forming the gate electrode, using the gate electrode as a mask, leaving the mask layer and the second semiconductor layer formed under the gate electrode, the mask layer formed in another region, and 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the second semiconductor layer by etching until the stopper layer is exposed. The method further comprises a step of forming a source electrode and a drain electrode separately from each other on the stopper layer with the gate electrode interposed therebetween, after the step of removing the mask layer and the second semiconductor layer by etching. A method for manufacturing a semiconductor device according to claim 6. In the step of forming the channel layer, the channel layer is formed of InGaAs,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed of AlGaAs.

Images