JPS6386426A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS6386426A JPS6386426A JP22973786A JP22973786A JPS6386426A JP S6386426 A JPS6386426 A JP S6386426A JP 22973786 A JP22973786 A JP 22973786A JP 22973786 A JP22973786 A JP 22973786A JP S6386426 A JPS6386426 A JP S6386426A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- compound semiconductor
- deposited
- bpsg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 150000001875 compounds Chemical class 0.000 title claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 18
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 37
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910005091 Si3N Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は化合物半導体装置の製造方法に係り、特にＧａ
Ａｓショットキーゲート型電界効果トランジスタ（ＭＥ
ＳＦＥＴ）の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a compound semiconductor device, and particularly relates to a method for manufacturing a compound semiconductor device.
As Schottky gate field effect transistor (ME
SFET) manufacturing method.
（従来の技術）
ＧａＡｓデバイスは高周波増ａ器や発振器などを構成す
る個別半導体素子として広く使われている。(Prior Art) GaAs devices are widely used as individual semiconductor elements constituting high frequency amplifiers, oscillators, and the like.
また最近ではＧａＡｓ高速論理回路やメモリの基本素、
子としても重要な役割を果たしつつある。これらの
ＧａＡｓデバイスにおいては通常イオン注入によっ、
てドーパントをＧａＡｓ基板に打ち込み熱処理を行っ
てｎ型ないしはｐ型の活性層を形成する。例えばｎ型の
場合１代表的なドーパントはＳＬであり、この場合の熱
処理温度は７５０℃〜８５０℃程度必要である。Recently, GaAs high-speed logic circuits and basic elements of memory,
They are also playing an important role as children. In these GaAs devices, ion implantation is usually used to
A dopant is implanted into the GaAs substrate and heat treatment is performed to form an n-type or p-type active layer. For example, in the case of n-type, a typical dopant is SL, and the heat treatment temperature in this case needs to be about 750°C to 850°C.
（発明が解決しようとする問題点）
ＧａＡｓ中にイオン注入されたドーパントを十分活性化
させるためには７５０℃以上で熱処理を行うことが必要
である。このような高温ではＧａＡｓ中のＡｓが解離し
てしまい良好な素子が作製できないので。(Problems to be Solved by the Invention) In order to sufficiently activate the dopants ion-implanted into GaAs, it is necessary to perform heat treatment at 750° C. or higher. At such high temperatures, As in GaAs dissociates, making it impossible to produce a good device.
保護膜を堆積して熱処理を行うのが普通である。It is common to deposit a protective film and perform heat treatment.
この保護膜としてはＣＶＤ Ｓｉｎ、膜が広く知られて
いるが、アニール時ＧａＡｓからＧａが５ｉｎ２膜を通
して外部拡散するのが問題である。リンやボロンをＳｉ
ｎ。CVD Sin film is widely known as this protective film, but the problem is that Ga from GaAs diffuses out through the 5in2 film during annealing. Phosphorus and boron are Si
n.
にドーピングして高温でリフローするようにしたＰＳＧ
膜、 ＢＰＳＧ膜の場合にも、 このような事情は変ら
ない、 ＲＦプラズマ成長によるＳＬ３Ｎ、膜もＧａ
Ａｓのアニール保護膜に用いられる。 Ｓｉ３Ｎ４膜
の場合はＧａＡｓからのＧａやＡｓの外部拡散は全くな
く、そのブロッキング効果は優れたものがある。しかし
、膨張係数がＧａＡｓと異なるこの膜をプラズマ成長な
どのような比較的低温で成長した場合、高温アニール時
、膜と結晶間での大きな応力のため、膜に気泡やクラッ
クが発生、膜ははげやすくなる。PSG is doped and reflowed at high temperature.
This situation does not change in the case of the BPSG film, SL3N film grown by RF plasma, and the film is also made of Ga.
Used as an annealing protective film for As. In the case of the Si3N4 film, there is no outward diffusion of Ga or As from GaAs, and its blocking effect is excellent. However, when this film, which has a different coefficient of expansion than GaAs, is grown at a relatively low temperature such as by plasma growth, bubbles and cracks occur in the film due to the large stress between the film and the crystals during high-temperature annealing. It becomes easy to bald.
本発明は上記の如き難点を解決し、応力が小さくしかも
ＧａＡｓ基板からＧａやＡｓの外部拡散を抑制できるＧ
ａＡｓデバイスの製造方法を提供することを目的とする
。The present invention solves the above-mentioned difficulties and provides a G
The present invention aims to provide a method for manufacturing an aAs device.
（発明の構成〕
（問題点を解決するための手段）
本発明はＧａＡｓ基板にイオン注入を行い、保護膜を堆
積して熱処理することにより活性層を形成する工程を含
むＧａＡｓデバイス製造方法において、前記保ｉｌｌ膜
としてＰＳＧないしはＢＰＳＧＩＩｌＫを下層に、プラ
ズマ５ｉ３Ｎ４ ｇを上層に堆積した積層膜を用いるこ
とを特徴とする。(Structure of the Invention) (Means for Solving the Problems) The present invention provides a GaAs device manufacturing method including a step of implanting ions into a GaAs substrate, depositing a protective film, and forming an active layer by heat treatment. The present invention is characterized in that a laminated film in which PSG or BPSG IIlK is deposited as a lower layer and plasma 5i3N4g is deposited as an upper layer is used as the illumination film.
（作 用）
本発明によれば、 プラズマ５ｘａＮ４ｖＡとＧａＡｓ
基板との間に高温でリフローする膜を極く薄くはさんで
やることにより、 ＧａＡｓ基板とプラズマＳｉ、 Ｎ
、膜の膨張係数の差から生じる応力を緩和することがで
きるので、 ＧａＡＳからＧａやＡｓの外部拡散を抑止
したままはがれやクラックの生じない保護膜でアニール
することが可能になる。(Function) According to the present invention, plasma 5xaN4vA and GaAs
By sandwiching an extremely thin film that reflows at high temperature between the substrate and the substrate, the GaAs substrate and plasma Si, N
Since the stress caused by the difference in expansion coefficients of the films can be alleviated, it becomes possible to anneal with a protective film that does not peel or crack while suppressing the external diffusion of Ga and As from GaAS.
（実施例）
以下第１図（８）〜（Ｃ）を参照して本発明の詳細な説
明する。(Example) The present invention will be described in detail below with reference to FIGS. 1(8) to 1(C).
まず第１図（ａ）に示すように半絶縁性ＧａＡｓ基板１
１にＳＬ十のイオン注入により、イオン注入層１２を形
成する０次に第１図（ｂ）に示すようにＢＰＳＧ膜１３
を７００人、 ＣＶＤ法により堆積する。 ＢＰＳＧ膜
のＢ′ａ度。First, as shown in FIG. 1(a), a semi-insulating GaAs substrate 1
As shown in FIG. 1(b), an ion-implanted layer 12 is formed by ion implantation of SL0 in 1. As shown in FIG.
700 people, deposited by CVD method. B'a degree of BPSG film.
Ｐ濃度は６％、７％とし、７００℃ですでにリフローが
始まるような条件を用いる０次に第１図（ｃ）に示すよ
うにプラズマＳｉ、 Ｎ４膜１４を２０００人堆積した
後３Ｎ２雰囲気中で８００℃６０分間の熱処理を行う。The P concentration was set to 6% and 7%, and the conditions were such that reflow already started at 700°C.After depositing 2000 plasma Si and N4 films 14 as shown in FIG. 1(c), a 3N2 atmosphere was used. Heat treatment is performed at 800° C. for 60 minutes in the inside.
第２図は上層膜の５ｉ３Ｎｓ ［の膜厚を２０００人に
固定し、下層のＢＰＳＧ膜１３を１００人、３００人、
７００人。In Figure 2, the thickness of the upper layer 5i3Ns is fixed at 2000, and the thickness of the lower BPSG film 13 is 100, 300,
700 people.
２０００人、 ５０００人と変化させて、ｎ型活性層の
シート抵抗を測定したものである。イオン注入条件は、
１８０ＫｅＶの３ Ｘ １０’″ａ１−”とした、 Ｂ
ＰＳＧＩＩＩ １００人では。The sheet resistance of the n-type active layer was measured by changing the number of people to 2,000 and 5,000 people. The ion implantation conditions are
3 x 10'''a1-'' of 180 KeV, B
PSGIII 100 people.
膜にクラックを生じ、３００人では気泡がＩＩ察された
。また膜厚を２０００Å以上にすると、ＢＰＳＧＩＩ中
へのＧａの拡散によると想われるシート抵抗の減少が見
られた。従ってＳｉ、 Ｎ４膜と基板の間にはさむ膜は
少なくとも１０００Å以下である必要がある。Cracks occurred in the membrane, and bubbles were observed in 300 people. Further, when the film thickness was increased to 2000 Å or more, a decrease in sheet resistance was observed, which was thought to be due to the diffusion of Ga into BPSGII. Therefore, the thickness of the film sandwiched between the Si or N4 film and the substrate must be at least 1000 Å or less.
第３図はＳｉ、 Ｎ、膜と基板の間にはさむ膜として。Figure 3 shows Si, N, as a film sandwiched between the film and the substrate.
５ｉｎ２膜を用いた場合と、ＢＰＳＧ膜を用いた場合の
キャリア濃度プロファイルを比較したものである。The carrier concentration profiles are compared when a 5in2 film is used and when a BPSG film is used.
熱処理条件などは前と同じである。各々の場合について
上層Ｓｉ、 Ｎ、膜の膜厚を１０００人、 ２０００人
。The heat treatment conditions etc. are the same as before. In each case, the thickness of the upper layer Si, N, and film was 1000 and 2000.
４０００人と変化させ、Ｓ１０．膜とＢＰＳＧ膜は５０
０人一定とした＊ Ｓｉｏ、膜を用いた場合、キャリア
濃度プロファイルにＳｉ３Ｎ、膜の膜厚依存性が認めら
れるのに対し、ＢＰＳＧ膜を用いた場合にはＳｉ、 Ｎ
４膜厚依存性が小さくなっている。これはＢＰＳＧ膜が
上層の８１Ｊ４膜の応力を緩和していることを示してい
るためと考えられる。Changed to 4000 people, S10. The membrane and BPSG membrane are 50
*When using a Sio film, the carrier concentration profile is dependent on Si3N and film thickness, whereas when using a BPSG film, Si, N
4. Dependency on film thickness is small. This is considered to be because the BPSG film relaxes the stress of the upper 81J4 film.
以上に説明したように本発明によれば、ＧａＡｓデバイ
スの熱処理保護膜としてキャップ効果や電気的特性に優
れたものを得ることができる。As explained above, according to the present invention, it is possible to obtain a heat-treated protective film for GaAs devices that has excellent capping effects and electrical characteristics.
第１図は本発明の一実施例を説明する為の工程断面図、
第２図及び第３図は本発明の効果を活性層の電気的特性
により説明する為の図である。
１１・・・半絶縁性ＧａＡｓ基板
１２・・・イオン注入層
１３・・・ＢＰＳＧ膜
１４・・・Ｓｉ３Ｎ、膜
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
Ｃ（ａＩＱｓ遵猥
第１図
Ｂｐｓｒｒ腋屡（スフ
第２図
０ ０、Ｉ Ｑ２ ０．ｊ Ｏ，４−０，５
０６０，７Ｄ五Ｐ７Ｈ（％ａン
第 ３ 図FIG. 1 is a process sectional view for explaining one embodiment of the present invention.
FIGS. 2 and 3 are diagrams for explaining the effects of the present invention using the electrical characteristics of the active layer. 11... Semi-insulating GaAs substrate 12... Ion implantation layer 13... BPSG film 14... Si3N, film agent Patent attorney Nori Chika Yudo Kikuo Takehana C (aIQs Junshi Figure 1 Bpsrr Armpit (Sufu 2 0 0, I Q2 0.j O, 4-0, 5
060,7D5P7H (%a Figure 3
Claims (4)
った後、これに保護膜を堆積して熱処理を行う工程を含
む化合物半導体装置の製造方法において、前記保護膜に
ＰＳＧ膜ないしはＢＰＳＧ膜とＳｉ＿３Ｎ＿４膜の二重
層を用いることを特徴とする化合物半導体装置の製造方
法。(1) In a method for manufacturing a compound semiconductor device, which includes a step of implanting dopant ions into a compound semiconductor substrate, depositing a protective film thereon, and performing heat treatment, the protective film includes a PSG film or a BPSG film and a Si_3N_4 film. 1. A method for manufacturing a compound semiconductor device characterized by using a double layer of.
、上層がＳｉ＿３Ｎ＿４膜であることを特徴とする特許
請求の範囲第１項記載の化合物半導体装置の製造方法。(2) The method for manufacturing a compound semiconductor device according to claim 1, wherein the protective film has a PSG or BPSG film as a lower layer and a Si_3N_4 film as an upper layer.
リフローすることを特徴とする特許請求の範囲第２項記
載の化合物半導体装置の製造方法。(3) The method for manufacturing a compound semiconductor device according to claim 2, wherein the PSG or BPSG film is reflowed at a temperature of 700° C. or higher.
であることを特徴とする特許請求の範囲第１項記載の化
合物半導体装置の製造方法。(4) The method for manufacturing a compound semiconductor device according to claim 1, wherein the PSG or BPSG film has a thickness of 1000 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22973786A JPS6386426A (en) | 1986-09-30 | 1986-09-30 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22973786A JPS6386426A (en) | 1986-09-30 | 1986-09-30 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6386426A true JPS6386426A (en) | 1988-04-16 |
Family
ID=16896897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22973786A Pending JPS6386426A (en) | 1986-09-30 | 1986-09-30 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386426A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218009A (en) * | 1991-10-30 | 1993-08-27 | Samsung Electron Co Ltd | Formation method of interlayer insulating film of semiconductor device |
| US5652187A (en) * | 1991-10-30 | 1997-07-29 | Samsung Electronics Co., Ltd. | Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment |
-
1986
- 1986-09-30 JP JP22973786A patent/JPS6386426A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218009A (en) * | 1991-10-30 | 1993-08-27 | Samsung Electron Co Ltd | Formation method of interlayer insulating film of semiconductor device |
| US5405489A (en) * | 1991-10-30 | 1995-04-11 | Samsung Electronics Co., Ltd. | Method for fabricating an interlayer-dielectric film of a semiconductor device by using a plasma treatment prior to reflow |
| US5652187A (en) * | 1991-10-30 | 1997-07-29 | Samsung Electronics Co., Ltd. | Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment |
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