JPS6384210A - Signal processing unit - Google Patents

Abstract

PURPOSE:To contrive to increase the frequency shift without widening the transmission band by using a pre-emphasis circuit whose amplitude characteristic is a function of angular frequency and whose phase characteristic is linear while a ladder circuit network is constituted by an inductance and a capacitance. CONSTITUTION:A signal Vi inputted from a terminal 1 enters a delay circuit 10 and basic circuit 20. The circuit 10 retards a time T to the signal Vi and gives the result to an adder circuit 40. The signal Vi given to the circuit 20 is subject to filtering processing, amplified by K time in a coefficient circuit 30 and the result is given to the circuit 40, and an output Vo is outputted from a terminal 2. A transfer function H0(S) of a signal processing unit 100 is expressed as H0(S)=Vo/Vi=(1+K.coshST).e<->ST. The circuit 20 has an impedance circuit Z21, a resistor R123 or an admittance circuit Y22 and a resistor R224. The circuit 21 or 22 is a two-terminal circuit network realizing approximately a hyperbolic tangent function tanhST and is realized by an LC ladder circuit network.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a device for converting a signal such as a video signal into a signal having desired frequency characteristics, and particularly relates to a device for converting a signal such as a video signal into a signal having desired frequency characteristics, and particularly for improving signal S/N and waveform distortion in a transmission system. The present invention relates to a signal processing method and apparatus suitable for improving.

[Conventional technology]

In recording and reproducing devices such as video tape recorders and video disk players that record and reproduce video signals, and in signal transmission media such as Eiya Broadcasting, it is common to record and reproduce or transmit video signals using frequency modulation (FM) L. It is used in many ways. In order to prevent signal S/N degradation that occurs in such FM transmission systems, the high-frequency components of the video signal are emphasized (pre-emphasis) before frequency modulation of the video signal.
However, a signal processing method in which high frequency components are suppressed (de-emphasis) after demodulating an FM signal has been commonly used.

In such a signal processing method, in order to faithfully transmit the signal, the transfer function of the pre-emphasis circuit, Gl(
S), the transfer function of the de-emphasis circuit is 02 (S)
Then, the following equation must be satisfied regardless of frequency.

G1(S) x G2(S) = k
(1) However, S=jω, and ω is the angular frequency of the signal, which is a constant.

If the formula (1) is not satisfied, the recorded/reproduced or transmitted signal will have phase distortion and amplitude distortion, and the signal will not be recorded, reproduced, or transmitted faithfully.

As pre-emphasis circuits and de-emphasis circuits that satisfy equation (1), circuit networks each having a transfer function have been widely used since they can be easily and economically realized using resistors and capacitors. However, this conventional method does not take into account the linearity of the phase characteristics of the pre-emphasis circuit and de-emphasis circuit.

Regarding the method of improving the phase characteristics of the above-mentioned pre-emphasis circuit, please refer to JP-A-53-131814 and JP-A-53-
131815 and Japanese Patent Publication No. 61-8632 are known, but these do not give sufficient consideration to the de-emphasis system that satisfies equation (1).

Furthermore, regarding the method of improving the S/N of a signal using a pre-emphasis circuit and a de-emphasis circuit that can be expressed by the following equation, Japanese Patent Laid-Open No. 59-221126 and Japanese Patent Laid-Open No. 60-60
7279 is known, but none of these takes into consideration the linearity of the phase characteristics of the pre-emphasis circuit and the de-emphasis circuit themselves in equation (2).

[Problem that the invention seeks to solve]

In the above conventional technology, as is clear from equation (2), the linearity of the phase characteristics of the pre-emphasis circuit is poor. Significant levels of overshading and undershoot occur only in the direction. Therefore, when a pre-emphasized signal is frequency modulated, the amount of frequency deviation increases by the amount of overshading and undershoot, and the occupied band of the FM signal widens, resulting in a problem that a wider transmission band is required. was there.

In recording and reproducing apparatuses such as video tape recorders and video disc players, there is naturally a limit to the signal band that can be recorded on the medium. In the conventional pre-emphasis method described above, a large peak waveform in one direction occurs in the high frequency components of the signal. Therefore, for overshoot, F
The instantaneous frequency of the M signal becomes extremely high, and due to the band limitations of the above-mentioned media, high frequency signals cannot be reproduced at a sufficient level. Horizontal drawing noise occurs). Furthermore, for undershading, the instantaneous frequency of the FM signal is extremely reduced, and so-called spectral folding causes beat-like noise at the image contour, significantly deteriorating the reproduced image quality. To prevent this, generally
Forcibly clip (amplitude limit) the overshoot waveform and undershade waveform of the signal after pre-emphasis. However, because a part of the signal is lost due to this waveform clipping, equation (1) does not hold, and there is a problem in that the reproduced waveform is greatly distorted. Furthermore, in order to prevent these problems, methods are generally used in which the amount of pre-emphasis is reduced or the amount of frequency shift is reduced. However, even if these methods are used, although the waveform distortion is improved, the essential problem remains that the S/N is degraded accordingly.

The purpose of the present invention is to (1) eliminate the problems of the prior art described above;
The formula satisfies the equation, the linearity of the phase characteristics is good, there is no amplitude distortion or phase distortion, and the pre-emphasis amount is large (
An object of the present invention is to provide a pre-emphasis circuit and a de-emphasis circuit that can improve the S/N of a signal.

[Means for solving problems]

The above purpose is to reduce the angular frequency ω (S=j
hyperbolic tangent function tanh (ST) for ω).

(T is delay time) We focused on the fact that it is possible to realize an impedance circuit Z and an admittance circuit Y that have characteristics, and using this impedance circuit Z or admittance circuit Y, we can create an amplitude characteristic that is a function of the angular frequency ω (1 + 1 ■ ωT). ,
(-1<K<O), and the phase characteristic is IJ near (i.e.,
A pre-emphasis circuit (or a de-emphasis circuit when O<K<1) with a flat group delay characteristic is configured, and the impedance circuit Z or admittance circuit Y is also used to create a pre-emphasis circuit (or a de-emphasis circuit when O<K<1) whose amplitude characteristic is equal to that of the pre-emphasis circuit. The inverse function of the amplitude characteristic of 1/(1+−(2)ωT), (
-1<K<O) and a linear phase characteristic de-emphasis circuit (or a pre-emphasis circuit when O<K<1) is configured to realize a signal processing device that fully satisfies Equation 11 above. This can be achieved by

Furthermore, this can also be achieved by constructing the pre-emphasis circuit and de-emphasis circuit with digital filters using digital signal processing means.

[Effect]

The above pre-emphasis circuit has an amplitude characteristic of (1+ to -a
mωT), (-1<K<O) or)! 1/(1+ to -
Since auωi (o<K<1), the level of the mid-range component or high-range component of the signal input to this pre-emphasis circuit is emphasized, and since its phase characteristic is near, the level of the input signal is A waveform with waveform symmetry maintained is output. Specifically, the above-mentioned rectangular pulse box waste ratio f to 1
Before and after each edge of the rising edge of the falling edge of the falling edge, a pre-shade and a boost shoot occur in an oddly symmetrical manner at approximately the same peak level.

In this way, the high-frequency components of the input signal are almost evenly distributed as preshoots and boostshoots before and after each rising and falling edge of the signal due to emphasis, so the peak value (peak vs. peak value) is significantly smaller than that of the conventional emphasis method in which the phase characteristic expressed by the above equation (2) is not linear. Therefore, in the case of FM transmission, the transmission band can be narrowed, and the generation of beat noise due to the above-mentioned inversion phenomenon due to overmodulation and folding of the spectrum can be suppressed. Furthermore, since there is no need to forcefully clip the waveform after 2/phasis, the amplitude characteristic becomes an inverse function of the amplitude characteristic of the pre-emphasis circuit 1/(1+to 1■ωT), (-1<K<O' ) or (1+Kt■ω
T), (0<K<1) and the above-mentioned de-emphasis circuit having a linear phase characteristic makes it possible to obtain a reproduced signal that does not cause waveform distortion and has an improved S/N ratio.

〔Example〕

Examples of the present invention will be described in detail below.

FIG. 1 shows a signal processing device 100 showing an embodiment of the present invention.
FIG. In FIG. 1, 1 is a signal input terminal, 2 is a signal output terminal, 10 is a delay circuit that delays the signal by a time T (T is a constant), and 20 is a signal processing device 100.
30 is a coefficient circuit that amplifies the signal by a factor of 2 (K is a constant), and 40 is an addition circuit.

The signal Vi input from the terminal 1 is input to the delay circuit 10 and the basic circuit 20. In the delay circuit 10, the signal Vi
is delayed by a time T, and this delayed signal is input to the adder circuit 40. As is well known, the transfer function D1(S) of the delay circuit 10 is expressed by the following equation.

Ih (S) = e-” ・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・(
3) On the other hand, the signal Vi input to the basic circuit 20 is subjected to a predetermined filtering process. .

The output signal Vo of this basic circuit 20 is the coefficient circuit 3.
0, the signal is amplified twice and input to the adder circuit 40.

The transfer function Fl(S) of the basic circuit 20 is given by the following equation.

The adder circuit 40 adds the output signal of the delay circuit 10 and the output signal of the coefficient circuit 30, and the output signal of the adder circuit 40 is output to the terminal 2. Assuming that Vo is the signal output to terminal 2, the transfer function Ho (81) of the signal processing device 100 is given by the following equation.

O HO (S) ” vt = Dt (8) + K-F
1(St= (1+ to −CosbST) ・e−”
...(5) Figure 2 shows the basic circuit 20 above.
1 is a four-terminal network showing an embodiment of the present invention. In the same figure (a), 21 is an impedance circuit z, 23 is a resistor R1-
11-There is. Also in the same figure (in AI, 24 is the resistor R2
, 22 is an admittance circuit Y. The impedance circuit 2 and the admittance circuit Y are both two-terminal circuit networks that approximately realize the hyperbolic tangent function -hST, and when the reference resistance RO is set, it is given by the following equation.

The two-terminal circuit networks 21 and 22 that are approximately realized with these values of 2 and Y are shown in FIG. LC ladder networks of configurations are known. For reference, in Figure 3 (α), (A), the above (6)
The values of inductance L and capacitance C to satisfy the equations are given by the following equations. For impedance 2 in FIG. 3(α), for admittance Y in FIG. 3(b), where n is an integer greater than or equal to 1.

In the four-terminal network 20 of FIG. 2(a), the input voltage v
The transfer function F1(S) of the output voltage v2 with respect to V1 is expressed by the following formula using the above formula (6).

Here, if RO/R1=1, the equation (9) becomes the above (4
), and this transfer function can be realized. Similarly, the four-terminal network 20 of FIG.
The transfer function F'1(S) is expressed by the following equation using the above equation (6).

Here, if R2/R,=1, the formula (lO) becomes the above (
It matches the transfer function F1(S) of equation 4), and this transfer function can be realized.

Therefore, by using the four-terminal network 20 realized by the embodiment of FIG. 2, the configuration shown in FIG.
The signal processing device 100 having the transfer function Ha (81
can be realized.

The frequency characteristics of the signal processing device 100 shown in FIG. 1 determined by the transfer function Ho (S) in equation (5) are shown in FIG. 4d From the frequency characteristics shown in FIG. When -1<K<O, it operates as a pre-emphasis circuit that emphasizes the middle or high frequency components of the input signal Vi, and when 0<K<1, the input signal V
It is clear that the circuit operates as a de-emphasis circuit that suppresses the middle or high frequency components of i.

Next, in the signal processing device 100, the coefficient circuit 30
FIG. 5 shows a response waveform to a rectangular pulse input signal Vi when the circuit is operated as a pre-emphasis circuit with the coefficient K of -1<K<O. ) is the input signal V
The waveform of i is shown, and (b) of the same figure shows the waveform of the output signal vO. In this manner, the response waveform to a rectangular pulse signal produces a preshoot and a boost shoot oddly symmetrically at approximately the same peak level before and after each rising and falling edge of the signal.

In other words, the high-frequency components of the input signal Vi are almost equally distributed between the pre-shoot and the post-shoot due to the emphasis.
The peak-to-peak value of the output signal Vo is smaller than that of the conventional emphasis method expressed by the above equation (2).

Therefore, the signal Vo that is processed and output in this way is
When transmitting (or recording and reproducing) by frequency modulating the frequency, the amount of frequency deviation can be suppressed to a small value, so the occupied band of the FM signal can be narrowed accordingly, making it difficult to be subject to restrictions on the transmission band.

Furthermore, since overmodulation can be prevented, the occurrence of spurious due to inversion phenomena and spectrum folding can be suppressed, and there is no need for forced clipping of the waveform, so that waveform distortion can be prevented.

Next, an embodiment of a signal processing device 200 that can be applied complementary to the signal processing device 100 described above to almost completely match pre-emphasis characteristics and de-emphasis characteristics and faithfully restore the original signal. A block diagram of this is shown in FIG.

In the figure, 3 is a signal input terminal, 4 is a signal output terminal, 10 is a delay circuit that delays a signal by a time T, 11 is a delay circuit that delays a signal by a time 2T, and 12 is a signal delay circuit for a time 3
T delay circuit, 20a, 20,6.

20+? is the transmission of the above equation (4), which is the same as the basic circuit 20 in FIG.

Basic circuit realizing function F1(S), 30α, 30b
, 30C is a coefficient circuit that amplifies the signal by a factor of 2, similar to the coefficient circuit 30 in FIG. 1, and 50 is an adder circuit.

If the transfer function of the output signal Vo to the input signal Vi of the signal processing device 200 is Hl(S), then the transfer function is Hl(S).
o (S), in order to faithfully restore the signal processed by the signal processing device 100 to the original signal, the transfer function Hh(S) must satisfy the following equation, as is clear from equation (1). It must be a function that

Ho(Sl x Hl(S) = k...
・・・・・・・・・・・・・・・・・・・・・・・・(1) The phase characteristic that satisfies equation (11) is IJ. Assuming that the air transfer function H1(S), m is 0. Considering the above integers, from equations (5) and (121), H□(81X
Hl (S) = e-(-” 1)” −
”...(13). Therefore, the transfer function Ho (S
The signal processed by the signal processing device 100 having a transfer function H1 (Sl) and further processed by the signal processing device 200 having a transfer function H1 (Sl) has a constant value of [(m+1)T] with respect to the input signal of the signal processing device 1000. There is no phase distortion except for the delay time, and the amplitude characteristic is constant regardless of the frequency, so there is no response amplitude distortion.Therefore, by complementary application with the signal processing device 100, the pre-emphasis characteristic and the It is clear that the transfer function H1 (81) of the signal processing device 200, which can almost completely match the emphasis characteristics and faithfully restore the original signal, should be a function expressed by equation (121).

Expanding the transfer function Ht (8) of the above (1'lJ formula) into a polynomial, Hl (3) = e-msTΣ(-1)'-1
-(K-coshST)'-' -------(1
411 proverbs. Ignoring the (m+2)th term and subsequent terms, the transfer function H1
(S) is expressed as effective terms up to the (m+1)th term. - As an example, if the 5th term (m=3) and subsequent terms are ignored and the transfer function Hh(S) is expressed with up to the 4th term as effective terms, the following equation is obtained.

Hl(S)=e −(K-cashST-e)・
eThe block diagram of the signal processing device 200 shown in FIG.
This realizes the above equation (!6).

That is, the signal Vi input from the terminal 3 is sent to the delay circuit 12.
and is input to the basic circuit 20α. The delay circuit 12 delays the signal Vi by 3T, and this delayed signal is input to the non-inverting input terminal of the adder circuit 50.

The signal Vi input to the basic circuit 20α is
After a predetermined filtering process is performed at α, the signal is amplified twice by the coefficient circuit 30α. The signal Va output from the coefficient circuit 3oα is delayed by 2T in the delay circuit 11, and then input to the inverting input terminal of the adder circuit 50 and also input to the basic circuit 20b. The signal Va input to the basic circuit 2OA- is subjected to a predetermined filtering process and then amplified twice by the coefficient circuit 30b. Coefficient circuit 30
The signal vb output from b is delayed by a time T in the delay circuit 10, and is input to the non-inverting input terminal of the adder circuit 5o, as well as to the basic circuit 20c. The signal vb input to the basic circuit 20C is subjected to a predetermined filtering process, and further amplified twice by the coefficient circuit 30C, and then input to the inverting input terminal of the adder circuit 5o. Addition circuit 5o
In each of the above-mentioned signals inputted to Vl e
Va, and the output signal from the delay circuit 11 input to the inverting input terminal of the adder circuit 500 and the coefficient circuit 30
If the output signals from c are respectively V2 + V4,
In the adder circuit 50, ■o=vl-v2+v3-v4...
...(17) is performed, and the output signal Vo of this adder circuit 50 is output to the terminal 4.

Transfer functions D2 (S), D of delay circuits 11 and 12
It is well known that a (S) is each. Further, the transfer function DI(S) of the delay circuit 10 is given by equation (3). Therefore, the adder circuit 50Vc input signal Vl #V2 e v
Since the signal processing device 200 in FIG.
Transfer function Hh(
S) is given by the following equation from the above equations 07) and (19).

Hl(S) =ΔL i = Da(S)−K−F 1(S)・D2(S)+
(K-Fl(S))・Dl(S)-(K-Fx(S))
3...-...Scream...Scream...(3)) Furthermore, the above formula (2)) is converted into (3), (4), (1B)
Expressed using the formula, Hl(Sl=e −(K−ccg
hsT-e)-e, which matches the above equation (16).

As described above, in the signal processing device 200 of FIG.
The transfer function H1(S) (4 effective terms) in equation 6) can be realized. In addition, in general, the transfer function H1(S
t (number of effective terms (m+1) terms) can be realized with a circuit configuration similar to that shown in FIG.

Therefore, the signal processing device 200 of FIG.
The transfer function H1(S) in equation 2) can be approximately realized, and by complementary application to the signal processing device fIL100 shown in Fig. 1, the pre-emphasis characteristics and de-emphasis characteristics can be almost completely matched. The original signal can be correctly restored.

FIG. 7 shows the frequency characteristics of the signal processing device 2000.

From the frequency characteristics shown in FIG. 7, the signal processing device 200 operates as a de-emphasis circuit that suppresses the mid-range or high-range components of the input signal Vi when -1<K<00, with K=0 as the boundary. When O<K<1, the input signal Vi
It is clear that the circuit operates as a pre-emphasis circuit that emphasizes the mid-range or high-range components.

Here, in the signal processing device 100 of FIG. 1, the value of the coefficient of the coefficient circuit 30 is set as −1<K<0, and the signal processing device 100 is operated as a pre-emphasis circuit, as described in 5 above. , in the signal processing device 200 of FIG.
, coefficient circuit 304, 3(>b, by matching the value of the coefficient of aoc with the value of the coefficient of the coefficient circuit 30, -1<
K<0 is determined, and the signal processing device 200 is operated as a de-emphasis circuit. Then, after pre-emphasizing the signal to be transmitted (or recorded and reproduced) by the signal processing device 100, FM modulated and transmitted (or recorded), and after FM demodulating the received signal (or reproduced signal), If the system is configured so that the upper end signal processing device 200 performs de-emphasis to restore the original signal, the overall transfer characteristic of this transmission system is expressed by the above equation (5) and (12).
From equation 1, it is given by the following equation.

Ho(S) X Hl(S) = e-”
=-(22) That is, the overall transfer characteristic of this transmission system only has a constant (4T) delay time, and the phase characteristic is IJ
=A, and no response phase distortion occurs, and since the amplitude characteristics are constant regardless of frequency, no response amplitude distortion occurs. Therefore, in this transmission system,
The signal can be faithfully transmitted without waveform distortion, and the S/N ratio can be improved by suppressing noise received on the transmission path in accordance with the amount of emphasis corresponding to the value of the coefficient.

Further, in the signal processing device 100 of FIG. 1, the values of the coefficients of the coefficient circuit 30 are set as 0<K<1, and while the signal processing device 100 is operated as a de-emphasis circuit,
In the signal processing device 200 of FIG. 6, the coefficient circuit 30α
, -30b, and 3oC are made to match the values of the coefficients of the coefficient circuit 30 to determine O<K<1, and the signal processing device 200 is operated as a pre-emphasis circuit. Then, the signal to be transmitted (or recorded/reproduced) is pre-emphasized by the signal processing device 200, FM modulated and transmitted (or recorded), and the received signal (or reproduced signal) is FM demodulated. Even if a system is constructed such that the signal processing device 100 performs de-emphasis to restore the original signal, the overall transfer characteristic of this transmission system is given by the above equation (3), so the signal processing device 100 As in the case where a transmission system is constructed by operating the signal processing device 200 as a pre-emphasis circuit and the signal processing device 200 as a tie-emphasis circuit, the signal can be transmitted faithfully without waveform distortion, and the emphasis can be adjusted according to the value of the coefficient. According to the amount, the noise received on the transmission path can be suppressed and the S/N can be improved.

As described above, by complementary application of the signal processing device 100 shown in FIG. 1 and the signal processing device 200 shown in FIG. 6, it is possible to almost completely match the pre-emphasis characteristics and the de-emphasis characteristics. can. The waveform pre-emphasized by these methods is shown in Figure 5.'5K.

By emphasizing the high-frequency components of the signal, the preshoot and postsee2N)K are evenly distributed so that the peak-to-peak value of the signal is
This is smaller than the conventional emphasis method shown in equation (2). In other words, assuming that the peak-to-peak value of the high-frequency emphasized signal, which is determined by conditions such as the band of the transmission path, is constant, the emphasis method of the present invention can further increase the amount of emphasis compared to the conventional method. This has the effect of improving the S/N by that much.

The easiest way to increase this amount of emphasis is to increase the absolute value IK+ of the above coefficient, but the conventional pre-emphasis method having the transfer functions Gl(S) and 02(S) of equation (2) The circuit and the de-emphasis circuit may be used together with the signal processing apparatuses 100 and 200 of the present invention described above. Specifically, the signal processing device 100 in FIG.
When operating as a pre-emphasis circuit and complementarily operating the signal processing device 200 of FIG. 6 as a de-emphasis circuit, the transfer function 01(
A conventional pre-emphasis circuit having S) is connected in cascade with the signal processing circuit 100, and the transfer function 02 of equation (2) is
(S) is configured by connecting a conventional de-emphasis circuit with the signal processing device 200 in series. Similarly, when the signal processing device 100 in FIG. 1 is operated as a de-emphasis circuit, and the signal processing device 200 in FIG. 6 is operated as a pre-emphasis circuit in a complementary manner, the equation (2) is A conventional pre-emphasis circuit having a transfer function 01(S) is connected in series with the signal processing device 200, and a conventional de-emphasis circuit having a transfer function 02(S) of equation (2) is connected to the signal processing device 100. Consists of cascading connections. According to the above configuration, (2
) By setting the time constants τl and τ2 of the equation to relatively large values, the conventional pre-emphasis circuit with the transfer function Gl(S) can be used mainly for emphasizing the low frequency range of the signal, and can be used as a pre-emphasis circuit. The operated signal processing device 100 or 200 can be used mainly for emphasizing the middle or high frequencies of a signal, and the S/N ratio can be improved over a wide frequency range without waveform distortion.

In the above embodiment, the transfer function Ht(S) of equation (12) is used as a device that approximately realizes the transfer function Ht(S) of equation (12).
We used the signal processing device 200 shown in FIG. 6 that expands t(S) into a polynomial and realizes the transfer function H1(S) of equation (16) with up to the fourth term as effective terms. A signal processing device that realizes a fixed transfer function H1(S) with up to m+1) terms as effective terms can be realized with a circuit configuration similar to the signal processing device 200 in FIG. It is also possible to use a signal processing device that realizes effective terms up to the number of effective terms.It should be noted that a signal processing device that realizes more effective terms can more accurately realize the transfer function H1(S) of equation 121, Needless to say, it is possible to match the pre-emphasis characteristics more completely than Dien77sis4!HI.
The constant and the value of T in the transfer function H1(S) of the above equation (15) with terms up to m+1) as effective terms are expressed as (
It is possible to improve the degree of approximation of the transfer function H1 (81) in the above equation (15) by changing ° and T'&C to appropriate constants without necessarily matching the value in the transfer function H1 (S) in the equation (12). Even with a small number of effective terms, it is possible to strictly realize the fixed transfer function H1(S).

- As an example, K = -0,50, T = 125 n
m, and the number of effective terms is 4 (m=3), the above constant and the value of T in the transfer function H1(S) of the above (1φ equation) are respectively '= -0,49, T'='140nsI!
By changing to le, the transfer function Fh(S) of the above equation (16) and the transfer function Ht(S) of the above equation 6i can be made to match even more.

Furthermore, in all of the above embodiments, the basic circuit 20 of FIG.
Although a case has been shown in which the basic circuit 20 is constructed using an analog processing means using the LC ladder circuit network shown in FIG. It may also be configured with a so-called digital filter.

FIG. 8 shows an embodiment of a digital processing type basic circuit 20D in which the basic circuit 20 shown in FIG. 1 is constructed of a digital filter. In the figure, 5 is a signal input terminal;
6 is a signal output terminal, 60 is an A/D converter, 70 is a digital filter that realizes a transfer function F 1 (Z3, which will be described later), and 80 is a D/A converter.

The signal Ei inputted from the terminal 5 is sequentially converted from an analog signal to a digital signal at the sampling period To in the A/D converter 60, and the output signal Ei' is inputted to the digital filter 70. Digital filter 7
The signal Eo' subjected to a predetermined filtering process at 0 is D/
The signal is input to the A converter 80 and converted from a digital signal to an analog signal. The output signal Eo of this D/A converter 80 is output to the terminal 6.

Next, one embodiment of the digital filter 70 is shown in FIG.

As a method of converting an analog filter into a digital filter, a method using the standard Z conversion of the following equation is known.

Z = e” (T□ is the sampling period) ...
...(23) The basic circuit 20 in FIG. 1 shown by equation (4)
When the transfer function F1(S) is transformed, it becomes the following equation.

Fl(S)=+(1+e-2sT)...
(24) (Substituting the transfer function F1 (in 81) of the equation 241, the following equation is obtained.

F 1(Z) =+(1+Z-2N)...
・・・・・・・・・・・・・・・・・・・・・(25) However, N = T/T.

In the embodiment of FIG. 9, the transfer function F s of the above equation (25)
This is a digital filter that realizes (Z).

In the figure, 71 is an input terminal for the digital signal Ei output from the eighth factor A/D converter 60, 72 is an output terminal for the digital signal Eo input to the D/A converter 80 in FIG. 73 is a delay circuit, 74α and 74b are coefficient circuits, and 75 is an addition circuit.

Signal Ei input from terminal 71 is input to delay circuit 73 and coefficient circuit 74α. The signal Ei input to the delay circuit 73 is delayed by 2N bits (2T in time). The output signal from the delay circuit 73 is amplified by 1/2 in the coefficient circuit 74b, and the output signal is input to the addition circuit 75. On the other hand, the signal E1 input to the coefficient circuit 74α is reduced to 1/2 by the coefficient circuit 74α.
The signal is amplified twice, and the output signal is input to the adder circuit 75. The adder circuit 75 adds the output signal of the coefficient circuit 74α and the output signal of the coefficient circuit 74h.
The five output signals Eo are output to terminal 72. still,(
25) N (=T/To) shown in formula is the delay circuit 73α
, 73b, and is the number of delay bits at 73b, and the stybling period T is set to be an integer greater than or equal to 1.

Set.

By configuring the digital filter 70 in FIG. 8 as described above, the transfer function from the input terminal 5 to the output terminal 6 of the digital processing type basic circuit 20D in FIG. 8 is expressed by equation (4). It goes without saying that this matches the transfer function Fl(S) of the basic circuit 20 shown in FIG.

Therefore, by replacing the basic circuit 20 in the signal processing apparatus 100 of FIG. 1 with the digital processing type basic circuit 20D, a digital processing type signal processing apparatus corresponding to the signal processing apparatus 100 of FIG. 1 can be constructed.

Furthermore, in the signal processing device 200 of FIG. 6, the basic circuits 20α, 20b, 20C are the same as the basic circuit 20 described above, so the basic circuits 20α, 20h, 20C
In the above embodiments, a digital processing type signal processing device corresponding to the signal processing device 200 of FIG. 6th
In the signal processing device 200 shown in the figure, a digital processing type signal processing device is shown in which the basic circuit 20 and the basic circuits 20α, 20b, and 20C are each replaced with the digital processing type basic circuit 20D.
00 and 200 may all be constructed from digital circuits.

A digital processing type signal processing device 100D in which the signal processing device 100 shown in FIG. 1 is constructed entirely of digital circuits.
An example of this is shown in FIG. A part of this figure is common to FIG. 8, and the common parts are given the same reference numerals and detailed explanation thereof will be omitted. In Fig. 10, 1 is a signal input terminal, 2
is a signal output terminal, and 90 is a transfer function Ho(Z
) is a digital filter that realizes

The signal Vi input from the terminal 1 is successively converted into a digital signal at the sampling period To in the A/D converter 60, and the output signal Vi is input to the digital filter 90. The signal vO, which has been subjected to a predetermined filtering process by the digital filter 90, is input to the D/A converter 80 and converted into an analog signal.

The output signal vO of this D/A converter 80 is output from terminal 2.
is output to.

Next, one embodiment of the digital filter 90 will be described as an eleventh embodiment.
As shown in the figure.

The signal processing device in Figure 1 Zoo's transfer function Ho(S)(
The above equation (5) is transformed into the following equation.

H□(S) = ' + e-8T+ ', e-2S
T=-0, (24) Substituting the above equation into equation (26) and applying the above standard Z transformation yields the following equation.

The embodiment shown in FIG. 11 is a digital filter that realizes the transfer function Ho of the above equation (b).

In FIG. 11, 91 is the A/D converter 60 in FIG.
Digital signal output from ゜■1 input terminal, 92
is the output of the digital signal Vo input to the D/A converter 80 in FIG. 10, 93 is a delay circuit, 94 is a digital filter that realizes the transfer function F2 (Z+) of the above equation (b), and 95 is an adder circuit. The transfer function F2■ of the above equation (E) is basically the transfer function Fl■) (the above 2N) equation) of the digital filter 70 constituting the digital processing basic circuit 20D in FIG. Because it was done,
Specifically, in the digital filter 70 of FIG. 9, this can be realized by simply changing the coefficient circuits 74α and 74b to coefficient circuits whose coefficient values are multiplied by V2.

Signal v1 input from terminal 91 is input to delay circuit 93 and digital filter 94. Delay circuit 93
The signal Vi input to the delay circuit 93 is delayed by N pits (T in terms of time), and its output signal is input to the adder circuit 95. On the other hand, the signal Vi input to the digital filter 94 is subjected to a predetermined filtering process, and its output signal is input to the adder circuit 95. Addition circuit 95
Then, the output signal of the delay circuit 93 and the output signal of the digital filter 94 are added, and the output signal (2) of the adder circuit 95 is outputted to the terminal 92.

By configuring the digital filter 90 in FIG. 10 as described above, the input terminal 1 to the output terminal 2 of the digital processing type signal processing device 100D in FIG.
The transfer functions up to this point coincide with the transfer function Ho(S) of the signal processing device 100 in FIG. 1 shown by equation (5), and the signal processing device 100 can be constructed entirely from digital circuits.

Next K, digital processing type signal processing device 2 when the signal processing device 200 in FIG. 6 is constructed entirely of digital circuits
An example of 00D is shown in FIG. Part of the figure is 1st
This is common to FIG. 0, and common parts are given the same reference numerals and detailed explanation thereof will be omitted. In FIG. 12, 3 is a signal input terminal, 4 is a signal output terminal -110 is a digital filter that realizes a transfer function H1 (Zl), which will be described later.

The operation of the digital processing type signal processing device 200D shown in FIG. Since it is the same as the processing device 100D, detailed explanation thereof will be omitted.

Next, a first embodiment of the digital filter 110 will be described.
Shown in Figure 3.

Transfer function Hs (81(
Up.

When the equation (16) is transformed, it becomes the following equation.

−38T K Hl(S)=e −(−(1+e−”))・e−”
By substituting the above equation into this equation (a) and performing the standard 2 conversion described above, the following equation is obtained.

Hl (Zl = Z-3N-F2(:Zl ・Z-2
N+ (F2(Z)) 2・Z'-(F2(Z))3
・・・・・・・・・・・・・・・(2
)) However, F2 (Z) is a transfer function expressed by the above equation (b). The embodiment shown in FIG. 13 is a digital filter that realizes the transfer function H1(Z) of the above equation).

In FIG. 13, 111 is the A/D converter 6 of FIG.
An input terminal for the digital signal Vi output from 0, 11
2 is an output terminal for the digital signal Vo input to the D/A converter 80 in FIG. 12, 94α, 94h, 94C
is the same digital filter as the digital filter 94 in FIG. 11 that realizes the transfer function F2(Z) of the above equation (-), F3, 93, and 115 are delay circuits, and 116 is an adder circuit.

The signal Vi input from the terminal 111 is sent to the delay circuit 115.
and is input to a digital filter 94α. The signal v1 input to the delay circuit 115 is
The output signal v is delayed by N bits (3T in time).
1 is input to the adder circuit 116. On the other hand, the signal v1 input to the digital filter 944 is subjected to a predetermined filtering process, and the output signal Va is sent to the delay circuit 73.
and is input to a digital filter 94h. The signal Va input to the delay circuit 73 is delayed by 2N bits (2T in time), and its output signal v2 is input to the adder circuit 116. Further, the signal Va input to the digital filter 944 is subjected to a predetermined filtering process, and the output signal vb is input to the delay circuit 93 and the digital filter 94C. Delay circuit 9
The signal vb inputted to the circuit 3 is delayed by N bits in the delay circuit 93, and the output signal v3 is inputted to the addition circuit 116. The signal vb input to the digital filter 94C is subjected to a predetermined filtering process, and the output signal V
"4 is input to the addition circuit 116. In the addition circuit 116, the above signal v1e F2 input to the addition circuit 116
#For F3 e F4, Vo: V'I F2 + F3- F4
----- (This addition circuit 11 performs aol operation and
6 is output to the Vo It terminal 112.

Since the digital filter 110 in FIG. 12 is configured as described above, the transfer function from the input terminal 3 to the output terminal 4 of the digital processing type signal processing bag fi200D in FIG. 12 is expressed by equation 06). This corresponds to the transfer function H1(S) of the signal processing device 200 in FIG. 6, and the signal processing device 200 can be constructed entirely from digital circuits.

〔Effect of the invention〕

As described above, according to the present invention, a signal to be transmitted (or recorded and reproduced) is converted into a signal having a phase characteristic near IJ and a desired amplitude characteristic, and in particular, the middle or high frequencies of the signal are amplitude-emphasized. A pre-emphasis circuit whose phase characteristic is linear, and a de-emphasis circuit which has a characteristic opposite to its amplitude characteristic and whose phase characteristic is near IJ and can be sufficiently matched with the above pre-emphasis circuit over a wide frequency range. can be realized with a relatively simple configuration.

Additionally, these can be easily constructed using digital circuits, increasing the precision and stability of signal processing.
It also facilitates circuit integration.

Furthermore, if this is applied to an FM transmission system, it is possible to increase the amount of frequency deviation without widening the transmission band, and eliminates the need for waveform clipping to prevent overmodulation, reducing waveform distortion (S/ N can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a signal processing device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a basic circuit according to the present invention, and FIG. 3 is a block diagram showing an embodiment of a basic circuit according to the present invention. A wiring diagram showing specific examples of an impedance circuit and an admittance circuit, FIG. 4 is a characteristic diagram showing the amplitude characteristics of the signal processing device in FIG. 1, and FIG. 5 is a waveform diagram showing the response waveform of the signal processing device in FIG. 1. , FIG. 6 is a block diagram showing another embodiment of the signal processing device of the present invention, FIG. 7 is a characteristic diagram showing the amplitude characteristics of the signal processing device of FIG. 6, and FIG. 8 is a basic circuit according to the present invention. 9 is a block diagram showing an embodiment of the digital filter constituting the basic circuit of FIG. 8. FIG. 10 is a block diagram showing another embodiment of the signal processing device of the present invention. FIG. 11 is a block diagram showing an embodiment of the digital filter constituting the signal processing device shown in FIG. 10. FIG. 12 is a block diagram showing another embodiment of the signal processing device of the present invention, and FIG. 13 is a block diagram showing an embodiment of the digital filter constituting the signal processing device of FIG. 12. 20, 20D... Basic circuit, 21... Impedance circuit, 22... Admittance circuit, 10, 11, 12, 73, 93, 115...
・Delay circuit, 30, 30α, 30b, 74α,
74b...Coefficient circuit, 40, 50, 75, 95
, 116...addition circuit, 100, 100D,
200, 200D...Signal processing device. Representative Patent Attorney Katsuo Ogawa - Figure I Figure 2 (b) (b) Figure 5 (α) Figure 6 J Figure 7 Figure 8 Q Section I f. L-11111 Flood-J Kami tO Diagram No. 11 Ward L --m-#io ("Nooooooooooooooooooooo") I2 I3 I3 Diagram H

Claims (1)

[Claims] 1. In a device that converts an input signal into a signal having predetermined frequency characteristics, where ω is the angular frequency of the input signal and T is a constant having a unit of time, cosh(jωT)・e＾− A signal processing device comprising means for synthesizing an input signal via a basic circuit having a transfer function approximated by a function ^j^ω^T and a signal obtained by delaying the input signal by a predetermined time at a predetermined ratio. 2. The above basic circuit uses R_0 as a reference resistance, and R_0
A patent claim characterized in that it is constructed by connecting in series an impedance circuit Z approximated by a function xtanh(jωT) or an admittance circuit Y approximated by a function tanh(jωT)/R_0 and a resistor R. The signal processing device according to item 1. 3. The basic circuit above performs Z transformation (Z=e^
j^ω^T^_^0), and T_0 is the sampling period,
Claim 1, characterized in that it is constituted by a digital filter having a transfer function approximated by the following function, where N=T/T_0: (1/2)(1+Z^-^2^N)
The signal processing device described in Section 1. 4. In the signal processing device according to claim 1, the transfer function H(S) is defined as H(S) (S=jω, ω is the angular frequency of the input signal), and the transfer function H(S) is transformed by Z-transform ( Z
=e^j^ω^T^_^0, T_0 is the sampling period) A signal processing device configured with a digital filter whose transfer function is a function H (Z). 5. In a device that converts an input signal into a signal with predetermined frequency characteristics, where ω is the angular frequency of the input signal, T is a constant having the unit of time, and K is a constant, {1+K・cosh(jωT)}・e A first signal processing device having a transfer function approximated by the function ^-^j^ω^T, and m being an integer greater than or equal to 0, e^-^j^ω^T/1+K・cosh(jωT) 1. A signal processing device configured to be cascade-connected to a second signal processing device having a transfer function approximated by a function. 6. Assuming that both τ_1 and τ_2 are constants having units of time (τ_1≠τ_2), the first circuit has a transfer function approximated by the function (1+jωτ_1)/(1+jωτ_2).
The second circuit is connected in cascade to the signal processing device of
6. The signal processing device according to claim 5, wherein the signal processing device is cascade-connected to the signal processing device.