JPS6370458A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6370458A JPS6370458A JP21267186A JP21267186A JPS6370458A JP S6370458 A JPS6370458 A JP S6370458A JP 21267186 A JP21267186 A JP 21267186A JP 21267186 A JP21267186 A JP 21267186A JP S6370458 A JPS6370458 A JP S6370458A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- source
- drain
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 16
- 230000000694 effects Effects 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000002513 implantation Methods 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- -1 BF2 ions Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、絶縁ゲート型（ＭＯＳ型）半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing an insulated gate type (MOS type) semiconductor device.
（従来の技術）
ｎチャネル型の）ＩＯ３ＦＥＴでは、通常ｎ十−ポリＳ
ｉゲートを用いる関係上、閾値制御のためにチャネル表
面にＢをイオン注入してｎ基板表面にｐ型層を形成する
埋込み型チャネル溝造をとる。また、ソース、ドレイン
として拡散係数の大きいＢを注入不純物として用いるた
めに、ソース、ドレイン領域の接合深さは工ｊは、ｎチ
ャネル型の場合に比較して大きくなる。したがって、ｐ
チャネル型）１０３ＦＥＴのチャネル長を短くしていっ
たとき、以上述べた工ｊが大きいということと、表面ｐ
型層の領域がら空乏層が伸びやすいということのために
、しきい値が低下する短チヤネル効果が顕著に現われる
。(Prior art) In an n-channel type IO3FET, the n+-poly S
Since an i-gate is used, a buried channel groove structure is used in which B ions are implanted into the channel surface to form a p-type layer on the n-substrate surface for threshold control. Furthermore, since B, which has a large diffusion coefficient, is used as an implanted impurity for the source and drain, the junction depth of the source and drain regions is larger than that of the n-channel type. Therefore, p
(channel type) 103 When the channel length of FET is shortened, the above-mentioned process j is large and the surface p
Since the depletion layer tends to extend in the type layer region, a short channel effect that lowers the threshold value appears prominently.
（発明が解決しようとする問題点）
本発明は上記したｐチャネル型ＭＯ３ＦＥＴに現われる
短チヤネル効果を抑制した半導体装置の製造方法を提供
することを目的とする。(Problems to be Solved by the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device that suppresses the short channel effect that appears in the above-mentioned p-channel type MO3FET.
（発明の構成）
（問題点を解決するための手段）
本発明は半導体表面不純物注入層とゲート絶縁膜、ゲー
ト電極を形成した後、ゲート電極をマスクとした不純物
注入を行い、その後、ソース、ドレイン形成予定領域上
におけるゲート電極の側方部分に選択的に半導体膜を形
成させ、この後、従来と同様にゲート電極をマスクとし
て不純物をドープしてソース、ドレイン領域を形成する
ことを特徴とする。(Structure of the Invention) (Means for Solving Problems) In the present invention, after forming a semiconductor surface impurity implantation layer, a gate insulating film, and a gate electrode, impurity implantation is performed using the gate electrode as a mask. The method is characterized in that a semiconductor film is selectively formed on the side portions of the gate electrode on the region where the drain is to be formed, and then impurities are doped using the gate electrode as a mask as in the conventional method to form the source and drain regions. do.
（作 用）
本発明によれば、ソース、ドレイン形成予定誼域上のう
ちゲート電極の側方位置に半導体膜を選択的に形成させ
てソース、ドレインＰａ １６を形成するため、例えば
ソース、ドレイン領域の接合面を、ゲート電極に隣接す
る部分では、チャネル表面不純物注入層と基板との接合
深さとほぼ同じ深さに制御できる。また、同時にソース
、ドレイン領域が横方向拡散により、チャネル表面不純
物注入層にまでまわり込むのをほぼ完全に防ぐことがで
きる。従って、本発明によればチャネル長の減少にとも
なう短チヤネル効果を緩和することができる。(Function) According to the present invention, the semiconductor film is selectively formed on the side of the gate electrode on the planned source/drain formation region to form the source/drain Pa 16. The junction surface of the region can be controlled to approximately the same depth as the junction depth between the channel surface impurity implantation layer and the substrate in the portion adjacent to the gate electrode. Furthermore, at the same time, it is possible to almost completely prevent the source and drain regions from reaching the channel surface impurity implantation layer due to lateral diffusion. Therefore, according to the present invention, the short channel effect caused by a decrease in channel length can be alleviated.
本発明の実施例を図面を用いて説明する。第１図〜第７
図は本発明の一実施例のＭＯＳトランジスタの製造工程
断面図である。Embodiments of the present invention will be described using the drawings. Figures 1 to 7
The figure is a cross-sectional view of the manufacturing process of a MOS transistor according to an embodiment of the present invention.
まず、ｎ型３ｉ基板１に選択酸化法等によりフィールド
絶縁膜２を形成し、素子領域に閾値調整のためのＢ等の
イオン注入を行い表面領域にｎ型層３を形成し埋込みチ
ャネル型にする。そして、通常の工程に従いゲート酸化
膜４を介して多結晶シリコン膜によるゲート電極５を形
成する。ソース、ドレイン形成予定領域には、ゲート電
極５をマスクとしてＰまたはＡＳ等のイオン注入により
ｎ型層３より深い位置に高濃度のｎ型層６，７を形成す
る（第１図）。First, a field insulating film 2 is formed on an n-type 3i substrate 1 by selective oxidation, etc., ions such as B are implanted into the element region for threshold adjustment, and an n-type layer 3 is formed in the surface region to form a buried channel type. do. Then, a gate electrode 5 made of a polycrystalline silicon film is formed via the gate oxide film 4 according to a normal process. In the region where the source and drain are to be formed, highly doped n-type layers 6 and 7 are formed at a deeper position than the n-type layer 3 by ion implantation of P or AS using the gate electrode 5 as a mask (FIG. 1).
次いで、全面に３！０２膜８をＣＶＤ法により堆積し、
反応性イオンエツチング（ＲＩＥ）によりこれをエツチ
ングしてゲート電極５の側壁にのみ３１０２膜８を残す
。さらに全面にＳｉａＮ＋膜９をＣＶＤ法により堆積し
これをＲＩＥによりエツチングしてＳｉＯｚ膜８の外側
にのみＳｉ３Ｎ＋膜９を残す（第２図）。Next, a 3!02 film 8 is deposited on the entire surface by CVD method,
This is etched by reactive ion etching (RIE) to leave the 3102 film 8 only on the side walls of the gate electrode 5. Further, a SiaN+ film 9 is deposited over the entire surface by CVD and etched by RIE, leaving the Si3N+ film 9 only on the outside of the SiOz film 8 (FIG. 2).
この後ゲート電極５及びソース、ドレイン形成予定領域
の表面に熱酸化によりＳｉ０２膜１０膜形０する（第３
図）。そして、Ｓ ｉ ３ Ｎ４膜９をリン酸またはＣ
Ｆ３と０２とＮ２を含むガスを用いたＣＤＥ法により選
択的に除去し、ソース、ドレイン形成予定領域のゲート
電極５に隣接する位置に開口を設ける（第４図）。After that, 10 SiO2 films are formed on the surfaces of the regions where the gate electrode 5 and source and drain are to be formed by thermal oxidation (third
figure). Then, the Si 3 N 4 film 9 is coated with phosphoric acid or C
It is selectively removed by a CDE method using a gas containing F3, 02, and N2, and an opening is provided at a position adjacent to the gate electrode 5 in the region where the source and drain are to be formed (FIG. 4).
次に、開口部に露出した基板上にで択エピタキシャル法
によりＳｉ膜１１を選択成長させる（第５図）。そして
弗化アンモニウム液を用いてゲート電極５上及びソース
、ドレイン形成予定領域上の５ｔＯｚ膜１０を除去し、
Ｂ又は８Ｆ２のイオン注入と９００℃、６０分程度の熱
処理によりソース、ドレイン領域にｐ十型層１２．１３
を形成する（第６図）以下、通常の工程により全面に５
ｔＣｈ摸１４をＣＶＤ法により堆積し、これにコンタク
トホールを開口して１２膜によるソース、ドレイン電極
１５゜１６を形成する（第７図）。Next, a Si film 11 is selectively grown on the substrate exposed in the opening by a selective epitaxial method (FIG. 5). Then, using an ammonium fluoride solution, the 5tOz film 10 on the gate electrode 5 and on the regions where the source and drain are to be formed is removed.
A p-type layer 12.13 is formed in the source and drain regions by ion implantation of B or 8F2 and heat treatment at 900°C for about 60 minutes.
(Figure 6) After that, 5 layers are formed on the entire surface using the normal process.
A tCh pattern 14 is deposited by the CVD method, and contact holes are opened in it to form source and drain electrodes 15 and 16 made of 12 films (FIG. 7).
この実施例によれば、ゲート電極に隣接する位置に３ｉ
膜を選択成長させてイオン注入を行ってソース、ドレイ
ン領域を形成しているから、第６図おるいは第７図に示
すようにゲート電極に隣接する位置で実効的に極めて浅
いソース、ドレイン接合を形成することができる。ざら
にソース、ドレイン形成時におけるＢの横方向拡散μが
非常に効果的に抑制できる。従って、Ｂという拡散係数
の大きい注入不純物を用いてソース、ドレインを形成す
るｐチャネルＸ１０Ｓトランジスタにおいて従来さけら
れなかった短チヤネル効果が重めで有効に抑制でき、サ
ブミクロンのチャネル長の微細なｐチャネル？（Ｏ３Ｆ
ＥＴにおいても、短チヤネル効果の現れないものが実現
できる。According to this embodiment, 3i is located at a position adjacent to the gate electrode.
Since the source and drain regions are formed by selectively growing the film and performing ion implantation, the source and drain regions are effectively extremely shallow at the position adjacent to the gate electrode, as shown in Figures 6 and 7. A bond can be formed. In other words, the lateral diffusion μ of B during formation of the source and drain can be very effectively suppressed. Therefore, the short channel effect, which was conventionally unavoidable in p-channel ? (O3F
Even in ET, it is possible to realize a system in which short channel effects do not appear.
さらに、従来性われてきた側壁のみを用いる方法に比べ
て本方法では側壁の巾を小さくでき側壁５ｉＯｚ膜中へ
のキャリアトラップによる素子特性の劣化すなわち電流
駆動力の低下が防げる。Furthermore, compared to the conventional method of using only the sidewalls, this method allows the width of the sidewalls to be made smaller and prevents deterioration of device characteristics, ie, decrease in current driving power, due to carrier trapping in the sidewall 5iOz film.
次に、本発明の他の実施例として、上述した実施例の工
程中の第４図の状態において他の部分をマスクとして開
口部のみにＰまたはＡＳのイオン注入を行い高濃度のｎ
型領域２１．２２を形成する（第８図）。この後、上記
実施例と同じ工程（第５．６．７図）を経て、Ｒ柊的に
第９図に示す埋込み型ｐチャネルＭＯ３ＦＥＴが形成さ
れる。Next, as another embodiment of the present invention, in the state shown in FIG. 4 during the process of the above-mentioned embodiment, P or AS ions are implanted only into the opening using other parts as a mask, resulting in a high concentration of n.
Forming mold regions 21,22 (FIG. 8). Thereafter, the buried p-channel MO3FET shown in FIG. 9 is formed using the same steps as in the above embodiment (FIGS. 5.6.7).
この実施例では、短チヤネル効果を抑制するｎ型不純物
領域が２段階にわたって形成され、特に２回目の不純物
注入では第８図の開口部のみからの局所的な高精度な注
入不純物領域のυＪｉ３！ｌが可能である。従って、ソ
ース、ドレイン領域の実効的な接合深さ工ｊが浅くなっ
た効果と合せて、ｎ型不純物領域を浅く、しかも最通な
形状に形成することが可能であり、短チヤネル効果の抑
制に力めて有効である。In this embodiment, the n-type impurity region for suppressing the short channel effect is formed in two stages. In particular, in the second impurity implantation, the impurity region is locally and highly precisely implanted only from the opening shown in FIG. 8 (υJi3!). l is possible. Therefore, in addition to the effect of reducing the effective junction depth of the source and drain regions, it is possible to form the n-type impurity region in a shallow and continuous shape, which suppresses the short channel effect. It is extremely effective.
また、選択エピタキシャル法によるＳｉｖ、の厚みとイ
オン注入によるｎ型不純物領域の深さ、形状の両者をと
もに制御することにより、ソース、ドレイン領域の接合
面形状を任意に制御することができ、チャネル領域での
電界形状を好ましいものにすることができる。この結果
、ＬＤＤＩ造と同様にドレイン領域近傍での高電界を緩
和して微細）１０３ＦＥＴでのホットエレクトロン効果
を抑制することができる。In addition, by controlling both the thickness of Siv by selective epitaxial method and the depth and shape of the n-type impurity region by ion implantation, the shape of the junction surface of the source and drain regions can be arbitrarily controlled. The electric field shape in the region can be made preferable. As a result, similar to the LDDI structure, the high electric field near the drain region can be relaxed and the hot electron effect in the fine 103 FET can be suppressed.
（発明の効果〕
本発明によれば、短チヤネル効果の防止に有効なｐチャ
ネルＭＯＳトランジスタが１ｑられる。(Effects of the Invention) According to the present invention, 1q p-channel MOS transistors are provided which are effective in preventing short channel effects.
第１図乃至第７図は本発明の−実り色例を示す工程断面
図、第８図及び第９図は本発明の他の実施例を説明する
ための工程新面図である。
１・・・ｎ−型Ｓｉ基板 ２・・・フィールド絶縁膜
３・・・Ｄ ｒ Ｓ ！層 ４・・・ゲート電極
５・・・ゲート電極 ６，７・・・ｎ型層８ ・
” Ｓ ｉ Ｑ ２膜 ９＝Ｓ ｆ ｓ Ｎ ４膜
１０・・・Ｓ Ｉ Ｏ２膜 １１・・・ｓ１膜（選
択成長膜）１２、１３−、、ｐ＋型層１４−＝Ｓ ｉ
Ｏｚ 摸１５、１６・・・ソース、ドレインｉす※２１
、２２・・・ｎ十型領域
代理人 弁理士 則 近 憲 佑 。
同 竹 花 喜久男FIGS. 1 to 7 are process cross-sectional views showing a full-color example of the present invention, and FIGS. 8 and 9 are new process views for explaining other embodiments of the present invention. 1... N-type Si substrate 2... Field insulating film 3... Dr S! Layer 4... Gate electrode 5... Gate electrode 6, 7... N-type layer 8.
"S i Q 2 film 9 = S f s N 4 film 10... S I O2 film 11... s1 film (selective growth film) 12, 13-, p+ type layer 14- = Si
Oz 15, 16...source, drain isu*21
, 22...n type 10 area agent, patent attorney Noriyuki Chika. Kikuo Takehana
Claims (2)
工程と、前記基板の半導体表面上にゲート絶縁膜を介し
てゲート電極を形成する工程と、前記ゲート電極をマス
クとして基板と同導電型の不純物を注入する工程と、前
記ゲート電極の側方で絶縁膜を介してソース、ドレイン
形成予定領域上に部分的に半導体膜を形成させる工程と
、前記半導体領域と前記基板表面にわたって不純物を注
入してソース、ドレイン領域を形成する工程とを備えた
ことを特徴とする半導体装置の製造方法。(1) A step of implanting an impurity into the channel region of the semiconductor of the substrate, a step of forming a gate electrode on the semiconductor surface of the substrate via a gate insulating film, and a step of injecting an impurity into the channel region of the semiconductor of the substrate, using the gate electrode as a mask, and forming a gate electrode of the same conductivity type as the substrate. a step of implanting an impurity; a step of partially forming a semiconductor film on the region where the source and drain are to be formed via an insulating film on the side of the gate electrode; and a step of implanting the impurity over the semiconductor region and the surface of the substrate. A method of manufacturing a semiconductor device, comprising the step of forming source and drain regions.
予定領域のゲート電極側壁部に選択的にＳｉＯ＿２膜を
形成し、このＳｉＯ＿２膜が形成されたゲート電極側壁
部に選択的にＳｉ＿３Ｎ＿４膜を形成して、前記ソース
、ドレイン形成予定領域の残りの部分にＳｉＯ＿２膜を
形成した後、前記Ｓｉ＿３Ｎ＿４膜を選択的にエッチン
グ除去することにより、形成されたＳｉ＿３Ｎ＿４膜が
除去された開口部から、前記基板と同導電型の不純物を
注入し、その後、開口部に選択的に前記半導体膜をエピ
タキシャル成長させることを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。(2) After forming the gate electrode, a SiO_2 film is selectively formed on the sidewalls of the gate electrode in the regions where the source and drain are to be formed, and a Si_3N_4 film is selectively formed on the sidewalls of the gate electrode where the SiO_2 film is formed. After forming a SiO_2 film in the remaining portions of the regions where the source and drain are to be formed, the Si_3N_4 film is selectively etched away, and the substrate is then etched from the opening where the formed Si_3N_4 film is removed. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising implanting an impurity of the same conductivity type as the semiconductor film, and then epitaxially growing the semiconductor film selectively in the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21267186A JPS6370458A (en) | 1986-09-11 | 1986-09-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21267186A JPS6370458A (en) | 1986-09-11 | 1986-09-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6370458A true JPS6370458A (en) | 1988-03-30 |
Family
ID=16626471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21267186A Pending JPS6370458A (en) | 1986-09-11 | 1986-09-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6370458A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5132757A (en) * | 1990-11-16 | 1992-07-21 | Unisys Corporation | LDD field effect transistor having a large reproducible saturation current |
| US5221632A (en) * | 1990-10-31 | 1993-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of proudcing a MIS transistor |
-
1986
- 1986-09-11 JP JP21267186A patent/JPS6370458A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5221632A (en) * | 1990-10-31 | 1993-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of proudcing a MIS transistor |
| US5808347A (en) * | 1990-10-31 | 1998-09-15 | Matsushita Electric Industrial Co., Ltd. | MIS transistor with gate sidewall insulating layer |
| US5132757A (en) * | 1990-11-16 | 1992-07-21 | Unisys Corporation | LDD field effect transistor having a large reproducible saturation current |
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