JP3060948B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS semiconductor device for suppressing a short-channel effect such as reduction in threshold voltage and occurrence of punch-through.

[0002]

2. Description of the Related Art As elements become finer, it is necessary to suppress short channel effects such as lowering of threshold voltage and occurrence of punch-through. As a structure of a MOS semiconductor device for suppressing the short channel effect, a structure in which an oxide film region 53 is selectively formed between a source / drain region 51 and a channel region 52 as shown in FIG. Kaikai 64-73770). In FIG. 5, reference numeral 54 denotes a p-type Si substrate, 55 denotes a gate oxide film, and 56 denotes a gate electrode made of polycrystalline silicon. The feature of this structure is that by selectively forming an oxide film region 53 at the source / drain end of the channel region 52, the extension of the depletion layer from the source / drain region 51 to the channel region 52 is suppressed, and the threshold voltage is reduced. And short-channel effects such as generation of punch-through and the like.

As described above, a conventional method of forming an oxide film region selectively at the source / drain ends of the channel region, taking an n-type MOSFET as an example (JP-A-64-73).
770) are shown in FIGS. 6A to 6D. FIG.
As shown in (a), after forming an SiO ₂ film 62 to be an element isolation region and a gate insulating film region on a p-type Si substrate 61, a gate electrode 64 made of polycrystalline silicon is formed using a resist film 63 as a mask. I do. Then, FIG.
As shown in (b), the resist film 6 on the gate electrode 64
Using mask 3 as a mask, oxide film 62 and p-type Si substrate 61 on the source / drain formation planned region are etched by RIE to form openings 65 in the p-type Si substrate. Then, after removing the resist film 63 on the gate electrode 64,
As shown in FIG. 6C, SiO _{2 is formed on} the side wall of the opening 65.
Is formed. Note that the height of the sidewall 66 is set slightly lower than the etching depth of the p-type Si substrate 61 in the opening 65. Next, FIG.
As shown in FIG.
i is grown and the opening is buried and flattened. Then A
An n ⁺ -type impurity such as s ⁺ is ion-implanted to form an n ⁺ -type source / drain region 67.

[0004]

Problems to be Solved by the Invention FIGS. 6A to 6
In the conventional example shown in (d), there is a problem that it is difficult to form the side wall 66 only on the side wall on the gate electrode side. Even if an SiO ₂ film is grown on the entire surface including the gate electrode by CVD and etched back by RIE, the height of the side wall 66 is slightly lower than the etching depth of the p-type Si substrate 61. Is difficult to control. This means that the thickness of the source / drain region 67 in the upper portion of the sidewall 66 varies, which causes a problem that the characteristics of the MOS semiconductor device vary. Further, in this conventional example, the opening 65 of the p-type Si substrate in the region where the source / drain is to be formed shown in FIG.
As shown in (d), a step of backfilling by the Si selective epitaxial method is included. However, since the polysilicon which is the gate electrode 64 is exposed in this step,
When the selective epitaxial growth is performed, Si grows not only on the opening 65 of the p-type Si substrate but also on the gate electrode 64 and the side surface of the gate electrode 64, so that the gate electrode 64
And the source / drain region 67 is short-circuited. The present invention provides a method for manufacturing a semiconductor device that solves the above problems.

[0005]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on a semiconductor substrate and a step of forming a gate electrode. Forming a first sidewall on the side of the gate electrode, forming a second sidewall on the side of the first sidewall, and tilting the semiconductor substrate obliquely using the gate electrode and the second sidewall as a mask. Etching, oxidizing the semiconductor substrate to form a first oxide film, removing the second sidewall, and using the first sidewall and the gate electrode as a mask, the semiconductor substrate and the first Etching the oxide film, selectively growing the semiconductor film in the opening of the semiconductor substrate, and masking the first sidewall and the gate electrode. Those having a step of performing the source drain ion implantation and.

As described above, according to the present invention, since the sidewall is formed on the side surface of the gate electrode, the growth of the semiconductor film on the side surface of the gate electrode is suppressed at the time of selective growth of the semiconductor film. The short circuit of the source / drain region can be prevented.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show an example in which the present invention is applied to an nMOSFET. First, as shown in FIG. 1A, a gate oxide film 2 of about 6 nm is formed on the surface of a p (100) Si substrate 1 by, for example, a thermal oxidation method. Thereafter, polycrystalline silicon 3 of about 150 nm is deposited by a CVD method or the like. Next, a SiO ₂ film 4 of about 10 nm is formed by a CVD method or the like. Then, a silicon nitride film 5 of about 10 nm is formed by a CVD method or the like. Thereafter, a SiO ₂ film 6 of about 10 nm is deposited by a CVD method or the like. Subsequently, a gate electrode 7 having a laminated structure of polycrystalline silicon, SiO ₂ , a silicon nitride film, and SiO ₂ is formed by a photolithography process and an etching process. Thereafter, a first sidewall 8 of about 50 nm made of SiO ₂ is formed on the side face of the gate electrode, and a _second sidewall 9 of about 50 nm made of a silicon nitride film is formed on the side face of the first sidewall.

Next, as shown in FIG. 1B, RIE (Reactive Io) is performed using the gate electrode 7 and the second side wall 9 made of a silicon nitride film as a mask.
The p (100) Si substrate in the region where the source / drain is to be formed is etched to a thickness of about 150 nm by, for example, nEtching) to form an opening 10 in the p (100) Si substrate. At the time of this etching, the etching is performed obliquely at an angle of about 30 ° with respect to the normal line 11 of the p (100) Si substrate in a direction in which the opening is widened on the back side of the substrate.

Next, as shown in FIG. 1 (c), 40 p is formed in the opening 10 of the p (100) Si substrate by a thermal oxidation method or the like.
An oxide film 12 of about nm is formed. In general, in the thermal oxidation method, an oxide film is formed at about 45% in a Si substrate.
The oxide film 12 having a thickness of about 40 nm is formed on a Si substrate to a thickness of about 18 nm. Therefore, as shown in FIG.
On the surface of the (100) Si substrate, the p (100) Si substrate 1 is located immediately below the second sidewall 9 made of a silicon nitride film.
A portion remains, but in a slightly deep portion, only the oxide film 12 exists immediately below the second sidewall 9 made of the silicon nitride film. In a slightly deeper portion, the oxide film 12 exists immediately below the first sidewall 8 made of SiO ₂ .

After that, as shown in FIG. 1D, after the second side wall 9 made of a silicon nitride film is wet-etched with phosphoric acid or the like, the gate electrode 7 and the first side wall 8 made of SiO _{2 are formed.} Is used as a mask to etch the portion of the p (100) Si substrate 1 covered with the second sidewall 9 made of the silicon nitride film by the RIE method or the like. At this time, the p (100) Si substrate 1 is etched under a condition having a high selectivity to SiO ₂ . Since the surface of the gate electrode 7 is covered with the SiO ₂ film 6, the polysilicon 3 of the gate electrode 7 is not etched.

Subsequently, as shown in FIG.
Electrode 7 and SiO_Two First sidewall 8 made of
Is used as a mask in the opening 10 of the p (100) Si substrate.
The formed oxide film 12 is vertically etched by RIE or the like.
To run. At this time, selection was made for Si and silicon nitride films.
The oxide film 12 is etched under the condition of a high selectivity. Follow
Then, the p (100) Si substrate is opened by this etching.
At the opening 10, the oxide film 12 is etched at the bottom of the opening.
And the p (100) Si substrate 1 is exposed. Also
On the side surface of the opening, p (100) Si group near the surface
The structure is such that the plate 1 is exposed and the oxide film 12 remains under the plate 1.
Further, the gate electrode 7 has a surface portion of SiO 2. _Two Membrane 6
And the silicon nitride film 5 thereunder is exposed.
Becomes

Then, the silicon nitride film layer exposed on the surface of the gate electrode is etched with phosphoric acid or the like to expose the SiO ₂ film 4, and then, as shown in FIG. By selective epitaxial growth of p
(100) The opening of the Si substrate is backfilled with the Si epitaxial growth film 13. Since the surface of the gate electrode 7 is covered with the SiO ₂ film 4 and the side surface is covered with the first sidewall 8 made of SiO ₂ , no Si film grows on the gate electrode. . Therefore, the problem of a short circuit between the gate electrode and the source / drain portion, which has been a problem in the past, does not occur due to Si epitaxial growth.

Thereafter, as shown in FIG.
⁺¹⁴ or the like is implanted at an ion implantation energy of 50 keV and a dose of 3 × 10 ¹⁵ cm ⁻² , for example, and then an activation heat treatment at 1000 ° C. for about 10 seconds is performed in a nitrogen atmosphere to form the source / drain region 15. . Thereafter, an interlayer insulating film, a wiring, and the like are formed by using a conventional technique, and nM
An OS semiconductor device is formed.

FIGS. 3 and 4 show another embodiment in which the present invention is applied to a CMOSFET. First, FIG.
As shown in (a), a field oxide film 22 is formed on a p (100) Si substrate 21 by a known technique, and element isolation is performed. Thereafter, p (100) Si is formed by a well-known technique.
A p-type well region 23 and an n-type well region 24 are formed in a substrate 21 by an ion implantation method. And p (10
0) A gate oxide film 25 of about 6 nm is formed on the surface of the Si substrate 21 by, for example, a thermal oxidation method. Polycrystalline silicon 26 of about 150 nm is deposited thereon by CVD or the like. Next, about 10 nm of SiO _{2 is formed} by CVD or the like.
A film 27 is formed, and then a 10 nm
A silicon nitride film 28 of a degree is formed. Next, an SiO ₂ film 29 of about 10 nm is formed by a CVD method or the like.
In this manner, the gate electrode 30 having a laminated structure of the polycrystalline silicon, the SiO ₂ film, the silicon nitride film, and the SiO ₂ film is formed by the photolithography process and the etching process. After that, SiO 2 is formed on the side of the gate electrode 30.
After forming the first sidewall 31 of about 50nm comprised of _2, forming a second sidewall 32 50nm approximately composed of a silicon nitride film to the first sidewall side.

Next, as shown in FIG. 3B, the RI is formed using the field oxide film 22, the gate electrode 30, and the second sidewall 32 made of the silicon nitride film as a mask.
By the E method or the like, p (10
0) Etch Si substrate 21 by about 150 nm
An opening 33 is formed in a (100) Si substrate. At the time of this etching, p (1
00) Etching is performed obliquely at an angle of about 30 ° with respect to the normal 34 of the Si substrate. Then, as shown in FIG.
An oxide film 35 of about 40 nm is formed in the opening 33 of the p (100) Si substrate by a thermal oxidation method or the like.

Next, as shown in FIG. 3D, after the second sidewall 32 made of a silicon nitride film is wet-etched with phosphoric acid or the like, the gate electrode 30 and the first sidewall 31 made of SiO _{2 are formed.} Using RIE as a mask
The p (100) Si substrate 2 in a portion covered with the second sidewall 32 made of a silicon nitride film by a method or the like.
1 is etched. At this time, the p (100) Si substrate is etched under conditions having a high selectivity to SiO ₂ . Since the surface of the gate electrode 30 is covered with the SiO ₂ film 29, the polysilicon 26 of the gate electrode is not etched.

Thereafter, as shown in FIG. 4E, an oxide film formed in the opening 33 of the p (100) Si substrate using the gate electrode 30 and the first side wall 31 made of SiO ₂ as a mask. 35 is vertically etched by RIE or the like. At this time, the oxide film is etched under conditions having a high selectivity to the Si and silicon nitride films. Therefore, by this etching, in the opening 33 of the p (100) Si substrate, the oxide film 35 is etched at the bottom of the opening, and the p (100) Si substrate 21 is exposed. On the side of the opening, p (100) Si near the surface
The structure is such that the substrate 21 is exposed and the oxide film 35 remains thereunder. Further, the oxide film 35 may remain in the shadowed portion of the field oxide film 22 in some cases. Also, the gate electrode 30
The surface portion of the SiO ₂ film 29 is etched, and the underlying silicon nitride film 28 is exposed.

Thereafter, the silicon nitride film 28 exposed on the surface of the gate electrode 30 is etched with
After exposing the O ₂ film 27, as shown in FIG.
The Si substrate is selectively epitaxially grown by the CVD method or the like, and the opening 33 of the p (100) Si substrate is back-filled with the Si epitaxial growth film. Since the surface of the gate electrode 30 is covered with the SiO ₂ film 27 and the side surface is covered with the first sidewall 31 made of SiO ₂ , the Si film is grown on the gate electrode 30. do not do. Therefore, the problem that the gate electrode and the source / drain portion are short-circuited, which has conventionally been a problem, is not caused by the Si selective epitaxial growth.

Next, as shown in FIG.
On the OSFET side, As ⁺ 37 or the like is ion-implanted with, for example, an ion implantation energy of 50 keV and a dose of 3 × 10 ¹⁵ cm ⁻² , and on the pMOSFET side, BF ₂ ⁺ 38 or the like is ion-implanted with an ion implantation energy of 30 keV and a dose of 3 × 3 × 10 ¹⁵ cm ^−2. 10
Ion implantation at ¹⁵ cm ^-2 and then 100
An activation heat treatment at 0 ° C. for about 10 seconds is performed to form an n-type source / drain region 39 and a p-type source / drain region 40. After that, an interlayer insulating film, wiring, and the like are formed by using a conventional technique, and a CMOS semiconductor device is formed.

[0020]

As described above, in the manufacturing process of a semiconductor device in which an oxide film region is selectively formed between a source drain region and a channel region, the present invention covers the gate electrode with the SiO ₂ film. In addition, while preventing the short circuit between the gate electrode and the source / drain region, which has conventionally been a problem when burying the opening of the Si substrate, the selectively formed oxide film region causes a short channel such as a reduction in threshold voltage and occurrence of punch-through. The effect can be suppressed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating an embodiment of the present invention in the order of manufacturing steps.

FIGS. 2 (e) to 2 (g) are cross-sectional views showing a manufacturing process following FIG.

3 (a) to 3 (d) are cross-sectional views showing another embodiment of the present invention in the order of manufacturing steps.

4 (e) to 4 (g) are cross-sectional views showing a manufacturing process following FIG.

FIG. 5 is a cross-sectional view showing a structure of a conventional semiconductor device.

6 (a) to 6 (d) are cross-sectional views showing a conventional example in the order of manufacturing steps.

[Explanation of symbols]

Reference Signs List 1 p (100) Si substrate 2 gate oxide film 3 polycrystalline silicon 4 SiO ₂ film 5 silicon nitride film 6 SiO ₂ film 7 gate electrode 8 first sidewall made of SiO ₂ 9 second side made of silicon nitride film Wall 10 Opening 11 Normal of p (100) Si substrate 12 Oxide film 13 Si epitaxial growth film 14 As ⁺ 15 Source / drain region 21 p (100) Si substrate 22 Field oxide film 23 p-type well region 24 n-type well region 25 gate Oxide film 26 Polycrystalline silicon 27 SiO ₂ film 28 Silicon nitride film 29 SiO ₂ film 30 Gate electrode 31 First sidewall made of SiO ₂ 32 Second sidewall made of silicon nitride film 33 Opening 34 Si substrate normal 35 oxide film 36 Si epitaxial layer 37 As ⁺ 8 BF ₂ ⁺ 39 n-type source drain region 40 p-type source drain region 51 the source and drain regions 52 channel region 53 oxide region 54 p-type Si substrate 55 a gate oxide film 56 gate electrode 61 p-type Si substrate 62 SiO ₂ film 63 resist Film 64 gate electrode made of polycrystalline silicon 65 opening 66 sidewall made of SiO ₂ 67 n-type source / drain region

Claims (6)

(57) [Claims] A step of forming a gate oxide film on a semiconductor substrate of a first conductivity type; a step of forming a gate electrode on the gate oxide film; and a step of forming a first sidewall on a side surface of the gate electrode. Forming a second sidewall on the side surface of the first sidewall;
Forming an opening by obliquely etching the semiconductor substrate of the first conductivity type using the sidewall and the gate electrode as a mask, and oxidizing the semiconductor substrate of the first conductivity type to form a first oxide film Removing the second side wall; and using the first side wall and the gate electrode as a mask to form the semiconductor substrate.
By etching the oxide film perpendicularly to
Leave the first oxide film only immediately below the first sidewall, and others
Removing the first oxide film , selectively growing a semiconductor film in the opening, and ion- implanting impurities into the semiconductor substrate using the first sidewall and the gate electrode as a mask. the method of manufacturing a semiconductor device characterized by comprising the step of injecting. 2. A gate electrode comprising a polycrystalline silicon and a cover.
2. The method according to claim 1, wherein the semiconductor device has a two-layer structure . 3. The cover film is a SiO ₂ film and silicon nitride.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device has a three-layer structure of a film and a SiO ₂ film . 4. A step of forming a field oxide film on a semiconductor substrate of a first conductivity type to perform element isolation; a step of forming a p-type well region and an n-type well region on the semiconductor substrate; Forming a gate oxide film on a semiconductor substrate of a mold, forming a gate electrode on the gate oxide film, forming a first sidewall on the side surface of the gate electrode, and forming the first sidewall. Forming a second side wall on a side surface, forming an opening by diagonally etching the first conductivity type semiconductor substrate using the second side wall and the gate electrode as a mask, Oxidizing the one conductivity type semiconductor substrate to form a first oxide film, removing the second sidewall, and masking the first sidewall and the gate electrode. Perpendicular to the semiconductor substrate
By directly etching the oxide film, the first substrate is etched.
The first oxide film is left only under the
By comprising the step of removing the oxide film, and performing selective growth of the semiconductor film in the opening, a step of impurity ions implanted into the semiconductor substrate of the first sidewall and the gate electrode as a mask A method for manufacturing a semiconductor device, comprising: 5. A gate electrode comprising a polycrystalline silicon and a cover.
5. The method according to claim 4, wherein the semiconductor device has a two-layer structure . 6. The cover film is a SiO ₂ film, a silicon nitride film.
6. The method according to claim 5, wherein the semiconductor device has a three-layer structure of a film and a SiO ₂ film .