JPS636956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier used in combination with a hold capacitor.

For example, there are sample-and-hold circuits and comparison circuits that combine a voltage-holding capacitor and a circuit including an active element, and in recent years, it has been common practice to integrate the active elements and the like into an integrated circuit. In this case, the hold voltage by the capacitor may vary due to the influence of the input current. Therefore, several measures have been taken to solve this problem. One of them is to use a Darlington connection in the input stage to reduce the input current.

However, in this case, the input voltage range tends to be narrower and the offset voltage of the input differential stage tends to increase compared to the one-stage configuration, so complex process control is required to suppress this.

As a second method, there are means such as configuring the input stage with MOS transistors that essentially do not require input current, or using junction FETs.

However, when MOS transistors are used in the input stage, the offset voltage of the input differential stage is large due to poor matching of characteristics between MOS transistors compared to bipolar transistors, and in order to reduce this, process control and integrated circuit patterning are required. This is quite difficult as it requires consideration of the shape, arrangement, etc. Moreover, in many cases, integrated circuits with MOS transistors built into bipolar element circuits have the disadvantage of complicating the process.

Furthermore, when configuring the input stage with junction FETs, they can be formed at the same time as conventional bipolar elements in terms of process, but as with MOS transistors, it is difficult to control the process to obtain consistent characteristics.

An object of the present invention is to achieve a wide input voltage range by using transistors, diodes, etc. with element characteristics obtained by ordinary bipolar integrated circuits, without the need for complicated processes or process control as described above. It is an object of the present invention to provide an amplifier used in combination with a hold capacitor whose capacitor hold voltage is not affected by current.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention applied to a sample and hold circuit. As is well known, the sample and hold circuit captures and holds an analog input voltage for an arbitrary period of time, and the analog input voltage is applied to the input terminal in the figure.
A sample voltage is applied to the hold capacitor C _H while the analog switch SW is closed, and then when the analog switch SW is opened, the sample voltage is applied to the hold capacitor C _H
holds the sample voltage. Capacitor C _H is combined with operational amplifier OP, and capacitor C _H
The holding voltage of is taken out to the output terminal of the operational amplifier OP.

This operational amplifier OP is configured as an integrated circuit, and PNP transistors Q ₂ and Q ₃ provided in the input stage and configured as a differential amplifier are configured with extremely good matching. Therefore, the current from transistor Q ₁ , which is the current source for these transistors Q ₂ and Q ₃ , is shunted approximately equally to transistors Q ₂ and Q ₃ . If the current from the current source transistor Q ₁ is I, the currents flowing into the transistors Q ₂ and Q ₃ are each I/2. As a result, the base currents of transistors Q ₂ and Q ₃ are as follows, assuming that the common emitter current amplification factor of these transistors is _hFE
It becomes I/2h _FE . This base current flows into the output side via the feedback loop on the - input terminal side, but flows into the hold capacitor _Cr1 on the + input terminal side, changing the holding voltage value.

In order to prevent fluctuations in the hoard voltage due to this input current, an input current compensation circuit surrounded by a broken line is provided. This circuit consists of transistors Q ₇ to Q _12. Q ₇ has an emitter area exactly 1/2 that of Q ₁ , and the base bias is shared, so the Q ₁ current value becomes a current source of 1/2 of that of Further, Q ₈ has the same shape as Q ₂ and Q ₃ and is arranged at an adjacent position on the integrated circuit pattern so as to obtain the same characteristics as Q ₂ and Q ₃ in the input stage. Since the current of the current source Q ₇ is applied to the emitter of the transistor Q ₈ , the base current of the transistor Q ₈ becomes I/2h _FE ', and h _FE ' is the same as that of Q ₂ and Q ₃ due to matching.
Since it is almost the same as h _FE , it can be considered as I/2h _FE ,
It has the same value as the base current of _Q3 . This current I/
If 2h _FE is connected to the + input terminal, that is, the base terminal of Q ₃ via a current mirror circuit of transistors Q ₁₀ , Q ₁₁ , and Q ₁₂ , the same current I/2h _FE as above flows through Q ₁₁ , and Q ₃ can almost cancel out the base current of That is, most of the base current I/2h _FE of _Q8 flows to _Q10 . The base potential of Q ₁₀ to allow approximately I/2h _FE to flow through Q ₁₀ is set by Q ₁₂ .
Since the base potential of Q ₁₀ is common to that of Q ₁₁ , a current I/2h _FE equal to that flowing through Q ₁₀ also flows through Q ₁₁ . Since this current I/2h _FE is equal to the base current I/2h _FE of Q ₃ , it is possible to cancel the base current of Q ₃ . Note that the current flowing from the base of Q ₁₂ to the emitter of the base current of Q ₈ is approximately the value obtained by dividing the current flowing through Q ₁₀ by the product of h _FE of Q ₁₀ and h _FE of Q ₁₂ . Since they are equal, they can be almost ignored. of a normal PNP transistor obtained in an integrated circuit process.
Since h _FE is low (eg, 100 or less), the base current is quite large, and the error caused by this is large, but the compensation according to the present invention is an effective countermeasure against this. Note that transistors Q ₄ , Q ₅ and Q ₆ in this circuit cooperate with transistors Q ₂ and Q ₃ .

FIG. 2 shows another embodiment of the present invention applied to a comparison circuit, and the configuration and operation for input current compensation are the same as in FIG. 1. However, since this embodiment is configured as a comparator, a unique configuration is adopted. That is, if the − input terminal side is lower than the + input terminal side, most of the current from the current source _Q13 flows to the _Q14 side, so input current compensation must not be performed. Therefore, a transistor Q ₂₅ is provided that turns on when an output appears at the output terminal, so that the input of the current mirror circuit consisting of transistors Q ₂₂ , Q ₂₃ , and Q ₂₄ is set to 0. Note that in this circuit, transistors Q ₁₉ , Q ₂₀ , and Q ₂₁ are respectively Q ₇ , Q ₈ , and Q ₉ in FIG.
corresponds to

Figure 3 shows PNP in the circuits of Figures 1 and 2.
This is shown in an embodiment in which the transistor is replaced with an NPN transistor, and the structure and operation are basically the same.

As described above, the present invention provides another current path in a combination circuit of an amplifier and a hold capacitor so that a current equal to the input current flowing into or out of this capacitor flows, so that the holding voltage of the capacitor is equal to the input current. The amplifier and hold circuit are designed to prevent fluctuations due to influences, and therefore do not complicate the process or process control by using only bipolar integrated circuit technology, and also do not narrow the input voltage range as in Darlington connections. A combination circuit with a capacitor can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention applied to a sample and hold circuit, Figure 2 is a circuit diagram of another embodiment of the invention applied to a comparison circuit, and Figure 3 is a circuit diagram showing another embodiment of the present invention applied to a comparison circuit.
FIG. 3 is a diagram showing an example of a circuit using an NPN transistor. Q...transistor, C _H ...hold capacitor.

Claims (1)

[Claims] 1. In an integrated circuit amplifier in which a hold capacitor is connected to one input end of a pair of input stage transistors in a differential circuit composed of bipolar transistors, the amplifier has the same shape and conductivity type as the input stage transistors. , a compensation transistor to which a current having a predetermined relationship with the current flowing from the current source of the input stage transistor to the input stage transistor is supplied; the current supplied via the compensation transistor is used as an input current to the capacitor; An amplifier comprising: a current mirror circuit that provides a compensation current equal to the current flowing from the capacitor to the input terminal of the one input stage transistor.