JPS6369315A - Variable delay using cmos circuit - Google Patents

Abstract

PURPOSE:To make the control voltage delay time characteristic of a delay circuit comprising multi-stage connection of CMOS circuits linear by comparing an output signal of an adder means with a control signal and supplying its comparison output voltage to the 1st and 2nd delay circuits as a power supply voltage. CONSTITUTION:The 1st delay circuit 1, the 2nd delay circuit 6 and the 3rd delay circuit 11 act respectively like a main delay circuit, a control delay circuit and a standard monitor delay circuit. That is, the phase of the output signal of the 2nd delay circuit 6 is compared with that of the output signal of the 3rd delay circuit 11 to absorb the variance in the CMOS circuit. Moreover, the control range of the delay time of the 1st delay circuit 1 is minimized among control ranges restricted by various factors having dispersion, and phase detection over a wide range around the phase difference of 0 deg. is applied by using flip-flop circuits to constitute a phase detector.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay device formed by connecting CMOS circuits such as CMOS inverters in multiple stages. This can be used in a time axis correction device and the like.

(Summary of the Invention) The present invention comprises a first delay circuit which is made up of multi-stage connected CMOS circuits and to which an input signal is supplied, and a multi-stage connected CMOS circuit.
a second delay circuit made of an OS circuit and supplied with a reference signal of a predetermined frequency; a third delay circuit made of a multi-stage connected CMOS circuit supplied with a predetermined power supply voltage and supplied with the reference signal; A flip-flop circuit is provided in which the output signal of the second delay circuit and the output signal of the third delay circuit are alternately inverted, and the output signal of the second or third delay circuit and the flip-flop circuit are inverted alternately. By adding the output signal and comparing the added output signal and the control l signal, and supplying the comparison output voltage to the first and second delay circuits as the electric voltage, the temperature characteristics of the CMOS circuit can be adjusted. To provide a variable delay device using a CMOS circuit, which compensates for fluctuations in delay time caused by the problem, provides linearity to the relationship between control voltage and delay time, and widens the control range. It is.

[Conventional technology]

Generally, in a video disk player, a video tape recorder, etc., when reproducing an FM-modulated video signal recorded on a disk, tape, etc., time axis fluctuations, so-called jitter, occur. Therefore, in order to obtain a good reproduced image, it is necessary to correct the time axis of the reproduced signal to remove jitter.

Therefore, the present applicant proposed a time base correction device using a variable delay circuit formed by connecting CMOS inverters in multiple stages in Utility Application No. 186871/1987.

A variable delay circuit formed by connecting such CMOS inverters in multiple stages has a characteristic that the delay time changes as shown in FIG. 8 in response to changes in the power supply voltage. These characteristics mean that the time constant curve that occurs at the rise and fall of the on/off output of the CMOS inverter changes in response to changes in the power supply voltage, that is, the voltage of the capacitive load reaches the threshold level of the next stage CMOS inverter. This is caused by the time taken to change depending on the power supply voltage.

The variable delay circuit formed by connecting the above-mentioned CMOS inverters in multiple stages has a drawback that the delay time varies greatly depending on its temperature characteristics. Further, the relationship between the power supply voltage (delay time control voltage) and the delay time has non-linearity as shown in FIG.

Therefore, in Japanese Patent Application No. 61-49994, the present applicant proposed a variable delay device using a CMOS circuit that eliminates the influence of temperature characteristics and changes the delay time linearly with respect to the control voltage.

FIG. 6 shows an embodiment of a variable delay device formed by connecting CMOS circuits in multiple stages according to the above application, and FIG. 7 shows signal waveforms at points A, B, and C in FIG.

In FIG. 6, the first delay circuit 1 has, for example, 30,000
The CMOS inverter 2 of each stage is connected in series, and the maximum controllable delay time difference is, for example, 40 μsec. An input signal S is supplied to this delay circuit 1 from an input terminal 3. This input signal Sl may be, for example, an FM modulated reproduced video signal obtained from a pick amplifier device of a video disc player, and its center frequency is, for example, 8.5 MH2. A delayed signal S2 obtained from the delay circuit 1 at the output terminal 4 is sent to a signal processing circuit including, for example, a subsequent demodulation circuit.

On the other hand, the reference signal generation circuit 5 generates a rectangular wave reference signal of a predetermined frequency, for example, 1.5.MHz, as shown in FIG. 7A, and supplies it to the second delay circuit 6. This delay circuit 6 is C
An MOS inverter 2 connected in multiple stages is used, and is configured together with the first delay circuit 1 in a common chip. Therefore, the first and second delay circuits 1.6 have equal temperature characteristics. Further, the number of connected stages of the CMOS inverter 2 in the second delay circuit 6 is, for example, several hundred compared to 30,000 stages in the first delay circuit l.
There are several steps.

The delayed reference signal shown in FIG. 7B obtained from this second delay circuit 6 is applied to the exclusive OR circuit 7 together with the reference signal shown in FIG. Therefore, this exclusive OR circuit 7
As a result, a pulse signal having a pulse width corresponding to the delay time of the second delay circuit 6 as shown in FIG. 7C is obtained. This pulse signal is converted into a voltage signal (2) through a low-pass filter 8, and then applied to a comparator circuit 9 where it is level-compared with a control signal (2) applied from a terminal 1O. This control signal VCI is, for example, a time axis error signal detected from the reproduced video signal.

The comparison output voltage VCI obtained from the comparison circuit 9 is the first
and is applied to the second delay circuit 1.6 as a power supply voltage, that is, a delay time control signal VC1.

According to the above-described configuration and operation, the voltage signal v1 obtained from the low-pass filter 8 and having a level corresponding to the delay time of the second delay circuit 6 also becomes a signal obtained by detecting the delay time of the first delay circuit 1. .

Along with this, the above-mentioned signal ■Yo and control signal ■. By operating the control loop so that , and are equal, it is possible to compensate for changes in the delay time based on the temperature characteristics of the first delay circuit l, and the control signal ■. .

It is possible to provide linearity to the relationship between and the delay time.

The embodiment described above uses delay circuits 1 and 6 formed by connecting CMOS inverters 2 in multiple stages, but it is also possible to configure a delay circuit by connecting CMOS circuits other than inverters in multiple stages.

[Problem that the invention seeks to solve]

The circuit shown in FIG. 6 described above has a problem in that the control range of the delay time is limited if there are variations in the threshold voltage vtn, temperature characteristics, etc. of the CMOS inverter 2. For example, the delay circuit 1 shown in FIG. , control signal vc! 3~
5V, and as shown in FIG. 9, the delay time can be controlled in the range of TXTa by the threshold voltage vTM, and the delay time can be controlled in the range of TITs by the temperature characteristics. It shall be possible. In such a case, the delay circuit 1 can only be used within a narrow range of the common range T*Ta of the two controllable ranges T t -Ta and TIT3. Conventionally, CMO was used to expand the control range.
The increase in the number of S inverter stages led to an increase in manufacturing costs. Note that although the circuit shown in FIG. 6 can control the delay time to be constant against temperature changes, it cannot compensate for variations in temperature characteristics.

[Means for solving problems]

In the present invention, the first delay circuit is composed of CMOS circuits connected in multiple stages, and includes a first delay circuit to which an input signal is supplied, a circuit for generating a reference signal of a predetermined frequency, and a CMOS circuit connected in multiple stages.
a second delay circuit consisting of an S circuit and supplied with the reference signal; and a CMOS having a predetermined delay time and connected in multiple stages.
a third delay circuit to which a predetermined power supply voltage is supplied and the reference signal is supplied, and an output signal of the second delay circuit and an output signal of the third delay circuit are alternately inverted. a flip-flop circuit, a means for adding the output signal of the second or third delay circuit and the output signal of the flip-flop circuit, and comparing the output signal of the adding means and the control signal; and a comparison circuit that supplies the output voltage to the first and second delay circuits as a power supply voltage.

[Effect].

By comparing the phases of the output signal of the second delay circuit and the output signal of the third delay circuit, variations in the CMOS circuit can be absorbed.

Further, the control range of the delay time of the first delay circuit can be set to the minimum size among the control ranges regulated by various factors that cause variations.

Furthermore, since the phase detector is configured using a flip-flop circuit, phase detection can be performed over a wide range centered on the phase difference of θ°.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 6 are given the same reference numerals.

In this embodiment, a third delay circuit 11, an inverter 12.13, first and second flip-flop circuits 14.15, and resistors R, R1 are provided, and other parts are The structure is the same as that in FIG.

The third delay circuit 11 is formed by connecting CMOS inverters 2 in the same number of stages as the second delay circuit 6, and is supplied with a constant power supply voltage VC3 and connected to the first and second delay circuits 1. It is configured on a single chip, which is common to 6. This voltage VC3 is selected to have a magnitude that minimizes the delay time of the delay circuit 6.11, that is, the maximum voltage in the control range. For example, as described above with reference to FIG. 9, if the control range is 3 to 5 ■, then ■. , =5■ is selected.

The flip-flop circuit 14 is reset at the rise of the output signal at the delay circuit 60B point, and the flip-flop circuit 14 is reset at the rising edge of the output signal at the delay circuit 60B point.
It is set at the falling edge of the signal obtained by inverting the output signal at the 0 point of 1 by the inverter 12, that is, the signal at the 0 point. Further, the flip-flop 15 is set at the rising edge of the signal at point 0, and is reset at the falling edge of the signal at point B, which is the signal obtained by inverting the signal at point B by the inverter 13. The Q output signal of the flip-flop circuit 14 and the Q2 output signal of the flip-flop circuit 15 are added at point D via resistors R2 and R8, respectively, and this added output signal is applied to the low-pass filter 8.

The above flip-flop circuit 14.15, inverter 2
．． 13, resistor R+, R1, and low-pass filter 8 constitute a differential phase detection circuit 16.

Now, the period of the reference signal at point A is T*, V ct =
The above-mentioned minimum delay time of the delay circuit 11 when V C3 is T08, the varying delay time of the delay circuit 6 is Tc, the number of stages of the CMOS inverter 2 of the delay circuit 6.11 is n, and the number of stages of the CMOS inverter 2 of the delay circuit 1 is Number of stages is N, delay circuit l
If the delay time of is T, and Vc: +=5V, then ``rx = 'rc
-・---(1)I becomes. When Vc8 reaches the maximum value VC3, the above equation (2) is as follows: V, = 2.5'
......-(3). At this time, ■1 is a commercial
It remains constant regardless of the amount of delay of the OS inverter 2. Further, when Tc changes, the detection sensitivity S of the differential phase detection circuit 16 becomes T. Here, since T is constant, the detection sensitivity S is CM
(constant) related to the characteristics of the OS inverter 2. Therefore, the comparator circuit 9 obtains the difference between ■ and VCI, and feeds this ■ back to the delay circuit 1.6 to complete this feedback loop. If the gain of T is sufficient for VCI.

becomes linear. Also, the temperature characteristics and threshold voltage of CMOS inverter 2? TH if there is variation in □ etc.
Since IN also varies, 'rc-' in the above equation (2)
Variations are absorbed by r□8.

Figures 2 to 4 show timing charts of the output signals of points B, 0, Q, Q2, and D in Figure 1, and Figure 2 shows the timing charts of the output signals of point B and 0. Figure 3 shows the case where the signal at point B lags the signal at point 0 by T1, and Figure 4 shows the case where the signal at point B lags the signal at point 0 by T1.
! This shows the case where the progress has been made.

If the signal at point B and the signal at point 0 are in phase as in the second case, the frequency component of the reference signal does not appear in the signal at point D, which is the sum of both, and in this case ■, is 2.5■ becomes. Also, depending on the deviation amount T+, Tz between the signal at point B and the signal at point 0, ■,
will increase or decrease around 2.5■.

That is, this differential phase detector 16 can perform phase detection centered on when the phase difference between two input signals is θ''. In this case, the detection range is set to 180'' to 10 iso''. Also, two flip-flop circuits 14
．． 15 is used, so when the signal at point B and the signal at point 0 are in phase, as shown in Figure 2, the output signal Q and the output signal Q2 cancel each other out, and the output signal at point D has the reference value. The carrier component of the signal does not appear, so this phase detector 16 is
If used in a portion where the phase difference between the two input signals is small, the carrier component of the output signal at point D is suppressed, so the burden on the low-pass filter 8 at the subsequent stage is lightened, and its configuration can be simplified.

Further, although FIGS. 2 to 4 and FIG. 7 show cases where the duty ratio of the reference signal is 50%, the phase detector 16 can also be used when the duty ratio of the reference signal deviates.

Figure 5A shows the relationship between the detected voltage and phase when the Q1 output signal is integrated, Figure B shows the relationship between the detected voltage and phase when the Q8 output signal is integrated, and Figure C shows the relationship between the detected voltage and phase when the Q8 output signal is integrated. is Q, the voltage V that is the integral of the sum of the output signal and the Q2 output signal,
shows the relationship between and phase.

The curves shown by dotted lines in A and B in the figure show the case where the duty ratio of the reference signal is 50%, and the curves shown by the solid line show the case where the duty ratio of the reference signal deviates at a ratio of 3:4. As is clear from C in the figure, when the duty ratio deviates, the detection range becomes slightly narrower, and it can be used practically without any problem.

In the embodiment shown in FIG. 1, one of the two flip-flop circuits 14 and 15 is omitted, and the Q1 output signal or Q: output signal of the flip-flop circuit 14 or 15 and the B point or 0 point are used. The set signal and the recent signal of the flip-flop circuits 14 and 15 may be exchanged.

In this embodiment, the first delay circuit 1 functions as a main delay circuit, the second delay circuit 6 functions as a control delay circuit, and the third delay circuit 12 functions as a standard monitor delay circuit. In the present invention, variations in the CMOS inverter 2 are absorbed by comparing the phases of the output of the standard monitor and the output of the control delay circuit.

Therefore, according to this embodiment, the delay time T of the delay circuit 1,
Although the absolute value of VCI varies, it is possible to make the VCI vs. vM linear, and variations in the CMOS inverter 2 can be largely absorbed, thereby making it possible to significantly reduce the number of connected stages. Also, the delay time T of the delay circuit 1. The control range can be set to the minimum size among the control ranges each regulated by various factors that cause variations. For example, in the case of Figure 9 (TI T
3) If > (T! Ta), set the control range to T
2-T, and the conventional control range Tt -T
, can be expanded further. Furthermore, since the phase detection circuit is configured using a flip-flop circuit, phase detection can be performed over a wide range centered on a phase difference of 0''.

〔Effect of the invention〕

Control voltage delay time characteristics of a delay circuit formed by connecting three CMO circuits in multiple stages can be made linear.

In addition, since it is possible to largely absorb variations in the CMO3 circuit, the number of connected stages of the CMO3 circuit can be significantly reduced.
Yields can be improved and manufacturing costs reduced. Furthermore, since the phase detection circuit is configured using a flip-flop circuit, phase detection can be performed over a wide range centered on the phase difference of 0@.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing an embodiment of the present invention;
Fig. 4 is a timing chart of Fig. 1, Fig. 5 is a phase detection characteristic diagram of Fig. 1, and Fig. 6 is a block circuit showing a conventional example of a variable delay device using a delay circuit formed by connecting CMOS inverters in multiple stages. Fig. 7 is a signal waveform diagram of the main part of Fig. 1, Fig. 8 is a graph showing the characteristics of propagation delay time with respect to power supply voltage of a multistage connection circuit of CMOS inverters, Fig. 9 is controlled by variation of CMOS inverter. FIG. 6 is a diagram for explaining that the range is limited. In addition, in the symbols used in the drawings, 1...--...--... First delay circuit 6...--...--...--...-...・・Second delay circuit 11 ・・・・・・・−・・・・Third delay circuit 5・・・・・−・−・・・・Reference signal generation circuit 14.15...--Flip-flop circuit 28, h...-Resistor 9--Comparison It is a circuit.

Claims (1)

[Claims] 1. A first delay circuit which is made up of CMOS circuits connected in multiple stages and to which an input signal is supplied, a circuit which generates a reference signal of a predetermined frequency, and a CMOS circuit which is connected in multiple stages, a second delay circuit to which the reference signal is supplied; a third delay circuit consisting of multi-stage connected CMOS circuits, to which a predetermined power supply voltage is supplied and to which the reference signal is supplied; and a third delay circuit to which the reference signal is supplied. a first flip-flop circuit whose output signal is alternately inverted by the output signal of the circuit and the output signal of the third delay circuit; and the output signal of the second or third delay circuit and the output signal of the first flip-flop circuit. and a comparison circuit that compares the output signal of the addition means with the control signal and supplies the comparison output voltage to the first and second delay circuits as a power supply voltage. A variable delay device using a CMOS circuit consisting of: 2. A second flip-flop circuit that is alternately inverted by the output signal of the second delay circuit and the output signal of the third delay circuit and at a timing different from that of the first flip-flop circuit. an output signal of the first flip-flop circuit and an output signal of the second flip-flop circuit;
CM according to claim 1, wherein the output signal of the flip-flop circuit is supplied to the adding means.
Variable delay device using OS circuit.