JPS6359130A - Line switching device - Google Patents

Abstract

PURPOSE:To prevent a synchronizing switching circuit from being mulfunctioned even with a data signal from a sender side carrier terminal station at a light load by providing the advantage of a conventional line switching device applying synchronizing switching in fL as it is and inputting a data signal from a sender side carrier terminal station to a synchronizing switching period after being subjected to self-scramble. CONSTITUTION:The operation of the synchronizing switching circuit ( SYNCSW) 10-1 is the same as the operation of a conventional synchronizing switching circuit provided with a conventional line switching equipment applying synchronizing switching in fL. Even if a data signal D11 is a light load, the data signal D1 is rich in an AC component by scrambling at a self-scramble circuit (SELFSCRB) 5-1 and data signals D8, D9 compared with a comparator 25 are rich in the AC component. Thus, the detection of coincidence/noncoincidence of both data signals in the comparator 25 is easy and the possibility of malfunction of the SYNCSW10-1 is precluded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line switching device, and more particularly to a line switching device that switches between a working line and a protection line without code errors in a digital wireless communication system.

[Conventional technology]

The large-capacity #I-less communication system is designed to protect against line interruptions due to line maintenance, fading, equipment failure, etc.

It is customary to have a backup line in addition to the working line.

The line switching device connects the signal transmitted by the working wireless line to be switched to the backup wireless line in parallel at the sending end.
The line is switched by switching the two signals transmitted on both the working and protection lines at the receiving end.

If the transmitted signal is a data signal, the transmitting end converts the speed of this data signal and inserts additional bits for wireless line monitoring, and the receiving end performs a system to remove the additional bits from the transmitted data signal. It is necessary to convert the speed to the original data signal, and these data operations are usually performed by the transmitting signal processing circuit and the receiving signal processing circuit of the single line switching device.

There may or may not be a propagation delay difference between the working and protection lines to be switched, and this propagation delay difference may vary due to fading, etc., so the timings of the two transmitted data signals do not necessarily match. Even if the fixed component i of the propagation delay difference is compensated in advance.

If the fluctuation component becomes larger than one clock period of the data signal, a code error will occur during switching at the receiving end.

In order to avoid this code error, a line switching device is used that includes a synchronization switching circuit that performs bit synchronization between two transmitted data signals before switching.

A line switching device having such a synchronous switching function includes:

Synchronous switching is performed within the section where the speed is being converted by the transmitting signal processing circuit and receiving signal processing circuit.

2 with synchronous switching outside the section where speed conversion is being performed
There are different types. Depending on the level of the clock frequency at the stage of synchronous switching, the former is called synchronous switching at fH, and the latter is called synchronous switching at fL.

In a line switching device that performs synchronous switching at fH, prior to synchronous switching, the output data signal of the transmission signal processing circuit for the working radio line to be switched is connected in parallel to the backup radio line by the transmission switching circuit. The backup wireless line in standby usually transmits a test pattern, and the transmission signal processing circuit for the backup wireless line that inserts additional VIVTO into this test pattern operates asynchronously with the transmission signal processing circuit for the active wireless line. Therefore, the clock of the data signal output to the standby radio line is also changed during parallel connection in the transmission switching circuit.

If the clock changes discontinuously, the modulator of the backup radio line may become out of synchronization, and it may take a long time to recover. Therefore, the transmission switching circuit needs to have a clock buffer function so that the clock does not change discontinuously. In addition, it is necessary to transmit additional bits unique to each active wireless line and backup wireless line, such as a line identification code, and when connected in parallel, additional bits cannot be inserted in the transmission signal processing circuit for the backup wireless line. The switching circuit must also have an additional bit rewriting function.

The two data signals transmitted in parallel on the working radio line and the backup radio line are first frequency-divided by N in a synchronous switching circuit, and each is converted into two data signals in N columns. Due to phase uncertainty in frequency division.

Generally, the column order of the two frequency-divided data signals does not necessarily match. That is, it is generally uncertain in which column a particular data bit in a data signal before frequency division is placed after frequency division. However, the two data signals before frequency division by 1 each include a frame synchronization bit inserted by the transmitting signal processing circuit for the working wireless line, and by using this frame synchronization bit as the phase reference for branching,
The synchronous switching circuit can match the column order of the two frequency-divided data signals. Due to frequency division, the clock period of the data signal becomes longer by riN times. The value N is set so that the clock period after frequency division is longer than the fluctuation component of the propagation delay difference. As a result, typing occurs in which the respective bits of the two data signals after frequency division by 1 match each other, and since the synchronous switching circuit performs switching in this typing, no code error occurs at the time of switching. The switched data signal riN is multiplied and parallel-to-serial converted to reproduce the same data signal as that output from the transmitting signal processing circuit for the working wireless line. This completes the synchronous switching. The frame synchronization bit in the data signal manually input to the synchronization switching circuit via the backup wireless line is changed from the one inserted in the transmission signal processing circuit for the backup wireless line to the transmission signal for the working wireless line by parallel connection by the transmission switching circuit. Since these two frame sync bits are asynchronous to each other depending on what was inserted by the processing circuit, it takes time for the sync switching circuit to detect the new frame sync bit (frame synchronization is re-established). , during this period, the synchronous switching operation is interrupted.

In a line switching device that performs synchronous switching using fL.

Prior to synchronous switching, the data signal that is being manually sent to the transmission signal processing circuit for the working wireless line to be switched is connected in parallel to the transmission signal processing circuit for the backup wireless line by the transmission switching circuit. Since the transmission signal processing circuit has a clock buffer function for speed conversion, this parallel connection allows the clock of the data signal output to the backup wireless line to
Since cVC does not change and the additional bit inserted into this data signal also does not change, the transmission switching circuit does not need a clock buffer function or an additional bit rewriting function. The two data signals transmitted in parallel on the working wireless line and the backup wireless line are processed by the receiving signal processing circuit for the working wireless line and the receiving signal processing circuit for the backup wireless line, respectively, and then sent manually to the transmitting signal processing circuit. The data signal is restored to the original data signal. The two restored data signals are input to the synchronous switching circuit.

FIG. 2 is a prologue diagram showing an example of a synchronous switching circuit included in a line switching device that performs synchronous switching at fL.

The outputs of the received signal processing circuit for the working radio line and the received signal processing circuit for the backup radio line are data signals D4 and D5.

The synchronous switching circuit shown in FIG. 2 divides the frequency of the data signals D4 and D5 by N, converts them into negative column parallel, and converts the data signals D4 and D5 into N columns of data signals D6 and D7.
Negative column parallel conversion circuits 21 and 22 output data signals D6 and D70 under the control of exchange signals C82 and C83.
Swapping circuits 23 and 24 output the column order as data signals D8 and D9, and compare the data signals D8 and D9 for each column, and output swapping signals C82 and C83 in response to the comparison result and the switching instruction signal C81. and switching control signal C8
A comparison circuit 25 that outputs 41 outputs, a switching circuit 26 that selectively outputs either data signal D8 or D9 under the control of a switching control signal C84, and a data signal that is obtained by multiplying the output of the switching circuit 26 by N and converting it into parallel and serial data. It is configured to include a parallel-to-serial conversion circuit 27 that outputs as D1.

Due to the parallel connection at the sending end by the transmission switching circuit, the contents of the data signals D4 and D5 are equal, but the timings do not necessarily match.

Since the data signals D4 and D5 do not have frame synchronization inserted by the transmission signal processing circuit and a bit suitable for a phase reference for branching such as -y), the column order of the data signals D6 and D7 does not necessarily match. However, for example, if a certain bit of the data signal D4 is arranged in the i-th column of the data signal D6 (N≧i≧1), the next bit of the data signal D4 after this certain bit is the data signal D6. Since the data signals D6 and D7ri are arranged in the column next to the i-th column (the next after the N-th column is the 1st column), the data signals of each N column of the N sets with cyclically different column orders are arranged. It's either one or the other. The switching circuits 23-24 cyclically switch the order of each column of the data signals D6 and D7 one by one while the switching signal C82@C83 is input, and output the result. The comparison circuit 25 receives the data signal D8.
A value N is set so that corresponding bits of D9 can be compared. This setting is performed by setting the value N so that the clock period of the data signals D8 and D9 is longer than the conversion component of the propagation delay difference between the working radio line ftM and the backup radio line.

When the switching instruction signal C8l instructs synchronous switching from the working wireless line to the protection wireless line, the comparison circuit 25 generates a switching signal C83 if the comparison result is inconsistent. the result,
The switching circuit 24ri starts switching the order of the tie No. A D70 column. When the replacement of each scan is repeated a maximum of (N-1) times, the data signal D9 always matches the data signal D8 during that time, and the replacement signal C83ri is stopped. When the comparison circuit 25ri stops outputting the switching signal C83, the switching side 81I signal C84
The switching circuit 26 is controlled by the data signals D8 and D9.
The data signal D9 is selectively output by matching the respective bits. As a result, the data signal Dir
i. The data signal D5, that is, the restored data signal via the backup wireless line, completes the synchronous switching.

Note that when the current wireless line is being used normally, the replacement signals C82 and C83rt are not generated.

Since the switching control signal C84 controls the switching circuit 26 to selectively output the data signal D8, the data signal D1ri
This is the restored theta signal D4.

As explained above in Synchronization switching in fL, the synchronization switching circuit does not use the frame synchronization bit, and the reception signal processing circuit requires the frame synchronization bit for its data manipulation, but the transmission switching circuit does not use the frame synchronization bit. Frame synchronization bit ri in the data signal output to the backup radio line by parallel connection
Because it doesn't change.

The synchronization switching operation is not interrupted due to frame synchronization at the receiving end.

However, if the data signal to be transmitted (data signal DI using the reference numeral in FIG. 2) has a light load, most of the data signals other than the frame pattern inserted by the transmitting carrier terminal station are
When there is no alternating current component, there is almost no alternating current component of the data signals D8 and D9.

It is extremely difficult for the comparator circuit 25 to detect whether the two data signals match or do not match, and even a slight line code error may cause a false fault to determine a match and cause a malfunction.

[Problem to be Solved by the Invention 9] As explained above, when performing synchronous switching using conventional line switching devices ri and fH, a transmission switching circuit with a complex configuration having a clock buffer function and an additional VIVTO rewriting function is required. Therefore, it is expensive, and it takes a long time to re-establish frame synchronization at the receiving end when parallel connections are made in the transmission switching circuit, so the switching time is long.

Since the transmitting signal processing circuit and the receiving signal processing circuit are located outside the synchronous switching section, there is a drawback that deterioration in line quality caused by these circuits cannot be relieved by synchronous switching. Although all of these are solved, there is a drawback that malfunctions may occur if the transmitted data signal is under a light load.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching device that performs synchronous switching at fL and is free from malfunction even when the transmitted data signal is under a light load.

[Means for solving problems]

The line switching device of the present invention converts the speed of the first data signal and inserts a first additional bit for monitoring the working wireless line, and sends out the second data signal to the working wireless line. A third data signal obtained by converting the speed of the first data signal and inserting a second additional bit for monitoring the standby radio line as necessary is also transmitted in parallel to the standby standby radio line. The second and third data signals transmitted on the working wireless line and the backup wireless line are transmitted, the first and second additional bits are removed, the speeds are converted, and the fourth and fifth data signals are generated. and negative column parallel conversion of these fourth and fifth data signals to obtain sixth and seventh data signals each consisting of a plurality of columns, and converting these sixth and seventh data signals into respective columns of said columns. The column order is compared to detect whether or not the column order matches. If there is a mismatch, the column order is changed to match the column order to obtain the eighth and ninth data signals. In a line switching device that selects one of the bits at matching timing and performs parallel-to-serial conversion to obtain a tenth data signal that is equal to the first data signal, the tenth data signal from the transmitting carrier terminal station is a scrambling circuit that self-scrambles a data signal and outputs it as the first data signal; a scrambling circuit that self-descrambles the tenth data signal and outputs a twelfth data signal equal to the tenth data signal; It can be configured with a descrambling circuit that outputs to the station.

〔Example〕

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a line switching device according to the present invention.

The implementation shown in FIG. 1 is used in a digital radio communication system consisting of a working radio line and a standby radio line. HYB (hereinafter referred to as HYB) 1-1 to l-, each branching into two, and a test pattern generator (hereinafter referred to as TESTPG) 2.
One minute output of each of HYBI-1 to 1- and T
A switch 3 that inputs the output of the E8TPG2 and outputs one of these inputs, and a bipolar/unipolar conversion circuit (hereinafter referred to as B-[1) that outputs the output of the switch 3.
B-[14-1 to 4-, B-0 which inputs the other branch output of each of 4-0 and )IYBl-1 to 1-
A self-scramble circuit (hereinafter referred to as 8ELFSCRB) that inputs the output from 4-U to 4- to 5-0 to 5-%
Output of 5RLFSCRBs-o and 5RLFSCR
A transmission switching circuit (hereinafter referred to as TXSW) 6 which inputs one of the two outputs of each of B5-1 to B5-5-, and TX8W6
A transmission signal processing circuit C which outputs the output of the input C data signal D3 to the backup radio line is hereinafter referred to as TXDPU 5) 7-0.

The other of the two outputs of each of the 5ELFSCRBs 5-1 to 5- is input to the TXDPUs 7-1 to 7-7-, which output the outputs to the corresponding working wireless lines.

a reception signal processing circuit (hereinafter referred to as RXDPU) 8-0 that inputs the output of the backup wireless line and outputs the data signal D5;
RXDPU8 inputs each output of the working wireless line
-1 to 8-, a received signal distribution circuit (hereinafter referred to as RXDI8T) 9 that branches the data signal D5 (k+l);
One of the branch outputs of XDIST9 and RXDPU8-1
A synchronous switching circuit (hereinafter referred to as 5YNC) that manually outputs the output to ~B-
8W) 10-1 to 10-, R, XDI8T9
・Cell 7 descrambling circuit (hereinafter referred to as SgLFDSCRB) 11-0 to 11-, which inputs the output of 5YNC8W1o-1 to 10-, and 8ELFDSCR,B11
-0 to l'l-, unipolar/bipolar conversion circuits (hereinafter referred to as U-B) 12-0 to 12-, test pattern detectors (hereinafter referred to as 'rgs'rpD) 13, and U -812-0 to 12-, the U-812-00 output to TBSTPD13, and the rest to the receiving carrier terminal station (not shown).
-B All but one of 12-1-12- and U
-812-0 to the receiving carrier terminal station.

First, the operation of the embodiment shown in FIG. 1 will be described for the case where all the wireless lines are normal and the backup wireless line is on standby.

The data signals from the transmitting carrier terminal station are usually bipolar signals, and one of them, for example, the data signal D11 is HYBl.
-1, and is input to B-TJ4-1 and converted into a unipolar signal. 5ELFSCRB5-1rtB-U4-1
2>Z Self-scrambles the output uniform signal and outputs it as a data signal D1. The TXDPU7-1 converts the speed of the data signal D1 and converts the frame synchronization bit.
A frame is constructed by inserting additional bits such as a parity check bit, line identification ID code, and digital boobis channel signal, and is scrambled with a scrambling pattern synchronized with this frame and output as a data signal D2. The data signal D2rt is transmitted through one of the working radio channels and input to the RXDPU 8-1. RXDPU8-
1rlt, the 7 frame synchronization bits inserted in the data signal D2 are detected and frame synchronized, and the detected frame synchronization bits and V bits are used to reverse the data conversion in TXDPU7-1, and the data signal Output as D4. The data signal D4 is equal to the data signal Di outputted by 8ELP8CRB5-1. This data signal D4 (DI)
In this case, 8 B L through 5YNC8W10-1
Manually insert FDSCRB II-1 into 5ELFSCRB5-
The scramble at 1 is descrambled and the descrambled data signal becomes -L=[1-812-1 again -L=
The polar signal is converted into a bipolar signal, restored as a data signal Dll, and sent to the receiving carrier terminal station via the switch 14.

TESTPO2ri test pattern is generated.

In this case, this test pattern is
-0-5RLFSCRB5-o -TXSW6-TXD
PU7-0・Spare radio line・RXDPU8-0・RXD
IST9・5ELFD8CRB11-0・U-B12-
It is transmitted through the path of the 0/0 switch 14 in the same way as the data signal Dll, and is manually input to the TgSTPD 13 and used for monitoring the backup radio line.

Next, the operation of the embodiment shown in FIG. 1 will be described with respect to a case where one of the working radio lines is synchronously switched to a backup radio line for deterioration of line quality due to fading or the like or for line maintenance.

For example, assume that the line quality of the working wireless line transmitting the data signal D2 has deteriorated. The RXDPU 8-1 monitors the line quality of this working wireless line using the parity check pit in the data signal D2. RXDPU8-1
When detecting deterioration in line quality, the 1 line switching control unit fl!
(not shown) controls TX8W・6 and TXDPU7-
0 human power is switched from the previous output of 8ELFSCRB5-0 to the data signal D1. That is, the sending ends are arranged in parallel. As a result, there are differences in the data signal D7ri transmitted on the backup radio line, the additional bit part, and the TXDPU.
The same rc as the data signal D2 is obtained except for the pattern repetition phase of the scramble by 7-0. TX8W6 only needs to have a switch function to selectively output one of the input data signals.

And regarding the fact that the frame synchronization of RXDPU 8-0 will not be lost due to sending end parallelism [prior art]
This has already been explained in the section.

By parallel sending end, 9. The data signal D5 outputted by the RXDPU 8-0 is also the same as the data signal D1 outputted by the 5ELFSCRB 5-1. However, as already mentioned, 5Y
The timings of the data signals D4 and D5 input to the NC8WIU-1 do not necessarily match due to the propagation delay difference between the working radio line and the backup radio line. Of the propagation delay difference, the fixed component is YNC8W10-1 is used to compensate in advance. 5YNC8WI 0-1rt, data signal D4
Data signal D1 to be output after bit synchronization between -D5
of.

From the data signal D4 that had been output until then, the data signal D
5 without code error. This completes the synchronous switching.

The operation of 8YNC8W10-1 is the same as that of a synchronous switching circuit included in a conventional line switching device that performs synchronous switching at fL, and the synchronous switching circuit shown in FIG.
-1.

The following description will be made assuming that 5YNC8WI O-1 is shown in FIG.

Even if the data signal Dll has a light load, the 5ELF8CR
By scrambling at B5-1, the data signal DI(
D4 and D5)ri are rich in alternating current components, and therefore the data signals D8 and D9 compared in the comparator circuit 25 are also rich in alternating current components. Detection is easy and 5YNC8WIO-
There is no risk that 1 will malfunction.

8ELF8CRB5-1 scrambles the data signal D1 (therefore, the data signal D8
・D9) needs to have an AC component, so its scrambling pattern can be a pattern with a short repetition period. Therefore, 5RLFSCRB5-1・5ELFDSCR
BI 1-1 can be constructed inexpensively.

Synchronous switching from another working radio line to a backup radio line is also performed in the same manner as in the above case.

If the line is momentarily disconnected due to equipment failure or the like, synchronous switching is not possible, so the switching devices 3 and 14 are used to switch the line. For example, if the data signal Dll is input to the B-04-0 via the HYBl-1 switch 3, then the U-812-C
By outputting the output of I to the receiving carrier terminal station via the switch 14, the working radio line for transmitting the data signal 1) I It- is switched to the backup radio recall line.

〔Effect of the invention〕

As explained above, the line switching device (b) of the present invention is explained in detail.
Since the synchronous switching is performed at fL, the configuration of the transmission switching circuit is simple and economical, and since the frame synchronization does not occur at the receiving end when the sending end is parallel, the switching time is short and the synchronous switching interval is wide. fL, which can relieve line quality deterioration caused by signal processing circuits and received signal processing circuits with synchronous switching.
It still has the advantages of the conventional line switching device that performs synchronous switching in It has the effect that there is no risk of the synchronous switching circuit malfunctioning even when the signal is under a light load, and it is also economical because the self-scramble circuit and self-descramble circuit that are added need only have a simple configuration. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the line switching device of the present invention. FIG. 2 is a block diagram showing an example of a synchronous switching circuit. 5-0 to 5-k... Self-scramble circuit. 6... Transmission switching circuit, 7-0 to 7-k...
...Transmission signal processing circuit, 8-0 to 8-k...Reception signal processing circuit, 9...Reception signal distribution circuit, 1
0-1~10-k...Synchronous switching circuit, 11-0
~11-k...Self-descrambling circuit.

Claims (1)

[Claims] A second data signal obtained by converting the speed of the first data signal and inserting a first additional bit for monitoring the working wireless line is transmitted to the working wireless line, and if necessary, the first data signal is transmitted to the working wireless line. A third data signal obtained by speed converting the data signal and inserting a second additional bit for monitoring the backup wireless line is sent in parallel to the standby backup wireless line, and the working wireless line and The first and second additional bits are removed from the second and third data signals transmitted on the backup wireless line, the speeds are converted to obtain fourth and fifth data signals, and the fourth and fifth data signals are The fifth data signal is subjected to negative column parallel conversion to obtain sixth and seventh data signals each consisting of a plurality of columns, and these sixth and seventh data signals are compared for each of the columns to determine the column order. Matching/mismatching is detected, and if there is a mismatch, the column order is changed to match and the eighth and ninth data signals are obtained, and at the timing when the respective bits of these eighth and ninth data signals match. In a line switching device that selects one of them and performs parallel-to-serial conversion to obtain a tenth data signal equal to the first data signal, the eleventh data signal from the transmitting carrier terminal station is self-scrambled and the eleventh data signal is a scrambling circuit that self-descrambles the tenth data signal and outputs a twelfth data signal equal to the eleventh data signal to the receiving carrier terminal station; A line switching device characterized in that switching between working and protection can be performed without malfunctioning even when the input signal load is light by providing a circuit for switching scrambled signals from the working side on the protection transmission side.