JPS635640A - Channel controller in data transmission system - Google Patents

Abstract

PURPOSE:To lighten the burden imposed on a MPU, to use a small-sized MPU 7 and to secure the utilizing efficiency of plural channels by expanding and converting the arbitrary same channel signal in each time slot into low speed continuous signals exceeding the channel time length. CONSTITUTION:A receiver 3 connected to a transmission line 1 for an exchange signal has an amplifier circuit, a filter circuit, a modulator circuit, etc., demodulates a data signal from said transmission line 1, outputs a signal and is connected to a synchronizing circuit 5. A flip flop circuit 13 has a function to convert the data signal of a specific channel, which is outputted from a channel selection gate circuit 11, into the low speed continuous signals expanded to one frame time length 125 mus, and is connected to a serial communication interface 15. It serially processes the expanded low speed continuous signals from the flip flop circuit 13 and connects it to the MPU 7 and outputs transmission data from the MPU 7 to a register 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a channel control device in a data transmission system, and particularly to a channel control device in a data transmission system, and in particular, in a private branch exchange system or other local network, the present invention relates to a channel control device for controlling a digital signal including voice data between a plurality of terminals in a private branch switching system or other local network. The present invention relates to a channel control device suitable for a data transmission system for mutually transmitting and receiving data.

(Summary of the Invention) The present invention provides a receiving means for receiving and demodulating a data signal connected to a transmission line for transmitting and receiving, and having a predetermined cycle as one frame and dividing this frame into a plurality of channels including a synchronization channel; Synchronization detection means for detecting the synchronization signal from the output signal of the reception means, and a channel for selecting an arbitrary channel from the plurality of channels based on the signal timing from the synchronization detection means and outputting the signal of the selected channel. selection means; low-speed conversion means for expanding and converting the signal from the channel selection means into a low-speed continuous signal having a time length equal to or longer than the channel length; and a continuous signal for creating continuous data of the selected channel from the output signal of the low-speed conversion means. The MPU processing for each channel can be omitted by expanding a high-speed burst signal in an arbitrary channel within a frame into a low-speed continuous signal of one frame time length and outputting it continuously. This reduces the burden on the MPU.

(Prior art and its problems) Conventionally, PCM data signals in digital exchanges in circuit-switched communication systems and data signals in bus-type circuit-switched communication systems have a predetermined period of one frame, as shown in Figure 3. (for example, 125 μs), and has a pit stream structure in which this frame is divided into a plurality of time slots, and each time slot is divided into a synchronization channel SYN, a data transmission/reception channel Ch+, ch2 .・・・
- chE (for example, 5 μs for each channel).

The reception format for such data signals is to store the data in any channel used between the connected devices among the divided multiple channels in the -H memory, and then transfer the stored data to the next Processing was performed by the MPU when the same channel of a frame ran.

However, in such a system, in a configuration in which channel data is stored in a memory and read out every multiple frames, M
The PU is required to process interrupts in real time for each 5 μs wide channel that occurs every 125 μS, and the MPt
The load on J increases, and to improve this, an MPU with a large processing capacity is required.

In general, in the conventional system, when multiple channels within the same frame are used, the MPU is required to have even higher real-time processing ability, and there is a risk of exceeding the limit of the MPU's processing ability.

(Purpose of the Invention) The present invention was made in order to solve these conventional drawbacks, and it expands the time slot of the transmitted and received signals, which is a feature of the line conversion method, into a serial signal that is a continuous signal for each same channel. The present invention provides a channel control device in a data transmission system that can reduce the burden on the MPU, reduce the size of the MPU, and ensure efficient use of a plurality of channels.

(Configuration and Effects of the Invention) In order to achieve such an object, the present invention is configured to connect a transmitting/receiving transmission line, have a predetermined cycle as one frame, and divide this frame into a plurality of channels including a synchronization channel. A receiving means for receiving and demodulating a data signal, a synchronization detecting means for detecting a synchronization signal from an output signal from the receiving means, and an arbitrary channel among the plurality of channels is selected based on the signal timing from the synchronization detecting means. a channel selection means for outputting a signal of the selected channel; a low-speed conversion means for expanding and converting the signal from the channel selection means into a low-speed continuous signal having a time length equal to or longer than the channel length; continuous data creation means for creating continuous data of the selected channel from the signal;
The receiving means.

The control means controls the channel selection means, the low-speed conversion means, and the continuous data creation means.

According to the present invention, since continuous data is created by expanding and converting the signal in any channel into a serial signal that is a continuous signal, it is no longer necessary for the MPU to perform interrupt processing for each channel of each frame, and the MPU The burden is reduced and processing can be done with a compact configuration.

(Explanation of Examples) The present invention will be explained in detail below.

FIG. 1 is a block diagram showing an embodiment of a channel control device in a data transmission system according to the present invention.

In FIG. 1, a receiver 3 connected to the transmission line 1 for transmission and reception signals has an amplifier circuit, a filter circuit, a demodulation circuit, etc., and demodulates the data signal from the transmission line 1 for transmission and reception signals and outputs the signal. and is connected to the synchronous circuit 5.

The output signal from the receiver 3 is of a so-called pit stream type, as shown in FIG. Has multiple data channels.

A synchronization circuit 5 connected to the receiver 3 uses a predetermined synchronization pattern, for example, if the synchronization signal is 8 bits long, all signals are
This circuit compares and verifies the signal pattern of the synchronization channel in one frame of the pit stream inputted from the receiver 3, and if the timing signal is matched, the timing signal is transmitted via the bus 6. It is output to the MPU 7.

The MPU 7 has the functions of creating transmission data, creating reception data, decoding the reception data, controlling connections, and synchronizing with other timing signals from the synchronization circuit 5.

Furthermore, the MPtJ 7 has a function of outputting a channel designation control signal synchronized to an arbitrary channel based on the timing signal from the synchronization circuit 5 to the time slot gate circuit 9.

The time slot gate circuit 9 generates a plurality of time slots by dividing a predetermined period into one frame based on the timing signal from the synchronization circuit 5, for example, and generates a plurality of time slots. It has an AND circuit etc. that outputs the sum, and the gate signal GIIG2
This outputs the following. That is, when the channel designation control signal from the MPU 7 matches the same channel within one frame, gate signals G+ and G2 as shown in FIG. 2B and E are output.

Output from receiver 3 and time thrower 1 to game 8 circuit 9
The two-manual channel selection gate circuit 11 to which the gate signal G1 from the time slot gate circuit 9 is input is in the pit stream of the receiver 3 and while the gate signal G from the time slot gate circuit 9 is being output, the high-speed burst It has the function of applying a signal to the flip-flop circuit 13, and has the function of outputting only the data signal of the designated channel designated by the MPU 7 among each channel, as shown in FIG. 2C.

The flip-flop circuit 13 converts the data signal of the specific channel output from the channel selection gate circuit 11 into a second
As shown in the figure, it has a function of converting into a low-speed continuous signal expanded to one frame time length of 125 μs, and is connected to a serial communication interface 15.

The serial communication interface 15 has the function of processing the decompressed low-speed continuous signal from the flip-flop circuit 13 into serial data, connecting it to the MPU 7 via a bus, and outputting the transmission data from the MPU 7 to the register 17.

The register 17 has a function of temporarily holding transmission data from the serial communication interface 15, and
A transmission signal is outputted to the transmitter 19 within a channel specified by the MPU 7 based on a gate signal G2 from the time slot gate circuit 9 based on support from the MPU 7.

The transmitter 19 modulates the transmission data signal inputted from the register 17 and outputs it to the transmission line 1 for transmission and reception signals, and includes a modulation circuit and a filter circuit.

It has an amplifier circuit, etc.

Next, the operation of the channel control device in the data transmission system of the present invention will be explained.

The received data signal is transmitted from the transmission line 1 for transmitting and receiving signals to the receiver 3.
When the pit stream signal is inputted to the receiver 3, a pit stream signal as shown in FIG. For example, in the case of PCM24 system, this pit stream signal is 1.5 Mb.
ps, which is 2 Mbps in the case of the 32 system.

In the synchronization circuit 5, the signal pattern of the synchronization channel in the pit stream and the specific bit pattern in the synchronization circuit 5 are compared and verified, and when both match, the timing signal is
The signal is output to the PU 7 and the entire device is synchronized.

When synchronization is established, the MPU 7 outputs a channel designation control signal synchronized with any channel n to be received to the time slot gate circuit 9, and the time slot gate circuit 9 outputs a channel designation control signal synchronized with any channel n to be received, and the time slot gate circuit 9 A gate signal G is outputted to the channel selection gate circuit 11 during the time period, and the gate of the channel selection gate circuit 11 is opened at the timing of channel n.

Therefore, in the channel selection gate circuit 11, only the 8 bits in the designated channel in the pit stream are
The signal is output as shown in FIG. C and added to the flip-flop circuit 13. In other words, the signal on this day's channel is 125μ
The signal is input to the flip-flop circuit 13 in burst every s.

In the flip-flop circuit 13, the input signal is expanded and converted into a low-speed continuous signal in one frame, and is output from the first pit to the serial communication interface 15 as a 64 Kbps continuous signal as shown in the second diagram.

The serial communication interface 15 receives the input 64Kbp
MP by processing the continuous serial signal of S.
A continuous data signal is generated by outputting the bus to U7.

On the other hand, during transmission, a transmission data signal is input from the MPU 7 to the register 17 via the serial communication interface 15, and the input signal is temporarily stored in the register 17.

In the register 17, the gate to which the gate signal G2 (E in FIG. 2) is input opens at a timing synchronized with the arbitrary channel n to be transmitted supported by the MPU 7, and the gate is opened at 1.5 M bps as shown in F in FIG. or 2MbpS
is applied to the transmitter 19 with a shift clock of
sent to.

Thus, in the present invention, there is no need for the MPU 7 to execute real-time interrupt processing operations for each channel of each frame when receiving and transmitting data signals.

In the channel control device applicable to the data transmission system of the present invention described above, the receiver 3 includes a channel selection gate circuit 11 for one channel. Flip-flop circuit 13. An example has been shown in which the serial communication interface 15 is connected, and the received data for n channels is expanded and converted into a low-speed continuous signal.

However, in the present invention, these channel selection gate circuits 11 . It is also possible to construct a structure by connecting a plurality of sets of flip-flop circuits 13 and serial communication interfaces 15, and by configuring the time slot gate circuit 9 to output a plurality of gate signals that sequentially open the gates according to the channel order. , multiple channel signals are processed by MPU for each frame
7 can be received in real time without interrupt processing. In short, it may be performed on any channel or all channels depending on the purpose.

Normally, in the same terminal device, 8K [3 yt
Although the transmission capacity is only e/sec, it can be increased by the present invention.

In the configuration of the transmitting means, if register cores corresponding to a plurality of channels are provided and sequential switching is controlled by the time slot gate circuit 9, signals of a plurality of channels can be similarly transmitted without placing a burden on the MPU 7. Can be done.

Furthermore, in the present invention, it is not necessary that any channel data to be decompressed be one frame long, and it is sufficient that it is at least the time length of the channel band, as described above, the channel control device in the data transmission system of the present invention. is configured to expand and convert any same-channel signal in each time slot into a low-speed continuous signal longer than the channel time length, so there is no need for the MPU to perform interrupt processing in real time for each channel in each frame. The burden on the MPtJ is reduced, a small MPU 7 can be used, and the efficiency of using a plurality of channels is ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a channel control device in a data transmission system according to the present invention, FIG. 2 is a waveform diagram of the main parts in FIG. 1, and FIG. 3 is a data signal pit in the data transmission system. This is a diagram showing a stream. 1... Transmission line for transmitted and received signals 3... Receiver 5... Synchronous circuit 7... MPU 9... Time slot gate circuit 11... CC selection gate circuit 13... Flip-flop circuit 15...Serial communication interface 19...Transmitter Fig. 1 Fig. 2

Claims (1)

[Claims] (1) Receiving means connected to a transmission line for both transmitting and receiving purposes, and receiving and demodulating data signals in which one frame has a predetermined period and is divided into multiple channels including a synchronization channel; and an output signal from this receiving means. a synchronization detection means for detecting a synchronization signal from the synchronization detection means; a channel selection means for selecting an arbitrary channel among the channels based on the signal timing from the synchronization detection means and outputting a signal of the selected channel; low-speed conversion means for expanding and converting the signal of the means into a low-speed continuous signal having a time length equal to or longer than the channel length; continuous data creation means for creating continuous data of the selected channel from the signal of the low-speed conversion means; and the receiving means;
1. A channel control device in a data transmission system, comprising: control means for controlling a channel selection means, a low-speed conversion means, and a continuous data creation means.