JPH0642668B2 - Data exchange system - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a data exchange system.

[Technical background of the invention and its problems]

Usually, data transmission is performed by a network centered on a switch. In the early days, the network was also provided exclusively, but as the application and disassembly of data transmission spread, the flexibility of the network has been required.

For example, a data terminal (Data t
erminal equrpment; hereinafter abbreviated as DTE. Since many types have been developed, it is desirable that any type of DTE can be connected to the network. It is a necessary element when forming a system that integrates the currently widespread networks.

However, DTE has synchronous and asynchronous transmission methods. DTE is also classified according to the transmission speed. 48Kbp
s There is a DTE with a transmission speed such as 9.6kpbs. However, the transmission speed of DTE is set to a common divisor of 48 kbps.

Therefore, it is basically impossible to connect these different DTEs to the same network. For example,
Synchronous and asynchronous DTEs cannot be connected to the same network. This is because the same data transmission form is required on the transmission line in the network. However, when a DTE pair that differs only in transmission speed is connected to the network, the transmission speed according to the maximum transmission speed among the connected DTEs is used inside the network,
For lower-speed DTE, a data terminal interface device (hereinafter abbreviated as DIE) is provided with a function of transmitting a dummy signal to cope with a change in DTE. However, in this case, sending the dummy signal itself is not preferable because it causes a load on hardware and software, and further, when the dummy signal is received,
It is necessary to separate this dummy signal from the significant signal,
The circuit has become complicated.

[Object of the Invention]

It is an object of the present invention to eliminate the above drawbacks and provide a data exchange system capable of performing transmission between a DTE and an exchange in the same format regardless of the type of DTE. That is, when a DTE pair having a lower transmission speed than the transmission speed between the DIE and the exchange is connected to the DIE,
An object of the present invention is to provide a data exchange system capable of smoothly transmitting data via an exchange.

[Outline of Invention]

According to the present invention, data transmission between a first data terminal and a second data terminal is performed via an exchange, data from the first data terminal on the transmitting side is sampled at one point or multiple points, and the sampled data is received. In the data exchange system in which the data is restored on the side and transmitted to the second data terminal, the data is delayed on the receiving side for a predetermined time.
The clock signals supplied to the transmitting side and the receiving side are in phase synchronization with each other, and the delay time is determined based on this clock signal.

When the first and second data terminals are of the synchronous type, a data clock signal for data transfer and reception is supplied according to the transmission speed of the first and second data terminal ports and the data terminal, and the data clock signal Is set as a multiple of the cycle of the clock signal described above. Then, these signals are phase-synchronized, and the second delay is performed at the same timing as the data transfer timing from the first data terminal by the delay time described above.
The data terminal receives the data. When the first and second data terminals are asynchronous, the supply of the data clock signal is simply stopped and the other configurations are unchanged.

〔The invention's effect〕

In the present invention, the data transmission on the subscriber line is the same regardless of the type of data terminal, and if the type of data terminal is different, only the data clock signal supplied to the data terminal needs to be changed. Therefore, no matter what kind of data terminal is connected in the system, the system itself
A flexible configuration is possible without requiring other changes.
That is, even when a data terminal pair having a transmission speed lower than that of the exchange is connected, the system itself does not need to be significantly changed, so that the flexibility of the data exchange system is significantly increased.

Example of Invention

Next, an embodiment of the present invention will be described with reference to the drawings. In the data exchange system in this embodiment, ping-pong transmission (time division transmission) is used, and data is transmitted in a synchronous manner.

This system, as shown in FIG. 1, is an exchange (11).
And DTE (13) and DIE (15). DTE (13) and DIE (1
5) is connected to the transmission data signal line T, the clock signal line S, the control signal line C, the reception data signal line R, and the like. DIE
A transmission line is provided between (15) and the exchange (11).

Data is transmitted on this transmission line by the above-mentioned ping-pong transmission (see, for example, Proceedings 1712 of the National Conference of the Institute of Electronics and Communication Engineers, 1982). In ping-pong transmission, data is intermittently generated to form a burst signal, which is transmitted at intervals of time between the DIE (15) and the exchange (11). Also called time division directional control transmission. In the present invention, first, the exchange (11) synchronously sends a burst signal to the two DIEs (15) to which data transmission is desired. The burst signal at this time does not include data, but does include a frame synchronization bit "0" for setting the clock cycle with two DIEs (15). The two DIEs (15) that have received this burst signal respectively output clocks according to the frame synchronization bit "0" (this clock is DI
The first clock supplied from E (15) to DTE (13) and D
There are two types of second clocks that are generated only inside the IE (15)). Next, in the two DIEs (15), the data sent from the DTE (13) is sampled and put on the burst signal (when there is no data to be put, the burst signal remains "0"). , The frame synchronization bit is changed to “1” and sent back to the exchange (11). Switch (1
In 1), when the burst signals are received from both DIEs (15), each of them is sent as it is to the other party's DIEs (15) in synchronization. When each DIE (15) receives the burst signal from the exchange (11), the data is taken into the DTE (13) and the DTE (13) is received.
If there is new data from (13), it is added and the burst signal is sent again to the exchange (11). Thereafter, transmission and reception of burst signals are repeated between the two DIEs (15) via the exchange (11) (ping-pong transmission). Here, the first clock is D
The second clock is used to specify the transmission / reception of data at the TE (13), and the second clock to specify the data sampling / reception at the DIE (15) and the exchange (11). used. In addition, the exchange (11) has both DIE (1
When the burst signal received from 5) reaches a predetermined number of times, the frame synchronization bit of the burst signal is changed from "1" to "0" and transmitted to the other party's DIE (15). Upon receiving this burst signal, the DIE (15) outputs the first clock and the second clock again in synchronization with each other according to the frame synchronization bit "0". For example, if the transmission speed of the DTE (13) is 9.6 kbps and the transmission speed of the exchange (11) is 48 kbps, when the exchange (11) receives the burst signal from both DIEs (15) for the fifth time, the frame synchronization bit Is changed from "1" to "0". Therefore, in the DIE (15), the first clock and the second clock are synchronized every time the burst signal is received five times.

Next, the operation of each component will be described in detail.

First, the clock signal line S from the DIE (15) to the DTE (13)
The clock is supplied via. In synchronization with this clock, data is transmitted from the DTE (13) via the transmission data signal line T. This data is sent at a transmission rate of 48 kps.

In the DIE (15), this data is sampled, then collected as a burst signal for every fixed number of bits and sent out on the transmission path. The burst signal, as shown in FIG.
It consists of a 10-bit signal. The first bit is a frame synchronization bit F, the last bit is a control bit S for transmitting and receiving various control information, and 8 bits between them are data.

In normal data transmission, various devices are designed on the basis of voice transmission. That is, the transmission speed required for voice transmission is 64 kbps, and it is assumed that 8-bit data is transmitted at a frequency of 8 KHz, and even if it is 8 KHz on the transmission line (subscriber line) of the system in this embodiment. Data is transmitted at the frequency, that is, every 125 μsec.

Since the transmission speed of DTE (13) is 48 kbps, the data is transmitted in the format shown in Fig. 2 as D ₆ and D ₇ as insignificant bits and the other bits as significant bits. To be done. That is, D ₇ = 1 and D ₆
= 0, 6-bit data is transmitted every 125 μsec.
Data of such a format is transmitted on the transmission data signal line T
(If D ₇ = 0, this burst signal is meaningless as data.) This data has the control bit S as described above. Only, the control information from the DTE (13) (or from the exchange (11)) is transmitted as control bits S bit by bit. If the number of control bits sent reaches a certain number, it will be the first and only one instruction. This command is decoded in the DIE (15) and supplied to the DTE (13) via the control signal line C.

Further, since the DTE (13) in this embodiment is of the synchronous type, the clock is supplied from the DIE (13) via the clock signal line S. According to the present invention, a plurality of DTEs (13) for transmitting data to each other
One of the features of the clocks supplied to is that they are in phase synchronization with each other.

In the system having such a configuration, from the exchange (11),
At the same time, a signal for instructing the generation of a clock is supplied to the DIEs (15) that exchange data. This signal has a structure in which the data D _{0 to} D ₇ are “0” and the frame synchronization bit is “0” in the burst signal shown in FIG. The DIE (15) outputs a detection signal for synchronizing the first clock and the second clock only when the frame synchronization bit of the received burst signal is "0". DIE
In (15), two types of clocks are generated according to this signal. One is the first clock signal that defines the timing of data transmission / reception in DTE (15), and the other is DIE (15).
This is a second clock signal that defines the internal data sampling cycle. These clock signals are all DI
Phase synchronization is achieved at E (15). The frequency of the first clock signal differs depending on the corresponding DTE (13).
(This will be described later.) The frequency of the second clock signal is required to be equal to or higher than the frequency of the first clock signal. That is, in synchronization with the first clock signal
For the data supplied to the DIE (15), one-point sampling (when the frequencies of the first and second clock signals are the same) or multi-point sampling (the frequency of the second clock signal is the first frequency) Higher (if higher). This data is sent to the subscriber line SUB.

This data is exchanged in the exchange (11). The designated signal of the other party is transmitted to the corresponding DIE (15). This signal is provided with a predetermined delay amount so as to be synchronized with the first clock signal, and is supplied to the DTE (13).
Thereby, data transmission can be performed between DTEs (15) that mutually transmit.

Here, it is assumed that the first clock signals are phase-synchronized with each other, the frequency of these signals is variable, and is adjusted according to the DTE (13). The second clock signal is constantly constant, and data transmission between DIEs (15) is constant regardless of DTE (13).

By doing so, data is transmitted between the DTEs (15) in the same transmission form regardless of what the DTEs (13) are. That is, signals are transmitted in the same data format, and only the first clock signal needs to be changed. Of course, no change is necessary in the circuit configuration inside the DIE (15).

Next, the configuration of the DIE (15) will be described. The DIE (15) in this embodiment, as shown in FIG.
Includes V (21). The transceiver circuit TRCV (21) converts the signal from the subscriber line SUB into a signal form handled inside the DIE (15). Conversely D
Converts data from TE (13) into a signal suitable for transmission on subscriber line SUB.

The output of the transceiver circuit TRCV (21) is the sync signal detection circuit SYNDET.
(23), the first clock frequency dividing circuit CLKDIV1 (25) is supplied to the second clock frequency dividing circuit CLKDIVII (27), the selection circuit SEL (29), and the control circuit CTRL (31). Sync signal detection circuit SYNDE
At T (23), a detection signal is output only when the frame synchronization bit "0" is detected in the reception output of the transmission / reception circuit TRCV (21). The detection signal from the synchronization signal detection circuit SYNDET (23) is the first and second clock frequency divider circuits CLKDIVI, II (2
5), (27) is supplied. First clock divider CLKDIVI
The first clock signal from (25) is supplied to the clock signal line S described above. Also, this first clock divider circuit CL
A control signal is supplied to the KDIVI (25) from the selection circuit (29). This control signal is output when the DTE (13) is asynchronous, and the output from the first frequency dividing circuit CLKDIVI (25) is prohibited.

The second clock signal output from the second clock divider circuit (27) is supplied to the sampling circuit SAMP (33), the first and second registers REGI, II (35) and (37), and the transceiver circuit TRCV (21 ). A data signal is supplied to the sampling circuit SAMP (33) via the transmission data signal line T. The output of the sampling circuit (33) is once written in the first register (35) and sent to the transmission / reception circuit TRCV (21) every predetermined number of bits.

On the other hand, the second register REGII (37) has a transmitting / receiving circuit TRCV.
The output of (21) is also supplied. The output of the register REGII (37) is input to the delay circuit DLYREG (39). Delay circuit DLYREG (3
The output of 9) is supplied to the reception data signal line R.

Next, the form of the signal on the subscriber line SUB will be described. In this embodiment, the signal of logic level is subjected to die-phase coding. What is diphase encoding? 2
This is a method of expressing the value signal by the level change and width of the digital waveform, which is used in the transmission of subscriber lines. In the diphase code, as shown in FIG. 4, it is required that a level change always occurs at the break of the time lock when transmitting a significant signal. The binary "0" is represented by a waveform that causes a level change in the middle of the timeslot. For example, "0" is represented by changing from a positive value to a negative value (absolute values are the same for simplification). In contrast, a binary "1" is represented by holding the same level across time slots. Furthermore, zero shall be maintained when no significant signal is transmitted. Fourth
The upper part of the figure shows the waveform when signal transmission is started halfway. In this example, the signal "01011100101" is transmitted.

As mentioned above, the signal on the subscriber line SUB forms the format as shown in FIG. 2, but the first bit, the frame sync bit F, is as shown in FIG. 5 (a). As a general rule, it is represented by "1". Therefore, it is detected that the data transmission is started if there is a level change to positive or negative after the zero level. DIE as described above (15)
, The signal for instructing the generation of the clock signal is supplied to the frame synchronizing bit F in this embodiment.
Plays this function by. In other words, DIE (15)
Then, each time the frame synchronization bit "0" is received, the first clock and the second clock are synchronized and output.

For example, the transmission speed of DTE (13) is 9.6 kbps, and the exchange (1
If the transmission rate of 1) is 48 kbps, DTE (13) and DIE
While the clock is output once between (15), the clock is output five times between the DIE (15) and the exchange (11). Therefore, in order to match these synchronizations, assuming that the normal frame synchronization bit (used to indicate the start of data) of the burst signal is "1", the frame synchronization bit F of one burst signal among the five burst signals. Is represented by "0" as shown in FIG. 5 (b). With the diphase code, the start of data transmission is detected even if it is "0". As described above, the exchange (11) sends the burst signal including the frame synchronization bit “0” as the initial setting to both DIs.
Send to E (15) at the same time. These two DIEs (15) output in synchronization with the first clock and the second clock according to the frame synchronization bit "0" of the received burst signal. The DTE (13) transmits data to the DIE (15) at the first clock timing. Second in DIE (15)
The data is sampled at the clock timing of. Then, in the transmission / reception circuit (21) in the DIE (15), the burst signal in which these sampling data are put and the frame synchronization bit "0" is changed to "1" is sent to the exchange (11) at the timing of the second clock. Send out. In this manner, when the exchange 11 receives the burst signals from both the DIEs 15, the respective ones are simultaneously transmitted to the other (the opposite side) DIEs 15 as they are. This operation is repeated, but the exchange
In (11), when the burst signal is received from both DIEs (15) for the fifth time, the frame synchronization bit is changed to "0" and simultaneously transmitted to the counterpart DIEs (15). Therefore DIE (1
In 5), the first clock and the second clock are synchronized every time the burst signal is received five times.

The processing of each unit in the DIE (15) for this frame synchronization bit will be described. First, it is assumed that the 1st to 4th burst signals (the frame synchronization bit is "1") are received by the DIE (15).

Such a signal is converted into a logic level signal by the transmission / reception circuit (21). The frame sync bit F, which is the first bit of the converted signal (40), is "1" and is detected by the sync signal detection circuit SYNDET (23). However, at this time, the synchronization signal detection circuit SYNDET (23) does not output a signal. Next, it is assumed that the fifth burst signal (the frame synchronization bit is "0") is received by DIE (15). Every time this is detected by the sync detection circuit (23), that is, 125 × 5 μsec
The detection signal (41) is output every time, and the second clock divider circuit CL is output.
Supply to KDIVII (27) and control circuit CTRL (31). The second clock frequency dividing circuit CLKDIVII (27) outputs the second clock signal whose synchronization T is a pulse of 125 μsec. This second
The clock signal of is used for sampling and the like. The control circuit CTRL (31) detects the control bit S based on the detection signal (41), collects a predetermined number of bits as described above, and outputs the control signal to the control signal line C.

Further, the frame sync bit F modified as described above is detected by the sync signal detection circuit SYNDET (23) every 125 × 5 (μsec), and the detection signal (43) is sent to the first frequency dividing circuit (25). Supplied. The first frequency divider circuit (25) outputs a first clock signal in response to this detection signal. The frequency of the first clock signal is one fifth of the frequency of the second clock signal.
Has become. Naturally, the cycle T is 5 times. The first clock signal is introduced into the DTE (13) via the clock signal line S. The DTE (13) sends and receives a data signal in synchronization with the first clock signal. Thus, the first clock divider circuit outputs the first clock that defines the timing when the data terminal transmits / receives the data, and the second clock divider circuit outputs the transmission data in the data terminal interface device. It outputs a second clock that defines the timing of sampling and the timing of data transmission / reception with the exchange. The first clock frequency dividing circuit and the second clock frequency dividing circuit are synchronized each time the frame synchronization bit "0" is detected from the received burst signal. Therefore, in the above example, every time the burst signal is received five times, the first clock and the second clock are synchronized and output.

In this embodiment, the frequency of the first clock signal having the waveform as shown in FIG. 6 (a) is 9.6 KHz. At the rising timing of this first clock signal,
Data is transmitted from DTE (13). This data signal line T
And is supplied to the sampling circuit SAMP (33) via. The sampling circuit SAMP (33) is supplied with the second clock signal as shown in FIG. 6 (c). This second clock signal is a clock used for sampling, and data is sampled at the rising edge of this signal.
The waveform is shown in (d).

In the sampled data, the second clock signal (shown in FIG. 6 (c)) serves as the operation clock. The first register REGI (35) collects 6 bits at a time. This signal is converted into the format shown in FIG. 2 in the transmission / reception circuit TRCV (21) and transmitted to the subscriber line SUB. Further, this data is exchange-processed in the exchange (11).
It should be noted that in the exchange (11) using the time division method, the exchange process inevitably causes a delay time.
The data signal accompanied by this delay time is supplied to the DIE (15) corresponding to the DTE (13) of the other party.

First, it is supplied to the transmission / reception circuit TRCV (21) via the subscriber line SUB. Here, the conversion to the logical level is as described above. This signal is supplied to the second register REGII (37). In the second register REGII (37), see FIG. 6 (f).
The second clock signal (shown in FIG. 6 (c), which is the same as the signal shown in FIG. 6 (c) and is phase-synchronized) is used as the operation clock, and bits other than data are removed and at the same time delayed by one bit. Send to circuit DLYREG (39).

The delay circuit DLYREG (39) delays the data transmission by the time T _L as shown in FIGS. 6 (g) and 6 (h). This delay time T _L
Is defined by counting the number of clocks of the second clock signal from the second divider circuit CLKDIVII (27).
As a result, the output of the delay circuit DLYREG (39) is
In synchronization with the first clock signal shown in (e), the DTE (13)
Is supplied to. The first clock signal is the same DTE (15)
In addition to being phase-synchronized with the second clock signal in (1), it is also phase-synchronized with the first and second clock signals in the mutually transmitting DIEs (15). Delay circuit DLYREG
Since the delay time T _L in (39) is determined with reference to the second clock signal, data transmission in two DTEs (13) is
It will be perfectly synchronized.

[Other Embodiments of the Invention]

Next, a case where the transmission speed of DTE (13) is 4800 bps will be described. The structure of the DIE (15) is almost the same as the above-mentioned embodiment.
The difference lies in the frame sync bit. In this embodiment, of the 10 burst signals, a predetermined burst signal carries the start information of the first clock signal. That is, data is transmitted by a diphase code, a normal frame synchronization bit F is represented by "1", and a frame synchronization bit F of a specific burst signal is represented by "0". As a result, the frequency of the first clock signal from the first frequency dividing circuit (25) becomes 1/2 of that of the above-described embodiment (the transmission speed is 9600 bps, which is twice that of this embodiment). 7 (a) shows the calling side DTE (13), and FIG. 7 (c) shows the called side DTE.
The first clock signal supplied to (13) is shown. When the former transfers data to DIE (15), the latter transfers data to DIE (15)
It is a synchronizing signal when supplied from. The delay time generated inside the exchange (11) is the same as that in the above-mentioned embodiment. Delay circuit
The delay time T _L at (39) is also the same as in the above-mentioned embodiment. The delay time T _L is selected to be synchronous with the first clock signal. Furthermore, the DTE (13) that is normally used is selected based on the one with the lowest transmission rate. If the transmission speed of the DTE (13) is slow, the cycle of the first clock signal becomes long. For this cycle, the delay time inside the exchange (11) does not depend on the DTE (13). Then, the first clock signal changes with respect to the delay time inside the exchange (11). However, usually DTE (1
The transmission speed of 3) is set to a common divisor of 48 kbps. Therefore, even if the DTEs (13) having different transmission rates are connected, the delay time in the delay circuit DLYREG (39) can be commonly selected. Of course, the delay time may be changed by each DIE (15).

The same applies to the activation information of the first clock signal carried in the burst signal. For example, this information may be determined based on the DTE (13) having the lowest transmission rate in the system. For example, when 4800 bps is the lowest transmission rate, one burst signal out of 10 burst signals for all DTE (13) carries the activation information of the first clock signal. However, the transmission speed of the corresponding DTE (13) may be transmitted from the selection circuit SEL (29) to the first clock frequency dividing circuit CKL-DIV I (25). At this time, the selection circuit SEL (29) may be linked with the switch of the DTE (13) or the like, or the transmission speed may be set by the operator.

A case where the DTE (13) is asynchronous will be described. At this time, the fact that the DTE (13) is asynchronous is transmitted to the selection circuit SEL (29) by the switch of the DIE (15) or the like. The selection circuit SEL (29) commands the first clock frequency dividing circuit (25) to stop the output of the first clock signal. This is because the asynchronous terminal does not need a clock signal. This is the case where (a) and (e) are not present in FIGS. 6 and 7.

Further, in the above embodiments, the diphase coding is used as the coding, but it goes without saying that bipolar or the like may be used.

Thus, it goes without saying that the present invention includes any modifications without departing from the spirit of the present invention.

[Brief description of drawings]

FIG. 1 is a diagram showing a system configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a burst signal in the system of FIG. 1, and FIG. 3 is a configuration of DIE (15). FIG. 4 is a diagram showing a waveform of a signal on a subscriber line, FIG. 5 is a diagram showing a frame synchronization bit which is a leading bit of the burst signal shown in FIG. 2, and FIG. And Figure 7
It is a figure which shows the various signals inside the DIE shown in FIG. 11 ... Exchanger, 13 ... Data terminal, 15 ... Data terminal interface device, 21 ... Transceiver circuit, 39 ... Delay circuit.

Claims (1)

[Claims] 1. An exchange, a plurality of data terminal interface devices respectively connected to the exchange by subscriber lines, and a plurality of data terminals respectively connected to these data terminal interface devices for transmitting and receiving data. In the data exchange system for performing synchronous data transmission between the two data terminals via the exchange, the exchange is configured to transmit the first data transmitted from the two data terminal interface devices performing the synchronous data transmission. Receiving a signal with a frame synchronization bit and transmitting them simultaneously to the data terminal interface device of the other party, and changing the first frame synchronization bit to the second frame synchronization bit every predetermined number of signal receptions. The data terminal interface device samples the data transmitted from the data terminal. A sampling circuit for ringing, a transmission / reception circuit that collects data from the sampling circuit for every predetermined number and transmits to the exchange as a signal with a first frame synchronization bit, or receives a signal transmitted from the exchange, A synchronization signal detection circuit that outputs a detection signal each time the second frame synchronization bit is detected in a reception signal from the transmission / reception circuit, and the data terminal in response to the detection signal output from the synchronization signal detection circuit. A first clock frequency dividing circuit that outputs a first clock signal that defines data transmission and reception in the above-mentioned case, and sampling in the sampling circuit in response to the detection signal output from the synchronization signal detection circuit and the A second clock divider circuit that outputs a second clock signal that defines transmission and reception of a signal to and from the exchange; By counting the second clock signal output from the lock frequency divider circuit, the received data from the transmitter / receiver circuit is counted by the first clock signal.
And a delay circuit that outputs the data to the data terminal after delaying the same for a predetermined time so as to be synchronized with the clock signal.