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JPS6355860B2 - - Google Patents

Info

Publication number
JPS6355860B2
JPS6355860B2 JP58048217A JP4821783A JPS6355860B2 JP S6355860 B2 JPS6355860 B2 JP S6355860B2 JP 58048217 A JP58048217 A JP 58048217A JP 4821783 A JP4821783 A JP 4821783A JP S6355860 B2 JPS6355860 B2 JP S6355860B2
Authority
JP
Japan
Prior art keywords
sealed chamber
carrier
processing
wafer
semiconductor substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58048217A
Other languages
Japanese (ja)
Other versions
JPS59175122A (en
Inventor
Hidemi Amai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4821783A priority Critical patent/JPS59175122A/en
Publication of JPS59175122A publication Critical patent/JPS59175122A/en
Publication of JPS6355860B2 publication Critical patent/JPS6355860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Coating Apparatus (AREA)

Description

【発明の詳細な説明】 本発明は半導体基板塗布前処理装置にかかり、
特に半導体素子製造工程におけるフオトリソグラ
フイ工程の半導体基板塗布前処理装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate coating pretreatment apparatus,
In particular, the present invention relates to a semiconductor substrate coating pretreatment apparatus for a photolithography process in a semiconductor device manufacturing process.

半導体基板塗布前処理とは、その後処理工程で
ある目合せ露光工程、現像処理工程及びエツチン
グ処理工程等において半導体素子の微細なパター
ンを形成する上で重要な要因となる感光材(以下
フオトレジストと呼ぶ)と半導体基板(以下ウエ
ハと呼ぶ)の密着性を向上させる為のものであ
る。
Semiconductor substrate coating pretreatment refers to the use of photosensitive materials (hereinafter referred to as photoresists), which are important factors in forming fine patterns on semiconductor elements in subsequent processing steps such as alignment exposure, development, and etching. This is to improve the adhesion between a semiconductor substrate (hereinafter referred to as a wafer) and a semiconductor substrate (hereinafter referred to as a wafer).

ウエハとフオトレジストの密着性が低いとフオ
トレジストの剥れの発生及びエツチング量の不安
定等の半導体素子の微細なパターンを形成する上
で大きな支障を来たす為、良好な半導体基板塗布
前処理を行う必要がある。
If the adhesion between the wafer and the photoresist is poor, it will cause major problems in forming fine patterns for semiconductor devices, such as peeling of the photoresist and instability of the etching amount, so good pre-treatment for semiconductor substrate coating is required. There is a need to do.

半導体基板塗布前処理の方法として大別し、ウ
エハ表面に処理薬液を適下し、該ウエハを回転し
塗布するスピンコート法、及び処理薬液又は処理
薬液によるベーパーガスをウエハ表面にスプレー
しウエハ表面に付着させるスプレーコート法、及
び処理薬液によるベーパーガスの雰囲気中にウエ
ハを設置し処理薬液を付着させるベーパーガス処
理法等がある。
The pre-treatment methods for semiconductor substrate coating are roughly divided into spin coating methods, in which a processing chemical is dropped onto the wafer surface and the wafer is rotated to coat the wafer, and spin coating, in which a processing chemical or vapor gas from the processing chemical is sprayed onto the wafer surface. There is a spray coating method in which the wafer is deposited on the wafer, and a vapor gas treatment method in which the wafer is placed in an atmosphere of vapor gas caused by a processing chemical and the processing chemical is deposited on the wafer.

前記、各処理方法においてスピンコート法は処
理薬液の使用量が多く、又、塗布膜厚の“むら”
“ばらつぎ”等が発生しやすく、良好な処理状態
も望めない。
Among the above-mentioned processing methods, the spin coating method uses a large amount of processing chemicals, and also causes "unevenness" in the coating film thickness.
"Uneven splicing" etc. are likely to occur, and good processing conditions cannot be expected.

スプレーコート法においても前記同様の問題が
有り、ベーパーガス処理法が用いられる場合が多
い。
The spray coating method also has the same problem as described above, and a vapor gas treatment method is often used.

ベーパーガス処理法は処理薬液の使用量も比較
的小さく処理状態も良好なものが得られる。
The vapor gas treatment method requires a relatively small amount of processing chemicals and provides good processing conditions.

しかし、ベーパーガス処理法では処理薬品雰囲
気中にウエハを設置する処理時間が比較的長くか
かる為、複数枚のウエハを同時に処理するバツチ
処理法が通常用いられる。
However, since the vapor gas processing method requires a relatively long processing time in which the wafers are placed in a processing chemical atmosphere, a batch processing method is usually used in which a plurality of wafers are processed at the same time.

尚、通常バツチ処理では規定数のキヤリア単位
で行われ、処理用キヤリアへウエハを入れ換え、
そのキヤリアごと処理薬品雰囲気中に設置し処理
を実行し、再びそのキヤリアごと処理薬品雰囲気
中より取り出し処理用キヤリアより入れ換えが行
われる。
Normally, batch processing is performed in units of a specified number of carriers, and wafers are transferred to processing carriers,
The carrier is placed in a processing chemical atmosphere to perform processing, and the carrier is again taken out from the processing chemical atmosphere and replaced with a processing carrier.

前記の様にウエハ入れ換え作業が多く、又、処
理薬品雰囲気中へ直接キヤリアを出し入れする
為、塵埃の発生及び処理雰囲気中への混入、又、
キヤリアを出し入れできる程度に処理薬品の密閉
雰囲気を開放する為、処理薬品雰囲気の状態を乱
す等の支障がある。さらに、現在、各処理行程で
進行している自動化、省力化、キヤリアtoキヤリ
アによる連続処理及び他のフオトリソグラフイ工
程の処理装置との接続(In−Line化)が困難であ
り、作業の発展性に支障を来たすものである。
As mentioned above, there is a lot of wafer exchange work, and since the carrier is directly taken in and out of the processing chemical atmosphere, dust is generated and mixed into the processing atmosphere.
Since the sealed atmosphere of the processing chemicals is opened to the extent that the carrier can be taken in and taken out, there are problems such as disturbing the state of the processing chemical atmosphere. Furthermore, automation, labor saving, carrier-to-carrier continuous processing, and connection (in-line) with processing equipment for other photolithography processes, which are currently underway in each processing process, are difficult, and work progress is difficult. It interferes with sexuality.

本発明はベーパーガス処理方法による良好な処
理状態を保ち、前記した種々の問題を解消し作業
の発展性に豊んだ半導体基板塗布前処理装置を提
供するものである。
The present invention provides a semiconductor substrate coating pretreatment apparatus that maintains a good treatment state by a vapor gas treatment method, solves the various problems described above, and has a rich work expandability.

本発明の特徴は、塗布前処理薬品雰囲気を発生
する手段を具備した密閉室と、該密閉室内に設け
られ、昇降機能を有しかつ多数の半導体基板を水
平に所定間隔あけて積み重ねる態様をもつて収容
する専用キヤリアと、該密閉室の一方の側に設け
られた供給エレベータと、該密閉室の他方の側に
設けられた収納エレベータと、該密閉室の側壁に
それぞれ設けられた密閉室入口および出口機構
と、該供給エレベータ上に搭載された半導体基板
を多数収納したキヤリアより該半導体基板を該密
閉室入口機構を通して該専用キヤリアへ順次自動
搬送する手段と、該専用キヤリアに収容されてい
る半導体基板を該密閉室出口機構を通して該収納
エレベータ上に搭載されたキヤリアへ順次自動搬
送する手段とを有する半導体基板塗布前処理装置
にある。このような本発明によれば処理薬品の雰
囲気の状態を乱すことはなくなる。又、密閉室が
コンパクトとなるからレイアウト上の制約がなく
なりかつ使用する薬品が少なくてすむこととな
る。さらに専用キヤリアは昇降機能を有している
から供給もしくは収納エレベータの上下運動と逆
方向の下上運動を行なうことにより半導体基板の
供給もしくは収納作業が短かい時間で行なわれる
こととなる。
The present invention is characterized by having a sealed chamber equipped with a means for generating a chemical atmosphere for pre-coating treatment, and a mode in which a large number of semiconductor substrates are horizontally stacked at predetermined intervals, and is provided within the sealed chamber, and has an elevating function. A supply elevator provided on one side of the sealed room, a storage elevator provided on the other side of the sealed room, and a sealed room entrance provided on the side wall of the sealed room, respectively. and an exit mechanism, means for automatically transporting the semiconductor substrates from a carrier loaded on the supply elevator and containing a large number of semiconductor substrates to the dedicated carrier through the closed chamber entrance mechanism, and the semiconductor substrates are accommodated in the dedicated carrier. The present invention provides a semiconductor substrate coating pre-processing apparatus having means for automatically sequentially transporting semiconductor substrates through the closed chamber exit mechanism to a carrier mounted on the storage elevator. According to the present invention, the atmosphere of the processing chemicals is not disturbed. Furthermore, since the sealed chamber becomes compact, there are no restrictions on the layout and less chemicals can be used. Further, since the dedicated carrier has an elevating function, the semiconductor substrate supplying or storing operation can be carried out in a short time by performing a downward movement in the opposite direction to the vertical movement of the supplying or storing elevator.

尚、塗布前処理薬品雰囲気を発生する手段を密
閉室内に設ける場合、又は密閉室外に設け発生し
たベーパーガスを配管により密閉室内に導く場
合、又、密閉室内の専用キヤリアへのウエハの搬
送及び送出を一つの手段で兼ねた場合のものも、
本発明の範囲に含まれるものである。
In addition, when a means for generating a pre-coating treatment chemical atmosphere is provided in a sealed chamber, or when it is installed outside the sealed chamber and the generated vapor gas is guided into the sealed chamber via piping, the wafer is transported and sent to a dedicated carrier inside the sealed chamber. In the case where both are used as one means,
It is within the scope of the present invention.

第1図は本発明の一実施例を示す概略側面図で
あり、供給エレベータ1にセツトされたウエハを
収納したキヤリア2よりウエハ搬送機構3により
搬送されたウエハは密閉室4の内部に収納された
昇降機能を有する専用キヤリア5へ開閉機能を有
する密閉室入口シヤツター6を通過し収納され
る。
FIG. 1 is a schematic side view showing one embodiment of the present invention, in which wafers are transported by a wafer transport mechanism 3 from a carrier 2 which stores wafers set in a supply elevator 1, and are stored inside a sealed chamber 4. The container is stored in a dedicated carrier 5 which has an elevating function and passes through a closed room entrance shutter 6 which has an opening/closing function.

専用キヤリア5へ収納されたウエハ7はバブリ
ング配管等のベーパーガス発生促進機能を有する
塗布前処理液槽8より発生したベーパーガスの雰
囲気に一定時間設置される。
The wafer 7 housed in the dedicated carrier 5 is placed in an atmosphere of vapor gas generated from a coating pretreatment liquid tank 8 having a function of promoting vapor gas generation, such as bubbling piping, for a certain period of time.

その後、専用キヤリア5よりウエハ送出機構9
により処理されたウエハ7を開閉機能を有する密
閉室出口シヤツター10を通過し収納エレベータ
11にセツトされたウエハを収納するキヤリア1
2へ送出するものである。
After that, the wafer delivery mechanism 9 is transferred from the dedicated carrier 5.
A carrier 1 stores the processed wafers 7 which pass through a closed chamber exit shutter 10 having an opening/closing function and are set in a storage elevator 11.
2.

以上、述べた様に本発明はウエハに対する処理
はベーパーガス処理方法であり良好な処理状態を
保ち、尚かつ、ウエハ毎の搬送、送出手段を用い
る為、ウエハの入れ換え等により発生する問題を
解消し、他のフオトリソグラフイ工程の処理装置
との接続が容易である事は言うまでもない。
As described above, the present invention uses a vapor gas treatment method to process wafers, which maintains good processing conditions, and also eliminates problems that may occur due to wafer replacement, etc., as it uses transport and delivery means for each wafer. However, it goes without saying that it is easy to connect to processing equipment for other photolithography processes.

以上、本発明により良好な処理状態を保ち、作
業の発展性に豊んだ半導体基板塗布前処理装置が
提供される事は明らかである。
As described above, it is clear that the present invention provides a semiconductor substrate coating pretreatment apparatus that maintains a good processing state and has a wide range of operability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す概略側面図で
ある。 尚、図において、1……供給エレベータ、2…
…供給キヤリア、3……ウエハ搬送機構、4……
密閉室、5……専用キヤリア、6……入口シヤツ
ター、7……ウエハ、8……塗布前処理液槽、9
……ウエハ送出機構、10……出口シヤツター、
11……収納エレベータ、12……収納キヤリア
である。
FIG. 1 is a schematic side view showing one embodiment of the present invention. In the figure, 1... supply elevator, 2...
...Supply carrier, 3...Wafer transport mechanism, 4...
Sealed chamber, 5... Dedicated carrier, 6... Inlet shutter, 7... Wafer, 8... Pre-coating treatment liquid tank, 9
...Wafer delivery mechanism, 10...Exit shutter,
11...Storage elevator, 12...Storage carrier.

Claims (1)

【特許請求の範囲】[Claims] 1 塗布前処理薬品雰囲気を発生する手段を具備
した密閉室と、該密閉室内に設けられ、昇降機能
を有しかつ多数の半導体基板を水平に所定間隔あ
けて積み重ねる態様をもつて収容する専用キヤリ
アと、該密閉室の一方の側に設けられた供給エレ
ベータと、該密閉室の他方の側に設けられた収納
エレベータと、該密閉室の側壁にそれぞれ設けら
れた密閉室入口および出口機構と、該供給エレベ
ータ上に搭載された半導体基板を多数収納したキ
ヤリアより該半導体基板を該密閉室入口機構を通
して該専用キヤリアへ順次自動搬送する手段と、
該専用キヤリアに収容されている半導体基板を該
密閉室出口機構を通して該収納エレベータ上に搭
載されたキヤリアへ順次自動搬送する手段とを有
することを特徴とする半導体基板塗布前処理装
置。
1. A sealed chamber equipped with means for generating a pre-coating treatment chemical atmosphere, and a dedicated carrier provided within the sealed chamber, which has a lifting function and accommodates a large number of semiconductor substrates in a manner that allows them to be stacked horizontally at predetermined intervals. a supply elevator provided on one side of the sealed chamber; a storage elevator provided on the other side of the sealed chamber; and a sealed chamber entrance and exit mechanism provided on a side wall of the sealed chamber, respectively; means for sequentially automatically transporting the semiconductor substrates from a carrier containing a large number of semiconductor substrates mounted on the supply elevator to the dedicated carrier through the closed chamber entrance mechanism;
A semiconductor substrate coating pre-processing apparatus comprising means for automatically transporting semiconductor substrates housed in the dedicated carrier sequentially through the closed chamber exit mechanism to the carrier mounted on the storage elevator.
JP4821783A 1983-03-23 1983-03-23 Before-coating processing device for semiconductor wafer Granted JPS59175122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4821783A JPS59175122A (en) 1983-03-23 1983-03-23 Before-coating processing device for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4821783A JPS59175122A (en) 1983-03-23 1983-03-23 Before-coating processing device for semiconductor wafer

Publications (2)

Publication Number Publication Date
JPS59175122A JPS59175122A (en) 1984-10-03
JPS6355860B2 true JPS6355860B2 (en) 1988-11-04

Family

ID=12797241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4821783A Granted JPS59175122A (en) 1983-03-23 1983-03-23 Before-coating processing device for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS59175122A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364031U (en) * 1986-10-16 1988-04-27
JPS63199423A (en) * 1987-02-16 1988-08-17 Toshiba Corp Surface treating method for semiconductor substrate
JP5287913B2 (en) * 2011-03-18 2013-09-11 東京エレクトロン株式会社 Coating, developing device, coating, developing method and storage medium

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52142972A (en) * 1976-05-25 1977-11-29 Toshiba Corp Semiconductor production device
JPS5731151A (en) * 1980-08-04 1982-02-19 Toshiba Corp Automatic continuous treating device for semiconductor substrate
JPS5753933A (en) * 1980-09-18 1982-03-31 Toshiba Corp Manufacture of semiconductor element

Also Published As

Publication number Publication date
JPS59175122A (en) 1984-10-03

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