JPS6353797A - Memory circuit - Google Patents

Abstract

PURPOSE:To attain access to a memory as data suitable for data compression by providing a means to convert the bit arrangement of a data to be accessed to a memory array in matrix state. CONSTITUTION:When an A/B terminal input 104 is '0', if a rotating input 106 from terminals S1 and S0 is '00', outputs A0, A1, A2, and A3 correspond respectively to inputs B0, B1, B2, and B3. If the rotating input 106 is '01', outputs A1, A2, A3, and A0 correspond respectively to inputs B0, B1, B2, and B3. In such a manner, the outputs are rotated by one bit to the right. If the rotating input 106 is '10', said rotation goes to be by two bits to the right and the outputs A2, A3, A0, and A1 respectively correspond to the same inputs as the above, and further, if the input 106 is '11', the outputs goes to be A3, A0, A1, and A2. Since the conversion of bit arrangement of an access data is available corresponding to dither matrix, etc., the efficiency of data compression, etc., can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and more particularly to a memory circuit that stores image information in a matrix, for example, for a display or a printer.

[Prior Art] Conventionally, the image memory of displays and printers has been designed with top priority given to reading speed. For example, since the memory space is set in correspondence with the CPU bus, it is difficult to access data on the memory. Moreover, memory operations such as block movement, rotation, and scrolling in memory space are complicated. Furthermore, density patterns such as dither patterns used in image processing and the like are determined with emphasis on image reproducibility, and therefore cannot be passed through compression processing of image information in memory space.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned conventional example, and it is an object of the present invention to provide a memory circuit that can access a memory as data suitable for data compression, for example, by rearranging bits. With the goal.

[Means for Solving the Problems] In order to achieve the above object, the memory circuit of the present invention has the following configuration. That is, a memory array having a small number of memory elements arranged in an n×m matrix, a first address means for outputting an address corresponding to the position of the memory element in the row direction, and a first address means for outputting an address corresponding to the position of the memory element in the column direction. a second address means for outputting an address corresponding to a position, an input/output means for accessing the memory array addressed by the first and second address means, and a bit arrangement of access data of the memory array. and bit position changing means for rearranging the bit positions.

[Operation] The above configuration operates by converting the bit array of access data to the memory array so that the bit string of 1 or 0 becomes longer.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of the structure of image memory (FIG. 1)] FIG. 1 is a diagram showing the structure of the image memory 1 of this embodiment.

The storage section of the image memory 1 includes a memory array 110 having 4×4 memories 102 (256×256×1 pit) shown in FIG. The X-address output section 3 outputs a direction address. The X address output unit 2 inputs the address Ax in the X direction from the cPU, and the X address output unit 3 inputs Ay, respectively, and outputs 8 bits of AX 6 - AX s + A'/o~Ay.
3 address signal is output.

Reference numeral 4 denotes a data conversion unit, which allows the bit arrangement of the data bus when accessing the memory array 110 to be output as is or after being changed. 5 is the mask section and memory element 1 is specified by the bit of the data bus.
Writing to 02 is prohibited. 6 is a video output unit that reads bit data from the memory array 110 in the horizontal or vertical direction and outputs it as a video signal 716. Note that the VAS signal input to the video output unit 6 is a signal synchronized with a video signal such as a video clock, and is a clock signal provided from an external device such as a display unit (not shown).

[Explanation of connection with CPU (Figure 2)] Figure 2 shows the CPU
7 and the image memory 1. FIG.

The CPU outputs an X-direction address bus and a y-direction address A3/ of the memory via an address bus, and when performing scrolling, provides RLA for setting the scroll amount in the row direction and CA for determining the scroll amount in the column direction. The data bus is a 16-bit (bo-b1.) bidirectional bus. Register 8 has an address bus, a data bus,
The write signal (WR) is manually latched, and the instruction signal (X/Y) in the x and y directions, the signal RU to instruct vertical mirror image readout or left rotation, and the horizontal direction mirror image readout or clockwise rotation are instructed. Outputs signal CU, etc.

[Description of Memory Array (Fig. 3) Fig. 3 shows the configuration of the memory array 110 and the x, y address output section 2.3 of this embodiment.

100 is a 10-bit adder, 101 has the S terminal “O”
This is an 8-bit selector in which the A input is selected when ``1'' and the B input is selected and output to Y. Selector 101
The upper 8 bits of the adder 100 are input to the A input of the adder 100. 102 is a memory element which will be described later with reference to FIGS. 6 and 7, and has a capacity of 256×256×f bits. The memory element 102 is a 1-bit data input/output port 1.
0, there is an output port SO for reading data when used as an image memory, and a write terminal WE has an output port SO from the mask section 5. ~m33 receives an X/Y signal, etc. that instructs the x and y read directions.

[Description of Data Converter (FIG. 4)] FIG. 4 is a diagram showing the configuration of the data converter 4 that converts the bit array of data output to the memory array 110.

In the figure, 103 indicates B when the A/B terminal input 104 is “0”.
It is a tri-state buffer with bidirectional rotation that inputs from the A side and outputs to the A side, and conversely inputs from the A side and outputs to the B side when the A/B terminal input 104 is "1".
When the terminal 105 is "0", each output is enabled. Further, for example, if the A/B terminal power 104 is “0” (
To explain this in the case of writing to the memory 102), St
.

When the rotate input 106 of the SO terminal is 00'', the output is (AO, A
1. A2. A3). Rotate input 106 is “0”
When it is 1", the output is rotated 1 bit to the right with respect to the manual power (BO9Bl, B2.B3) as (AI, A2゜A3.AO). When the rotate manual power 106 is 10", the output is rotated 2 bits to the right. The output is rotated to (A2゜A
3. AO, Al), the rotate input 106 is “11”
In this case, the output becomes (A3.AO, Al, A2).
107 to 109 are 16-bit bidirectional tri-state buffers, and when On is input to the T terminal 111,
The signal is input from B and output from A, and vice versa when the T terminal 111 is P1''.

Also, when the OE terminal is "0", it becomes output data enable, and when it is '1', the output becomes high impedance. 30 is the memory 110 when the buffer 107 is selected.
Similarly, 31 indicates the bit position relationship between the memory 110 and the CPU 7 when the buffer 108 is selected. In both cases, the bit position on the CPU side is on the right side.

[Explanation of the mask part (Figure 5)] FIG. 5 shows the write signal mo to the memory array 110.

It is a block diagram of the mask part which outputs -m33.

113 is 4-bit raw data, which is input data (to, il) corresponding to the rotate input 114 of the So, St terminals.
, i2. Output data (00, O
f, 02, 03). Raw data 113 is CP
It is provided to associate the bit positions of the data bus U7 with the memory elements 102 of the memory array 110. This amount of rotation is the same as in the case of the bi-directional rotating tri-state buffer 103 described above.

115 is a 16-bit D type flip-flop.
Latch 16-bit data from CPU7.

[Explanation of the structure of the memory element (Fig. 6)
FIG. 2 is a diagram showing the configuration of the memory 102 shown in the figure.

500 and 501 are decoders in which any one of 256 output ports becomes "1" in response to the value of six 8-bit inputs, and 502 is a memory cell shown in FIG. 7, the total number of which is 256 x 256 = 65536. It is individual. 503,50
Both 256-bit D type flip-flops 4 latch 256-bit data from each memory cell in response to the tS signal. 505 and 506 both use 1 bit out of 256 bits to address AD 510
A data multiplexer that selects and outputs according to the
When X/Y input 10 is “0”, multiplexer 505
When the output of the multiplexer 505 is 1'', the output of the multiplexer 505 is selected and output as a 1-bit signal 11 (SOOO to 5.).

Note that io is a 1-bit input/output signal for each memory cell.

[Explanation of Operation (FIGS. 3.4 and 9 to 11)] The circuit operation will be explained based on the image memory 80 shown in FIG. 9.

In the image space, both the X-axis and the X-axis are defined as 0 to 1023, and this space 80 is divided into 4×4 pixels 81. In this embodiment, when the CPU 7 accesses the image memory 80, it is possible to read and write in units of 4 x 4. In particular, the pixel 81 can be read or written from an address other than a multiple of 4, that is, from any position on the X axis or y@. It is designed so that it can be accessed in 4×4 units even from the outside.

Therefore, even if X is 135, 136, 137° 138 and y is 210, 211, 212, 213, the CPU 7 can access them in one machine cycle.

This operation will be explained below.

If the CPU 7 now outputs Ax=135 as the X-axis address and Ay=210 as the y-axis address, the output of the adder 100 that outputs Axa will be "138" (=0
010001010), and the upper 8 bits "QO100010=34" are input to the A input of the selector 101. Now the S terminal tx of the selector 101 is “0”
'', Axo becomes 34°'.Similarly, AX
l=34. AX2=34, Ax3=33. Looking at the case in the y-axis direction, A y = 210 (1101
0010), so similarly, AYo "53.A
3'l=52. Ayz=2 and Ay3=52.

Memory array 1 addressed and read in this way
The 16-bit data (10°.~103s) from 10 is stored in the rotating tri-state buffer 103 in FIG.
is man-powered. St, So large input Ay of buffer 103
The lower 2 bits (10) of Ay are the same, and AX is the lower 2 bits (11) of AX, so for example, buffer 10
10° input to AO of 3. is output to B2, inputted to AO of buffer 103', and output to Bl (da9). If the THRU signal 116 is "ON" now, it is output to bit 9 of the data bus of the CPU 7 through the buffer 109.

Similarly, 10. . →Bit 13. io・2o→bit 1. io,. →Bit 5. io,, → bit 10°10
8. -Bit 14. io2+→bit 1. io3+→bit 6.1002→bit 11. i0+2 → bit 15
, 1022 → bit 3. to,,-bit 7゜10゜,
-bits 8, 1o13-"bits 12.io2゜-bits O, io, , → bits 4 are converted and output. That is, this means that X is "135 to 138" and y is "210 to The 4×4 matrix data addressed by 213” is stored as 1 word (16 bits) of data.
This indicates that the data is output to the CPU 7 at the same time. In this case, it is of course possible to write 4×4 matrix data into the memory array 110 at one time by setting the write signal (WR) 117 to “0”.

Also, instead of turning on the THRU signal 116,
When the HER signal 118 is set to 0'', the flip-flop 1
Every time a read signal (RD) 120 or a write signal (WR) 117 is input by 19, D I T o
The signal 121 and the D I T 1 times signal 122 alternately sound 0. When the D I T o signal 121 becomes 0, the buffer 107 is selected, and when the DITI signal 122 becomes 0, the buffer 108 is selected, and each 30 The bit position is changed as shown in .31.

Figure 10 shows that when one pixel is represented by a 4x4 matrix,
This figure shows a pattern in which the number of bits increases as the density increases, and 17 stages of patterns 900 to 916 are shown.

FIG. 11A shows each of the patterns 900 to 916 in FIG. 10 expressed in 16 bits, and each word corresponds to the patterns 900 to 916. Figure 11 (A)
In this case, since the "0" run and "1" run are short, the compression ratio cannot be increased much when performing run length compression, MH compression, MR compression, MMR compression, etc., for example. However, when these pattern data are read out via the buffer 107 of the data converter 4 in FIG. 4, the bit positions are converted as shown in 30, resulting in a pattern data string as shown in FIG. 11(B). is obtained. Also buffer 1
08, the pattern data string shown in FIG. 11(C) is obtained.

As you can see from Figure 11 (B) and (C), “0” and °°1”
Since each run (white and black) becomes longer, the compression ratio improves. In particular, by passing the data alternately through the buffers 107 and 108, the white run and black run can be made twice as long even when the density is the same.

Since such conversion is performed for each bit, even if the image contains not only density but also graphic information like a normal dithered image, it can be compressed to a certain degree. Furthermore, by changing the way the bit positions are converted, it is also possible to support different density pattern data.

[Explanation of the mask part (Fig. 5) FIG. 5 is a diagram showing the circuit configuration of the mask section 5. As shown in FIG.

The D type flip-flop 115 is set to 1'' with the data bus bit corresponding to the element to which writing is not performed among the 4×4 matrix memory elements 102.Sl, So of the 4-bit raw data 113 The lower 2 bits of Ax and Ay are input manually to each terminal,
The bit positions of the data bus are associated with the bit positions of the 4×4 matrix. When other signal conditions are satisfied in the write mode, the output of the three-man OR circuit 124 becomes "0", and the write signal mQQ of each memory cell 102 other than the one set to "1" passes through the two-man OR circuit. ”m33
becomes “0”. This allows writing to a desired memory cell 102 or prohibiting writing.

[Description of Structure of Memory Cell (FIGS. 5 and 6)] FIG. 7 is a circuit diagram of each memory cell 502 in FIG. 6.

60 is a D-type flip-flop that latches 1-bit data; when writing, the buffer 64 is enabled by opening the 3-way AND circuit 63;
1-bit data at the 0 terminal is input to a D-type flip-flop 60 and latched by a WE signal 69. On the other hand, during reading, the WE signal 69 is at H" level, so A
The ND circuit 61 is opened and the signal is read out to the io terminal via the buffer 62. Naori X,, DY, are respectively x described later
, is a signal for reading bits in the X direction.

[Explanation of reading video signal (Figs. 6 to 8)] Fig. 8 shows how the video signal 7 is read when the memory array 110 is used as an image memory.
16 is a circuit diagram when reading as 16. FIG.

In the figure, 700 is a 20-bit counter, and memory array 1
Determine ten 1024x1024 pixel (vixel) addresses. 705, 707, and 708 all invert the i input and output it as "0" when the S terminal input is "1".
When , it is an output inversion circuit that outputs the output as is. The operation starts from the state where all bits (QO-Q19) of the counter 700 are 1". At this time, the output ts of the AND circuit 701 is 1", and the X/Y signal is 1", that is, reading in the X direction. tx becomes “1” for instruction, and ty becomes “1” for reading in the X direction.At this time, the output of adder 704 is “1”.
0", and when the S terminal human input RU signal of the output inverting circuit 705 is "0", its output becomes "0". Furthermore, RL
If the input of A is also “0”, the output of adder 706 is R
The A-fold signal becomes "0".

Considering the case of reading in the X direction, ty=t in FIG. 3, and RA multiplied signals are output from Ayo to Ay3.

Also, as mentioned above, since ts=1, the flip-flops 503 and 504 in FIG.
j signal is latched. Since the Ay times signal is “0”,
The DYo signal of the decoder 501 becomes '1'', and the signal OXO~0X2S from the memory cell 502 in the first row in FIG.
5 is read out and latched into flip-flop 503.

Since the X/Y signal is now “0”, multiplexer 5
05 is enabled, and the address signal 51 is output from 0.
1-bit data corresponding to address 0 is output. Every time the counter 511 is incremented by 1, the address signal 510 is incremented by the output inverting circuit 512 when U/D (CU signal) is "0", and conversely decreases when U/D is "1". , the bit signals of the memory cells are sequentially output in the horizontal direction.

Next, in FIG. 8, when the timing signal VAS changes from "0" to "1", the counter 700 outputs +it/, and all 20-bit outputs become "0".Here, CU.

When the RU multiplied signal is "0", the outputs of the output inverting circuits 707 and 708 are both "0". Now the X/Y signal is “0”
Therefore, in the selector 709, IOa+Ila is z,
, Zb, the selector 710 sets I, □ Ilb to Za,
It is output to Zb. As a result, multiplexer 712 is selected, and only the human power SO0° of 712 is selected and latched by the VAS signal in flip-flop 715, which is output as video signal 716.

Similarly, when the VAS signal repeats "ON" and "1", the counter 700 is incremented by 1, and so on.

5OO21SO03 are selected one after another and the video is output. In synchronization with this, the decoder 714 counts up the counter 511 of the memory 102, updates the address signal 510, and prepares the next data. When the VAS signal turns on and off 1024 times in this way, the output Q10 of the counter 700 becomes 1'', and from then on, SO,...
~SO3° are sequentially selected to become a video signal. Similarly, S 020 to S 023. SO3o~
S Oss is selected and output. In other words, 5OO0~
5OO3 pattern 256 times, SO5oNS O3
s(D pattern is repeated 256 times and output as a video signal 716.

When the outputs QO to Qll of the counter 700 all become "1", ts becomes 1" again, and when X/Y is "0", ty becomes "1". At this time, the outputs of the counter 700 Q12 to Q
Since 19 is still "0", RA becomes 1", and Ay0 to A"/3 in FIG. 3 are "1". Therefore, the sixth
Since the AY large input in the figure becomes "1", only DY is outputted by the decoder 501, the memory cell 502 in the second row is selected, and the output data ○X from them is output.

~0Xzss is latched in the D flip-flop 503. Similarly, from the memory array 110, 1024X
All 1024 point data are video signals (VIDEO)
It is output from the flip-flop 715 as 716.

[Explanation of reading out a mirror image in the horizontal direction] A method for obtaining a mirror image in the horizontal direction will be explained based on FIG.

This case can be obtained by setting the CU signal input to the output inverting circuit 708 to "1".

When the CU signal is set to "1", the output of the counter 708 is inverted, and when the output of the counter 700 is all bits "0" and X/Y=O, the multiplexer 712 is selected. The input of multiplexer 712 is S2S.

5o=011, and 5003 is selected and input to the flip-flop 715 and output as a video signal 716. Next, when the counter 700 increases by 1, 5OO2 is selected, and then 5oot, 5Ooo, and S 02.
3~S 020. S Os to S 030 are sequentially output.

In this way, CU=1 is output from the right side of the memory array 110 and is sent to the S terminal of the output inverting circuit 512 in FIG.
Since "1" is inputted, the inverted value of the counter 511, that is, the address data 510 in the direction in which the X direction address decreases, so that a mirror image in the horizontal direction is obtained.

As described above, the clock SC of the counter 511 is driven by the VAS signal in the same manner as the selection of the multiplexers 711 and 712 for outputting the video signal 716 in FIG.

[Description of how to obtain a mirror image in the vertical direction] To obtain a mirror image in the vertical direction, first, in Fig.
Set the flaw signal to “1”. As a result, when the output of the counter 700 is "0", the multiplexer 711 is selected, and the input SO3° is first selected and output. Next, S03□ to 5033 are selected in order, and when 1024 bits are output, 5O20 to So,3 are output next. Multiplexer 712 is then selected and 5olo~
3013, 5OOO to 5OO3 are selected in this order and output as a video signal 716. Also, since the RA flaw signal output inverting circuit 705 decreases as the counter 700 increases, the output of the Y decoder 501 in FIG.
The signals are output in the order of DYO and read vertically from bottom to top to obtain a vertical mirror image.

[Method for Obtaining Rotated Figures (Figs. 6 and 8)] Conversion in the X and Y directions will be explained based on Figs. 6 and 8.

Now, set the X/Y signal to "1" and set the CU signal to "1".
", set the RU scratch signal to "0". First, set the counter 700.
When all output bits of ts=1. tx=1. Next, when the output of the counter 700 becomes "0", the output Z of the selector 709.

zb is "11" and the output of 710 is "00". Therefore, multiplexer 711 is selected and SO2° is output. Next, the counter 700 is incremented by 1, and only QO is “1”.
”, the output of 708 becomes 10” and selector 70
The output of selector 710 is “°゛10”, while the output of selector 710 is “
It becomes 00°゛.

As a result, the 5o2o input of the multiplexer 711 is selected and output as a video signal 716. Next, when the output of the counter 700 becomes "2", the multiplexer 71
2 is selected and Sol. is output. In this way, the output pattern of the video signal 716 is S O30,S
O20, S Oro, S Oa.

...SO3, ~5Ool ...5o32~5Oo
2... Output in the order of 5033 to 5OO3.

In FIG. 6, since X/Y=1, selector 506 is selected and data in the Y direction from flip-flop 504 is output. At this time, since the U/D signal (CU) is 1'', the address signal 510 of the selector 506 is VAS
Since it decreases in synchronization with the signal, data in the decreasing direction in the Y direction is output, and an image rotated 90 degrees to the right is obtained.

Similarly, if X/Y=1, RU=1, and CU=0, S Oa3. S O13, S O23, S O3
3゜-, S Oo2~S 032. ”, S 001
~S 031. ”・Soo.˜S03° are output to the video signal 716 in the order, so a left-rotated image is obtained.

[Description of Scrolling] To perform scrolling in the row direction, set the desired number of scrolls in RLA in FIG. As a result, RA starts from the value of RLA, so the output video signal 716 becomes data scrolled in the row direction.

Next, in order to scroll in the column direction, data corresponding to the scroll amount is set in CA in FIG. This causes the address signal 51
Since 0 starts from that value, scrolling in the column direction is performed. Since RLA and CA are both 8 bits here, scrolling of about 4 rows or 4 trains corresponding to the matrix of the memory array 110 is possible.

As described above, according to this embodiment, since matrix data can be simultaneously accessed at any address, the memory access time can be reduced.

Also, B! of the block in the memory space! This has the advantage that lI, rotation, etc. can be easily performed.

Furthermore, according to this embodiment, scrolling in the row and column directions can be easily performed.

Furthermore, since bit strings can be rearranged in accordance with a dither matrix or the like, it is extremely effective in data compression and the like.

[Effects of the Invention] As described above, according to the present invention, the bit strings of access data can be rearranged in accordance with, for example, a dither matrix, so that the efficiency of data compression etc. can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of the image memory of this embodiment, Fig. 2 is a diagram showing the connection between the image memory and CPU of this embodiment, and Fig. 3 shows the x, X address output section and memory arrangement. 4 is a diagram showing the configuration of the data conversion section, FIG. 5 is a diagram showing the configuration of the mask section, FIG. 6 is a block diagram of the memory element, FIG. 7 is a configuration diagram of the memory cell, Fig. 8 is a diagram showing the configuration of the video output section, Fig. 9 is a diagram showing the relationship between image memory and pixels, Fig. 10 is a diagram showing an example of the density pattern of the dither matrix, and Fig. 11 (A) is a diagram showing the relationship between the image memory and pixels. 10 is a diagram showing the pattern of FIG. 10 as a bit arrangement. FIGS. 11(B) and 11(C) are diagrams showing an example of conversion of the bit arrangement by the data conversion section of this embodiment. In the figure, 1...image memory, 2...X address output section, 3...X address output section, 4...data conversion section,
5...Mask section, 6...Video output section, 7...C
P.U. 8...Register, 10o...Adder, 101...
Selector, 102... Memory element, 103... Bidirectional buffer with rotation, 107-109... Buffer, 113... Buffer with rotation, 500.50
1... Decoder, 502... Memory cell, 503.
504...Flip-flop, 505.506...
Multiplexer, 510...address signal, 511...
...Counter, 512.705.707.708...
Output inversion circuit, 709.710...Selector, 711
．． 712...Multiplexer, 713.714...
It is an encoder. Patent applicant Canon Co., Ltd. No. 71! I Figure 9 Figure 11 (B)

Claims (3)

[Claims] (1) A memory array including memory elements arranged in an n×m matrix, a first address means for outputting an address corresponding to the position of the memory element in the row direction, and a column direction of the memory element. a second address means for outputting an address corresponding to a position of the second address means, an input/output means for accessing the memory array addressed by the first and second address means, and a bit arrangement of access data of the memory array. A memory circuit comprising: bit position changing means for rearranging the bit positions. (2) The memory circuit according to claim 1, wherein the bit position changing means lengthens a data string of 1 or 0 in accordance with a dither pattern. (3) The bit position changing means includes a first bit array means for lengthening a data string of 1 from the MSB of one word of data for the same dither pattern, and a LS of one word of data.
and a second bit array means for lengthening the data string from B to 1, and the first and second bit array means are used alternately.
The memory circuit described in section.