JPH023163A - Multi-port memory - Google Patents

Abstract

PURPOSE:To make the input/output of data high speed and to process the data at high speed by obtaining a multi-port memory in which the input/output are executed parallel every plural input/output parts to stored different information and inputting the information of a information width different from the information width of the information inputted and outputted at other input/output part with the one of the plural input/output parts. CONSTITUTION:Data stored in a main memory 13 are given to a data processing part 15 through a dual port memory 11, fixed processing is executed, and the processed data are stored to the memory 13 through the memory 11. Then, data A from the device 13 are given from an input/output circuit 17 to a multiplexer 19 and are stored to an address designated with an address decoder 23 of a memory cell array 21. Next, data B are loaded by the multiplexer 19 in the same way as the data A and are stored on the same word line as the one on which the data A of the array 21 are stored. The stored data A and B are read in a lump and the data of a corresponding size to the bit width of the respective data A and B are processed at the data processing part 15.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application)
The present invention relates to a multi-port memory that is used as a memory and enables high-speed data processing.

(Prior Art) Recently, multi-port memory has been developed as a memory for the image field, which is equipped with a plurality of independent input/output paths (boats) and input/output data independently through these multiple input/output paths. is frequently used.

In such a multi-port memory, each port has the same data width. That is, the data output from the memory cell array of the multi-port memory and the data input to the memory cell array have the same width in all ports.

For example, a 2-port memory ([)ua as shown in FIG.
Port Memory), for example, 32-bit wide data is sent via input/output path 1 on the first port side.
input/output between the memory cell array 5 at the address specified by the address decoder 3 for the first boat and the outside,
Independently from this, 32-bit wide data is transferred between the memory cell array 5 at the address specified by the address decoder 9 for the second boat and the outside via the input/output circuit 7 on the second boat side. input and output.

The input/output data of such a 2-port memory is stored in an external main storage device, for example, in a 32-bit width as shown in FIG. There are cases in which the information is paired and indicates three pieces of information. That is, a total of 64 bits of data, data A and data B, consists of 32 bits of base address, 24 bits of area size, and 8 bits of attribute (protection information) when dividing the memory space into areas. It represents one piece of information. As shown in FIG. 5, data A consists of information from the 0th bit to the 15th bit of the base address and information from the 0th bit to the 15th bit of the area size. On the other hand, data B
As shown in Fig. 5, it consists of information from the 16th bit to the 23rd bit of the area size, an 8-bit attribute, and information from the 16th bit to the 31st bit of the base address. There is.

Therefore, in order to input or output such 64-bit data between the external main storage device and the two-port memory, data A and data B must be input or output twice. Roughly speaking, in order to process data A and data B read from the memory cell array, each piece of information from data 8 and data B is arranged in a manner suitable for processing, as shown in FIG. There must be.

Therefore, when processing, for example, data A and data B using a 2-port memory configured as shown in FIG. 5, data A is loaded from the main storage device to the memory cell array 5 of the 2-port memory. (1 step), loading data B from the main memory to the memory cell array 5 (2 steps), reading data A from the memory cell array 5 (3 steps), reading data B from the memory cell array 5 (4 steps) , Arranging data A and data B (5 steps), Processing the arranged data (6 steps), Rearranging the processed data into data A and data B (7 steps)
, write data A to memory cell array 5 (8 steps), write data B from memory cell array 5 (9 steps), store data A from memory cell array 5 to queen TG device (step 10), memory Eleven steps are required, such as storing data B from the cell array 5 to the main memory (step 11).

(Problems to be Solved by the Invention) As described above, in a conventional multi-port memory where each port has the same data width, when processing the stored data in combination, the stored data had to be input and output at least twice. Therefore, there has been a problem in that it is difficult to input and output data at high speed.

Therefore, the present invention has been made in view of the above, and its purpose is to provide a multi-port memory that can perform data input/output at high speed and contribute to speeding up data processing. It is in.

[Structure of the Invention] (Means for Solving the IF Problem) In order to achieve the above object, the present invention is provided with a plurality of input/output sections, and each of the plurality of input/output sections handles different stored information. In a multi-port memory in which input/output is performed in parallel, at least one input/output section among the plurality of input/output sections has an information width different from that of information input/output to/from the other input/output sections. It is configured to input and output information.

(Operation) In the above configuration, the present invention allows at least one of the plurality of input/output units to input/output information having an information width different from the information width of information input/output to the other input/output units. That's what I do.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a multi-boat boat according to an embodiment of the present invention. The multi-port memory shown in the figure has two ports ([)ual Port)
It's memory.

In FIG. 1, the 2-port memory 11 is configured to input and output 64-bit data configured as shown in FIG. The second port is used for data input/output with the external main storage device 13 in which the 2-port memory is stored.
Used for data input/output with 5.

The input/output circuit 17 of the first port is connected to the main memory device 13, and inputs and outputs data to and from the main memory IA device 13 in a width of 32 bits.

Further, the input/output circuit 17 is connected to a multiplexer 19.

The multiplexer 19 is connected to a memory cell array 21 of a two-port memory. The memory cell array 21 is
The number of columns is set to 64 bits, and for example, 32-bit data A as shown in FIG. 5 is stored in the 32-bit area on the left at the address specified by the address decoder 23, and In the bit area, 32 bits of data B, which is paired with data A, is stored at the address specified by address decoder 25 on the same word line (same row) as data A. Therefore, the multiplexer 19 separates the 32-bit data A and data B provided from the input/output circuit 17, and
It is given to each gAbA of the memory cell array 21.

On the other hand, the input/output circuit of the second port is composed of three input/output circuits, each input/output circuit is connected to the data processing section 15, and the input/output circuit of the second port is connected to the data processing section 15 and the two-port memory 11. It performs input and output. Three input/output circuits input and output base address information.
A 2-bit wide base address input/output circuit 27, an 8-bit wide attribute input/output circuit 29 that inputs and outputs attribute information,
It consists of a 24-bit wide size input/output circuit 31 that inputs and outputs information about the size of the area. As shown in FIG. 6, the information that each input/output circuit inputs and outputs is the base address information and attribute information obtained from data A and data B when dividing the memory space. , corresponds to information on the size of the area. These input/output circuits independently input and output information, and simultaneously input and output information. Therefore, on the first port side, 32-bit wide data is input/output all at once, while on the second port side, up to 64-bit wide data is input/output all at once. It turns out.

Further, these input/output circuits are connected to a bit rearrangement circuit 33.

The bit rearrangement circuit 33 is connected to the memory cell array 21, and converts a total of 64 bits of data A and data B stored in the memory cell array 21 to the base address as shown in FIG. information, area size information, and attribute information, and provides each of the arranged information to the corresponding input/output circuit. moreover,
The bit rearrangement circuit 33 is the base address input/output circuit 2
As shown in FIG. B and is applied to the memory cell array 21.

As explained above, one embodiment of the present invention is constructed, and the operation of this embodiment will be explained next with reference to FIGS. 2(A) to 2(F).

Here, the operation of this embodiment is such that the data stored in the main memory gA213 is given to the data processing unit 15 via the 2-port memory 11 to perform predetermined processing, and the processed data is sent via the 2-port memory 11. An example will be described in which the data is applied to the main memory line 11 and stored.

First, 32-bit data A stored in the storage device 13
is loaded from the storage device 13 and the loaded data A is applied to the multiplexer 19 via the input/output circuit 17. As shown in FIG. It is given to the address designated by the address decoder 23 of 21 and stored.

Next, data B is loaded from the main memory 13 in the same way as data A, and is loaded by the multiplexer 19 as shown in FIG.
), data A of the memory cell array 21 is applied and stored on the same word line where it is stored.

Data A and data B stored in the memory cell array 21 are read out all at once and given to the bit rearrangement circuit 33, and the bit array circuit 33 rearranges them into 32-bit wide data as shown in FIG. 2(C). The information is arranged to represent the base address, 8-bit width attribute, and 24-bit width area size, and the information that requires processing is sent to the data processing unit 15 through the corresponding input/output circuit. given to.

When the data processing unit 15 completes the processing and stores the data in the main memory 13 again, the information that needs to be stored is given to the bit rearrangement circuit 33 via the corresponding input/output circuit. As shown in FIG. 2(D), data A and data B of 32 bits are arranged and written into the memory cell array 21.

The written data A is applied to the main memory 13 via the multiplexer 19 and the input/output circuit 17 and stored therein, as shown in FIG. 2(E).

Next, as shown in FIG. 2(F), data B is also given to the main memory 13 and stored in the same way as data A.

In this way, the series of operations described above, as shown in FIGS. 2(△) to 2(F), include loading data A (first step), loading data B (second step), Reading and arranging data A and data B from the memory cell array 21 (third step), data processing (fourth step)
, writing of the data arrangement and data A and data B given from the data processing unit 15 to the memory cell array 21 (
5th step>, store data A (6th step),
This is performed in a total of seven steps, including storing data B (seventh step).

Therefore, whereas conventionally a similar operation required 11 steps, the embodiment of the present invention requires 7 steps.
Since data processing can be performed in steps, data processing can be performed at high speed.

Furthermore, by taking advantage of the characteristics of the two-port memory, as shown in Figure 3, if the input/output operations on the first port side and the input/output operations on the second port side are performed in parallel, Data processing can be performed even faster.

In the above-described embodiment, a two-port memory has been described, but the present invention is not limited to this, and it goes without saying that a multi-port memory having two or more ports may be used.

[Effects of the Invention] As explained above, according to the present invention, the information width of information input and output from at least one input/output unit among the plurality of input/output units via other input/output units is Since information of different information widths can be input and output, it is possible to input and output information at high speed, and it is possible to provide a multi-port memory that contributes to speeding up information processing.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a 2-port memory according to an embodiment of the present invention, Figs. 2 and 3 are explanatory diagrams of the operation of the 2-port memory shown in Fig. 1, and Fig. 4 is a conventional 2-port memory. Figures 5 and 6 are diagrams showing an example of a memory configuration, and Figures 1 and 4 are similar to Figures 1 and 4.
FIG. 3 is a diagram showing the configuration of input/output data of the two-port memory shown in the figure. 11...2-port memory 17.27.29.31...I/O circuit 21...Memory cell array

Claims (2)

[Claims] (1) A multi-port memory including a plurality of input/output sections, in which input/output is performed in parallel for each of the plurality of input/output sections for different stored information, and at least among the plurality of input/output sections. A multi-port memory characterized in that one input/output section inputs/outputs information having an information width different from that of information input/output to/from another input/output section. (2) The multi-port memory according to claim 1, wherein at least one of said input/output units among said plurality of input/output units is provided with an arrangement means for changing the arrangement of given information.