JPS6353558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix display device, and more particularly to a line-sequential scanning matrix display device including a data storage device suitable for storing one line of image data.

Matrix display devices include those that use plasma, electroluminescence, liquid crystal, etc. Among these, liquid crystal consumes almost no power by itself, so if the drive circuit is selected appropriately, it can be used as an extremely low-power display device. It is possible to realize this.

However, drive circuits for conventional liquid crystal display devices generally have slow operating speeds, as explained below.
It is characterized by particularly low power consumption.
When using a low-speed element such as a CMOS-IC (complementary MOS integrated circuit), it could not be used when the frequency of the image data signal was close to 4MHz, such as for television images.

FIG. 1 is a diagram showing the configuration of a matrix display device that operates in a line sequential scanning method, and the second diagram is a diagram showing operating waveforms of each part. The input signal of the display device is the video signal V, which is connected to the control circuit 3 and AD in FIG.
Connected to converter 4. The control circuit 3 generates a timing signal necessary for the operation of the display device based on the synchronization signal in the video signal V, and controls the scanning circuit 2 and AD.
It is supplied to the converter 4 and the column electrode drive circuit 5. Of these, what is supplied to the line memory 500 is a write signal CP ₁ and a latch signal CP ₀ whose waveforms are shown in FIG.
It is. In Fig. 2, 1H is the horizontal scanning time, which is 63.5 μS for Japanese television signals. The write signal CP ₁ includes N panels per 1H within the valid period excluding the horizontal retrace period of the video signal V. Here, N is the number of columns of pixels in the display device. Furthermore, the latch signal _CP0 includes one pulse within the horizontal retrace period of the video signal V.

The AD converter 4 in FIG. 1 receives the video signal V and the write signal _CP1 as input, and converts the analog voltage value of the video signal V into a digital image data signal DV.
Since the write signal CP ₁ is used as a timing signal for this conversion, the frequency of the image data signal VD is the same as the frequency of the write signal CP ₁ . As an example, if the number of pixel columns is N=320, these frequencies are
f ₁ =6.4MHz.

Further, the number of bits of the image data signal VD is related to the number of gradations of the display device, and here, as an example, it is assumed to be 4 bits (which enables display of 16 gradations).

Scanning circuit 2 inputs latch signal CP ₀ and outputs 1H.
The row electrode signals X ₁ to X _M , which are the outputs thereof, are switched each time, and the row electrodes of the display panel 1 are scanned.

The inside of the column electrode drive circuit 5 is further divided into a line memory 500 and a driver 51. The line memory 500 has a storage capacity of (4 bits) x (N words), and the image data signal DV is written in 4 bits at a time N times in 1H, and this writing is performed using the write signal _CP1. This is done in sync with the Also, the output of the line memory 500 is (4 bits) x (N words)
are read simultaneously. This readout is performed in synchronization with the latch signal _CP0 after 1H of writing is completed. The output of this line memory 500 is sent to the driver 51 as a brightness command signal DY _j (j=1 to N).
supplied to Each DY _j is a 4-bit digital signal, and the driver 51 generates N column electrode signals whose pulse widths are modulated in 16 steps corresponding to the value of each DY _j .
Y _j (j=1 to N) is generated and supplied to the column electrodes of the display panel, the brightness of each pixel is modulated, and an image is displayed on the display panel.

Now, since the purpose of the line memory 500 as described above is to convert signals from serial to parallel, a shift register has been used as its component. Third
The figure shows an example of such a conventional integrated circuit. One integrated circuit in this example can drive 40 column electrodes, and outputs column electrode signals Y ₁ to Y ₄₀ . The shift register is constructed by arranging 40 flip-flops 53 in series. The data input terminal D of the flip-flop 53 at the left end of each book is
One of the 4-bit image data signals DV _A to _DVD is respectively input. Since the write signal CP ₀ is input to the clock terminal C of each flip-flop, image data is shifted into the shift register 53 from left to right in synchronization with CP ₀ . In this case, since the first input image data is stored at the right end, the right end output in the figure corresponds to the column electrode signal _Y1 . 4
The outputs M _1A to _{M 1D} of the rightmost flip-flops of the main shift register are output to the outside of the integrated circuit.

The data stored in the shift register of this integrated circuit is from the first word ( _M1A to _M1D ) to the 40th word ( _{M40A to} M1D).
M _40D ), each word is 4 bits. All this data is connected to each flip-flop 52 as a latch register, and is transferred to the latch register in synchronization with the latch signal _CP0 . The output of the first word of the latch register is a 4-bit brightness command signal DY _1A to _{DY 1D} , and similar outputs exist up to the 40th word DY _40A to DY _40D .

The driver 51 generates a column electrode signal that controls the brightness of the display panel in response to a brightness command signal, but its details are not directly related to the present invention and will therefore be omitted. In general, the driver 51 requires various control signals in addition to the line memory 500, so these are collectively indicated as a driver control signal M in the figure.

Since the number N of column electrodes in a display device is generally 40 or more, it cannot be driven by one integrated circuit of this example. FIG. 4 shows a connection method when three integrated circuits 6, 7, and 8 are used to drive N=120 column electrodes. The key point is to transfer the memory signals M _1A to M _1D , which are the outputs of the shift registers of the left integrated circuit, to the shift registers of the right integrated circuit (see Figure 3).
DV _A to DV _D ) so that there are a total of four 120-bit shift registers.

Next, the drawbacks of the conventional system such as this example will be explained using FIG. This figure shows the waveform of the memory signal _M1A in FIG. 4. The shift register of this integrated circuit is assumed to operate at the falling edge of the write signal _CP1 , and the memory signal _M1A begins to change a little later than the falling edge of _CP1 . However, for the memory signal M _1A , the load is the capacitance of the output pin of the integrated circuit, the wiring capacitance of the printed circuit board, and the capacitance of the input pin of the next stage integrated circuit. must be slower than the internal signals of the integrated circuit. Now, if the time from the fall of the write signal CP ₁ until the memory signal M _1A reaches the threshold value of the input terminal of the integrated circuit is the delay time t _d , then t _d is longer than the period t _c of the write signal CP ₁ . Needs to be small. For this reason, the frequency of conventional integrated circuit CP ₁ is 400KHz
It was not possible to operate at high speed.

In addition, since four memory signal outputs are required, the integrated circuit has a large number of pins and is expensive. Furthermore, as a measure to reduce the above-mentioned t _d , it may be possible to output the memory signals M _1A to M _1D through powerful buffer amplifiers, but such buffer amplifiers require a large chip area, and if as many as four of these buffer amplifiers are incorporated, It also had the disadvantage of being more expensive.

In addition, the write signal CP ₁ is set at just N during 1H in order to stop the shift operation when the image data reaches the right end of the shift register.
It is necessary to generate only =120 pulses, and the control circuit 3 of FIG. 1 requires a counter to count the number of CP ₁ , which has the disadvantage of making it complicated.

An object of the present invention is to provide a data storage device which eliminates the drawbacks of the prior art described above, which is simpler, has fewer pins when integrated into a circuit, and which can operate faster than the conventional technology even when using elements of the same speed. The present invention provides a matrix display device including:

In order to achieve the above object, in the present invention, an address counter is provided for each unit integrated circuit, an image data signal is written to a memory cell by the output of this address counter, and this write operation is completed. By outputting a carry signal from the address counter at a point in time and giving only this one signal to the next stage integrated circuit, the operation of the address counter in the next stage integrated circuit is started. The feature is that it is easy to insert an amplifier to improve the rise of the carry signal, and the carry signal is output a little earlier than the end of the write operation, and the carry signal is output at the end of the write operation. It is characterized by being structured in such a way that it can be established reliably.

Hereinafter, the present invention will be explained in detail with reference to Examples.
FIG. 6 is a diagram showing an embodiment of the present invention. In this figure, a driver 51 and a latch register 52 are similar to those in the conventional example shown in FIG. However, the shift register 53 in FIG. 3 is replaced with a memory cell 61, an address counter 54, and a logic gate 55 in FIG.

The memory cell 61 has a capacity of 40 words, and one word is 4
It is a bit memory and is used to write a 4-bit image data signal DV into a word specified by address signals _A1 to _A6 . A write operation is performed only when memory clock W is input. The outputs M ₁ -M ₄₀ of memory cells 61 are each 4 bits and serve as inputs to latch register 52 like conventional memory signals.

The address counter 54 is a 41-decimal counter,
Can count from 0 to 40. Its reset terminal R is connected to the latch signal _CP0 , and the content of the counter 54 becomes 0 when _CP0 occurs. The contents of the counter 54 are incremented by 1 each time the memory clock W is applied to the clock terminal CP thereafter. The contents of the counter 54 are address signals A ₁ to A ₆
and is input to the memory cell 61. The address counter 54 also has a carry terminal CR as another output, and this output becomes 1 when the content of the counter 54 reaches 40, and becomes 0 otherwise. Carry signal C
is output externally as .

The enable signal E, which is a new input signal provided to the integrated circuit, the carry signal C, and the write signal CP ₁ are input to the logic gate 55, and the CP ₁
=1, E=1, and C=0, the output W=1.

The operation when these elements 61, 54, and 55 are combined is as follows.

First, while the enable signal E is 0, the memory clock W is always 0, and neither the counter 54 nor the memory cell 61 performs any operation. enable signal E
When becomes 1, the memory signal W is generated simultaneously with the write signal CP ₁ , and the counter 54 is set to 0 to 3.
Start counting up to 9 (counter was initially reset by latch signal _CP0 ). At this time, data from the first word to the 40th word is written into the memory cell 61. After the 40th pulse of the memory signal W occurs, the contents of the counter 54 become 40,
Carry signal C=1. Therefore, after this point, even if the write signal _CP1 is generated, the memory signal W is not generated, and writing and counting are stopped. The data written in the memory cell 61 is transferred to the latch register 5 when the latch signal CP ₀ is input next time.
At the same time, the counter 54 is reset and the carry signal C becomes 0.

FIG. 7 shows the connections when a plurality of such integrated circuits 16 to 18 are used, and FIG. 8 shows waveforms illustrating the operation thereof. The main points in Figure 7 are that each integrated circuit 1
6, 17, and 18, the carry signal C of the left integrated circuit is used as the enable signal E of the right integrated circuit. However, the enable signal _E1 of the leftmost integrated circuit 16 is always set to 1.
As can be seen in FIG. 8, in this case the integrated circuit 16
writes during the first 40 pulses of the write signal CP ₁ , and the integrated circuit 17 writes during the next 40 pulses of the write signal CP 1.
8 further writes during the next 40 pulses.

As described above, according to the embodiment of FIG. 6, since each integrated circuit includes a counter, the write signal
The number of pulses of CP ₁ should be N=120 or more, and the
There is no need to count the number of pulses in the control circuit 3 shown in the figure, and the control circuit can be simplified.

Figure 9 shows an enlarged waveform of the carry signal C. This signal C is the 40th pulse of CP _1.
It occurs at the falling edge of CP 1 and needs to be established by the falling edge of CP ₁ of the 41st pulse. That is, t _d < t _cp
This point is similar to the conventional memory signals A _1A to M _1D . However, in the case of FIG. 6, since only one output is required, it is easier to provide a more powerful buffer amplifier than in the past to speed up the rise. Furthermore, since the total number of pins of the integrated circuit is smaller than before, the cost is also lower, and when using the same package, it is possible to increase the number of column electrode signals than before.

Next, an embodiment which is a further improvement of the embodiment shown in FIG. 6 and which enables high-speed operation will be described. The gist of this is to advance the timing at which the carry signal C shown in FIG. 6 is generated as much as possible to compensate for the delay time caused by the load capacitance. FIG. 10 shows a waveform when the carry signal C is generated at the falling edge of the 39th pulse of the write signal CP ₁ instead of the 40th pulse according to the present policy. As shown in the figure, the delay time t _d of the carry signal
Even if tc is larger than the period _tc of the write signal, if _td > _2tc , the next stage integrated circuit can start the write operation at the 41st pulse of the write signal _{CP1 .} Can be made small and operate at high speed. However, t _d
varies depending on the power supply voltage and temperature, so it is possible that t _d < t _c in the figure. At this time, the next stage integrated circuit is not the 41st pulse of CP ₁ ,
Writing starts from the 40th pulse, resulting in a malfunction.

FIG. 11 shows a line memory that takes these points into consideration. This figure shows the inside of the line memory 501 in FIG. 7. Memory cell 61 is the same as in FIG. The operating waveforms of each part in Figure 11 are shown in Figure 12.
As shown in the figure.

In FIG. 11, the address counter is divided into a first counter 541 and a second counter 542. After the first counter 541 is reset by the latch signal CP ₀ , the frequency of the write signal CP ₁ is halved.
It operates on the falling edge of the write signal _CP1 . This first counter 541 operates at all times regardless of the enable signal E, and uses its output as the address signal _A1 .

The flip-flop 58 is newly provided to process the enable signal E, and is reset by the latch signal _CP0 supplied to the reset terminal, and the address signal supplied to the clock terminal C.
The enable signal E supplied to the data input terminal D is set at the falling edge of _A1 . This output is designated as the second enable signal F. As shown in Figure 12, the second
The enable signal F is from the first enable signal E.
Occurs with a delay of two pulses of CP ₁ . A second enable signal F is provided to logic gates 55 and 56.
The logic gate 55 is also input with an address signal _A1 and a second carry signal _C3 , which will be described later.
Address signal A ₁ is output as count clock C ₂ only when C 3 =1 and C ₃ =0. logic gate 56
is similar to gate 55, except that it transmits write signal _CP1 to its output, memory clock W, under the same conditions.

The second counter 542 is a 21-decimal counter,
The latch signal CP ₀ supplied to the reset terminal R causes its content to become 0, and then the clock terminal C
The contents increase to 1, 2, . . . 19, 20 by counting the count clock C ₂ supplied to . The contents of the counter 542 are supplied to the memory cell 61 as address signals A ₂ to _{A 6} together with the previous address signal A ₁ .

The carry terminal CR of the second counter 542 has
A signal is generated when the contents of the counter 542 reach 20, so this is used as the second carry signal mentioned above.
Let it be C ₃ .

According to the above operation, as shown in FIG. 12, when the memory clock W generates 40 pulses, the second carry signal _C3 is generated, which causes the memory clock W and the count clock to
C ₂ stops.

Finally, the decoder 59 outputs a second counter 542
It inputs address signals A ₂ to _{A 6} which are the outputs of , and generates a carry signal C when it detects that the content of the second counter is 19 or more. The timing of this occurrence is the fall of the 38th pulse of the memory clock W (the fall of the 40th pulse of the write signal _CP1 ).

The connection method when using a plurality of the above integrated circuits is the same as that shown in FIG. FIG. 12 shows the second enable signal F1 and memory signal W1 in the next stage integrated circuit. The enable signal for the next stage integrated circuit is the first stage carry signal C. Address signal A ₁
Since the latch signal CP ₀ and the write signal CP ₁ are the same in the first stage and the next stage and are unrelated to the enable signal, the waveforms are the same in the first stage and the next stage.

Since the carry signal C is set in the flip-flop 58 of the next stage integrated circuit at the falling edge of the address signal _A1 , it is sufficient that C is established as a signal 2t _c after it is generated. Even if it is established within _tc , there is no problem at this time because there is no falling edge of _A1 . In either case, the second enable signal F1 is generated at the falling edge of the 42nd pulse of the write signal _CP1 , and the memory clock W1 is generated by the write signal CP1.
It definitely starts to occur from the 43rd pulse of CP ₁ .

In this integrated circuit, as described above, the write operation starts with a delay of two pulses of the write signal _CP1 , so the number of pulses of the write signal _CP1 must be N+2=122 pulses or more.

According to this embodiment, the delay time of the carry signal C
Since t _d only needs to be within twice the period t _c of the write signal CP ₁ , compared to the embodiment shown in FIG.
The frequency of CP ₁ can be doubled, allowing even higher speed operation.

As described above, according to the present invention, by minimizing the number of output signals that require high-speed response, it becomes easy to improve the operating speed of a data storage device used in a display device, and the cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a display device having a data storage device, FIG. 2 is a diagram showing operating waveforms of the device in FIG. 1, and FIG. 3 is an integrated circuit used in a conventional column electrode drive circuit of a display device. 4 is a connection diagram when a plurality of conventional integrated circuits are used. FIG. 5 is a diagram showing operating waveforms in FIG. 4. FIG. 6 is a diagram showing an integrated circuit according to the present invention. The figure is a connection diagram when using a plurality of integrated circuits of the present invention, FIGS. 8 and 9 are diagrams showing operating waveforms in FIG.
0 is a diagram showing operating waveforms when high-speed operation is performed, FIG. 11 is a diagram showing another embodiment of the present invention, and FIG. 12 is a diagram showing operating waveforms of FIG. 11. 16, 17, 18... integrated circuit, 54, 54
1,542...address counter, 55,56...
...Logic gate, 58...Flip-flop, 59
...Decoder, 61...Memory cell.

Claims (1)

[Claims] 1 A display panel having a plurality of row electrodes and a plurality of column electrodes, a scanning circuit that generates a row electrode signal for scanning the row electrodes, and a display panel that is supplied with a write signal and a serial image data signal, A matrix display device comprising a data storage device that converts a serial image data signal into a parallel image data signal, and a driver that generates a column electrode signal to be supplied to the column electrodes in response to the parallel image data signal. The storage device is divided into multiple stages corresponding to multiple column electrodes, and the data storage device in each stage counts the write signal to generate an address signal, and when the count value reaches a predetermined value. an address counter that generates a second carry signal when a value is reached; a memory cell that writes the serial image data signal to the address indicated by the address signal; and the first carry signal of the preceding address counter that is an enable signal. and a logic gate that supplies the write signal to the address counter and the memory cell to enable counting and writing operations only while the second carry signal is not generated; a decoder that generates a first carry signal to the next stage a predetermined period earlier than the second carry signal by decoding the address signal; A matrix display device comprising: a logic circuit configured to start the operation of the address counter and the memory cell after a lapse of time.