JPS6350888A - Crt controller - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A CRT controller that reads out at least one of color data and attribute data during a horizontal blanking period and uses it for image display.
It is compatible with systems in which image information is transmitted during the horizontal display period, and improves CPU processing efficiency.

[Industrial application field]

The present invention relates to a CRT controller, which sequentially reads image data for one screen from a memory, converts this image data into a video signal, and displays it on a CRT.
Regarding La.

Generally, in an image display system, one screen worth of image data is stored in RAM, the image data is sequentially read out from RAM in accordance with the horizontal synchronization and vertical synchronization of the CRT, and the read image data is converted into a video signal and then transferred to the CRT. Supply and display.

In such an image display system, a CRT controller is provided to read image data for display from RAM,
The CPU is caused to rewrite the RAM and perform other processing to increase the speed at which the display images are changed in the system.

(Prior Art) FIG. 5 shows a system configuration diagram of an example of a conventional image display system. In the figure, a CPU 10 reads image data from a RAM 11 and writes the image data. Also, C
The RT controller (hereinafter referred to as rcRTcJ) has an RA
Image data is read from MII for display. c above
pui o and CRTCl 2 are each multiplexer 13
Either one accesses RAMII via.

The image data for display read out from the RAM 11 is supplied to the video signal generation circuit 14, where it is converted into primary color signals R, G, and B as video signals. Primary colors ff1R,
G and B are supplied to the C display 15 along with the synchronization signal B from the CRTCI 2, and displayed on the CRT 15.

[Problem that the invention seeks to solve]

In the conventional system, the CRTCI 2 accesses the RAM 11 at a predetermined period during the horizontal display period to read image data for display, and the CPU 10 accesses the RAM 11 during the horizontal blanking period and the vertical blanking period to read the 81st part of the image data. We are doing things like

However, for example, in the Captain System 7 system, image information is transmitted according to the scanning period and the blanking period. Therefore, the CPU 10 needs to access the RAM 11 and write image data even during the horizontal display period, which is a problem that cannot be handled by the conventional CRTCl2.

Furthermore, even if a request to access the RAM 11 occurs in CPtJlo, the CPU 10 is forced to wait until the horizontal blanking period and the vertical blanking period to access the RAM 11, resulting in a problem that the processing efficiency of the CPU 10 is poor and access to RAM II is coming soon. There was a point.

The present invention has been made in view of these points, and an object of the present invention is to provide a CRT controller that is compatible with the captain system and improves the processing efficiency of the CPU.

[Means for solving problems]

FIG. 1 shows a block diagram of a CRT controller according to the present invention.

In the figure, 1 represents one display block consisting of color data, attribute data, and a plurality of pattern data.
r! This is a memory in which at least one screen worth of ia data is stored.

The reading means 2 reads out one or both of color data and attribute data of all display blocks in one row in the horizontal direction during one horizontal blanking period per the number of scanning lines of the display block, and reads the color data and attribute data in each horizontal display period. The remaining one of the data and attribute data and the pattern data are sequentially read out by sub-division.

The storage means 3 stores the data read out during the horizontal blanking period for 1' of the horizontal scanning period corresponding to the number of scanning lines of the display block.
Data read out during the horizontal display period is stored for a predetermined period of time, and color data, attribute data, and pattern data are output simultaneously.

The converting means 4 converts the image data of color data, attribute data, and pattern data supplied from the storage means 3 into video signals, and causes the CRT 5 to display the video signals.

〔credit〕

In the present invention, since at least one of the color data and attribute data is read out during the horizontal blanking (1), the time required to access the memory 1 for displaying both images within the horizontal display period is shortened. Also, since at least one of color data and attribute data is read out only once per number of scanning lines of a display block,
The number of accesses to the memory 1 for displaying screen images is significantly reduced.

[Actual drop example]

FIG. 2 shows a block system diagram of an embodiment of a CRT controller according to the present invention. In the figure, a clock generation circuit 30
A system clock signal of the vM image display system is input from the terminal 29 to the terminal 29, and the clock generation circuit 30 generates a clock signal corresponding to two dots on the display screen from the system clock signal, and sends this clock signal to the horizontal counter 31, etc. Supplied to each circuit inside the CRTC.

The horizontal counter 31 counts the clock signal, and the count value is compared with a predetermined value by the horizontal controller 32.
Here, a pulse is generated every horizontal scanning period. This pulse is counted by the vertical counter 33, and the count value is compared with a predetermined value by the vertical controller 34, where 1!
r! Pulses are generated in a direct scan circular scan.

The output pulses of the horizontal controller 32 and the vertical controller 1-0-34 are supplied to a synchronizing signal generating circuit 35 to generate a horizontal synchronizing signal and a vertical synchronizing signal.

The above-mentioned synchronization signal is supplied to an arithmetic and control circuit 36, which will be described later, and the like, and is also supplied to the CRT 5 from terminals 37a and 37b. In addition, when performing superimposed display in which the video generated by this image display system and other video are mixed and displayed, the synchronization signal of the other video is sent to the terminal 37a.
, 37b to the synchronous engine 1 circuit 35, and the CR
TC is synchronized.

The interface circuit 40 connects CPtJ via a terminal 41.
A) is connected to the CPU, and various control signals are received from the CPU.
Various control signals output from the RTC are supplied to the CPU.

Further, data bus 42 and address register/14 are connected to CPtJ via terminals 43 and 45, respectively.

The internal register 46 contains initialization image data and trigger signals that have entered the data bus 42 from the CPU.

The address etc. of the CPU to the memory 1 are stored, and the transfer table 47 contains the image data for writing that comes from the CPU from the data bus 42, and the C
Self-other data etc. supplied to the PU are stored. The internal register 46 and the transfer table 47 constitute the persimmon preservation means 6. A lookup table (hereinafter abbreviated as LUTJ) 48 is a fixed table, and LUTs 49a and 49b are C
This is a table that can be rewritten by PU.

Which of the internal register 46, transfer table 47, and LUTJ9.50 the data, address, etc. entering the data bus 42 is to be supplied to is specified by the address supplied to the address register 44 by the CPU.

Here, image display is performed in units of display blocks. The display block has a first display mode consisting of 4 dots horizontally x 4 dots vertically, a second display mode consisting of 8 dots horizontally x 12 dots vertically, and so on.

The image data is the same as No. 1 above. The second display [1 regardless of - code]
11-byte 8-bit pattern data in which each bit represents 1 dot; 1-byte 8-bit color data in which 4 bits each represent foreground color and background color; and attributes such as underline display and 1 underline display. It consists of 1 byte and 8 bits of attribute data representing the . In addition, in the first display mode, 1 byte of pattern data is data for 1 line of 2 display blocks, and in the 1st display mode, 4 bits for each byte of 4 bytes of pattern data are used for 1 display block. ] is displayed, and in the second display mode, one display block is displayed with 12 bytes of pattern data.

The memory access timing controller 50 includes a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and a horizontal controller 32 . It is supplied with the output pulses of the vertical controllers 1 and 34, and is also supplied with a display mode control signal from the internal register 46.
A control signal for controlling writing/reading is supplied to the read/write controller 51, a control signal for varying the address value of the memory 1 is supplied to the address counter and limiter 52, and a control signal for transfer t++m is supplied to the transfer control circuit. 5
Supply to 3.

The read/write controller 51 generates a read enable signal at the time of reading and a write enable signal at the time of writing, and supplies them to the memory 1 from the terminal 54. Also,
The address output from the address counter and limiter 52 is converted by an address controller 55 into a format for accessing the memory 1 and is supplied to the memory 1 from a terminal 56.

This is because the format of the address differs depending on whether a dynamic RAM or a static RΔ~1 is used as the memory 1.

The horizontal controller 32, the vertical miller 34,
Internal register 45, memory access timing controller 50, read/write controller 511, address counter and limiter 52, address controller 5
5 constitutes the reading means 2.

Further, image data read out from the memory 1 for display is supplied from a terminal 58 to a buffer 59 which is the storage means 3, and pattern data, color data, and attribute data are sent to a pattern buffer 59a, a color buffer 59b, and an attribute buffer 59c, respectively. are stored separately. The calculation and control circuit 36 receives the pattern data, color data, and attributes 1 to 1 supplied from the buffer 59.
Performs zero processing on the data, and colors in dot units:, -
code data is generated and supplied to the selector 60.

The selector 60 changes the color code data to red using a table selected by an instruction from the internal register 40 behind the LUTs 48, 49a and 49b.

The data is converted into 412-bit primary color data using 4 bits each for green and front, and is supplied to the D/Δ conversion circuit 61.

The D/A conversion circuit 61 receives Ab [l] supplied from the terminal 62.
The above primary color data is D/Δ converted into analog primary color signals R, G, B using the power source for
The image is supplied to the RT 5 and displayed on the CRT 5.

LUTs 48 to 49b above.

Bad 7?59. Performance and control circuit 36. selector 60,
The conversion means 4 is constituted by the D/A conversion circuit 61.

FIG. 3 shows a detailed block system diagram of an embodiment of the essential parts of the CRT controller. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals.

In FIG. 3, a clock signal ga shown in FIG. 4 (△) enters the horizontal counter 31 from the terminal 70, the horizontal counter 31 counts this clock FQa, and the count value is sent to the horizontal controller 32. supply to. In addition,
Two dots are displayed on the display screen in one period of the clock signal a.

When the count value reaches a period corresponding to one horizontal scanning period, the horizontal controller 32 generates a horizontal clear signal to clear the horizontal counter 31, and in the first display mode, as shown in FIG. 4<8), (C).

(D), (E) Timing signal shown to people c.

d and a timing signal e. timing signal b
This is a signal that outputs the Gma Bakoon address.
It is generated every eight clock cycles during the horizontal display period, and its pulse width is one clock cycle. The timing signal Qc is a signal for instructing the output of a color address, and rises one clock period after the rising edge of the timing signal Qc, and has a pulse width of two clock cycles, 1g1. timing signal d
is a signal instructing the output of 71~review address, which rises to L level during the horizontal display period and 1-level during the horizontal blanking period, and has a pulse width of 34 [13th of the microphone period]. The timing signal e is the same signal as the timing signal a and instructs the output of pattern, color, and trivial data.

Furthermore, the horizontal controller 32 generates a pulse with a horizontal scanning period and supplies it to the synchronization signal generation circuit 35 from the terminal 71.

Note that the timing signal q starts from the falling edge of the timing signal S.
During the period until the rise of c, a timing signal similar to the timing signal for reading out the pattern data of the next raster when smoothing is performed 11 times is output.

The horizontal clear signal output from the horizontal controller 32 is supplied to a vertical counter 33, which counts this horizontal clear signal and supplies its curran l-value to the vertical controller 34.

When the count value reaches a value corresponding to one vertical scanning period, the vertical controller 34 generates a vertical clear signal to clear the vertical counter 33, and also generates a pulse corresponding to the vertical scanning period and sends it from the terminal 72 to the Domei signal generation circuit 35. supply cover.

Further, the horizontal clear signal is supplied to a raster counter 73 that constitutes the memory access timing controller 50, and the raster counter 73 counts the horizontal clear signal and supplies the count value to the raster decoder 74. In the first display mode, the raster decoder 74 generates a Goo 1- signal at H level during the period when the count value is "3" and supplies it to the AND circuit 75, and also supplies it to the AND circuit 75 when the count value is "4".
”, a raster clear signal is generated and supplied to the clear terminal CLRI of the raster counter 73.

Further, a vertical clear signal is supplied to the clear terminal CLR2 of the raster counter 73. As a result, the raster counter 73 is cleared to rOJ before the start of vertical scanning, and thereafter cleared to "0" in the fourth horizontal scanning period IIto.

The AND circuit 75 is supplied with the timing signal d output from the horizontal controller 32, and the gate circuit 75
When J3 is in the first display mode and the count value of the raster counter 73 is "3", the timing signal F is sent during the horizontal blanking period immediately after the last fourth rask of the display block is displayed.
'3d is taken out and output as a timing signal f.

The timing signal C output from the horizontal controller 32 is supplied to the pattern star 1 to address register 76 in the internal register 46 and the pattern buffer 59a via the memory access timing controller 50, and the timing signal C is supplied to the memory access timing controller 50.
is supplied to the color start address register 77 and the color buffer 5b via the color buffer 5b. The timing signal e is supplied via the memory access timing controller 50 to the pattern buffer 59a, color buffer 59b, and attribute buffer 7590, respectively. Also, the AND circuit 75 of the memory access timing controller 50
The timing signal f outputted by the attribute start address register 78 and the attribute buffer 75
Supplied to 9C. The Bakun start address register 76, the color start address register 77, and the attribute start address register 78 each transfer the stored star 1 to address to the address counter and limiter 52 at the rising edge of the supplied timing signals S, C, and F, respectively. Address counter 80 in []-
3, the address counter 80 increments the address value by the clock signal a supplied from the terminal 81. The signal is then supplied from the terminal 82 to the address controller 55 shown in the second figure, where it is configured to access the memory 1 and is supplied to the memory 1.

Memory 1 has approximately 7 bytes of pattern data area.

A byte color data area is set at approximately 0.35, and a byte attribute area is set at approximately 0.35 according to the address of J3. One address writes/reads 2-byte 16-bit data. Do the following.

The pattern data, color data, and attribute data read out from the memory 1 according to the output address value of the address counter 80 are shown in FIG.
759a via the data bus 83.
, color buff? 59b and 59c, respectively.

The pattern buffer 59a latches the pattern data of 2 bytes and 4 display blocks that arrive during the period of the timing signal C, and outputs the performance 0 and control data shown in the second figure from the terminal 84a during the 1'' level period of the timing signal C. 01+circuit 3
Supply to 6. The color buffer 59b latches the 4-byte color data for 4 display blocks that come during the H level period of the timing signal C, 2 bytes per clock cycle, and outputs the color data 1 byte at a time to the terminal during the F'' level period of the timing signal e. 84b to the input q and control circuit 36.

The attribute buffer 759C wraps 7 tribute data for 68 bytes and 68 display blocks that enters between trubel 1:g1 of the timing signal f, and transfers the data from the terminal 84c to the (b) and the control circuit 36.

By the way, one period of clock signal a is approximately 350 nsec.
The memory cycle of memory 1 is approximately 350 nsec. Furthermore, one horizontal display period on the CRT display screen is 1
With 36 clock periods, the horizontal blanking period is 46 clock periods, the vertical display period is 204 horizontal scan periods, and the vertical blanking period is 58 horizontal scan periods.

In the first display mode, 34 bytes of pattern data, 68 bytes of color data,
It is necessary to read 68 bytes of attribute data, a total of 170 bytes, from the memory 1, and if further smoothing is to be performed, a total of 204 bytes are required. Therefore, if memory 1 is 17 addresses and 1 byte is 8 bits read/interfered, 1 horizontal scanning period is 182 [cock period (, 1 smoothing cannot be done ()), so memory 1 is 1 address Read 2 bytes 16 bits with /
It is configured to perform fortune telling.

Also, out of the horizontal display period of 136 clock cycles, 17
34 bytes of pattern data are read out in one clock cycle, 68 bytes of color data are read out in 34 clock cycles, and attribute l-data is read out during the horizontal blanking period. Therefore, the remaining 85 clock periods of the horizontal display period can be used by the CPU.

In addition, in the fourth edition (C), the memory 1 is
It is also possible to read out different image data to generate a video signal different from the above-mentioned video signal, and to switch between the two systems of video signals to display two types of images in a switched manner.

Also, if attribute data is read out for each line, 13872 data will be read per screen in the first display mode.
(=68x204> bytes of attribute data must be read. However, in the above example, the attribute data is read during the horizontal blanking period for every t14 line, so 3468 bytes of attribute data are read per screen.) Therefore, the number of accesses to memory 1 can be reduced to 25% of the above number, that is, 1734 times.

Note that when the CPU loads image data into the memory 1, information such as the write address and the number of transferred words outputted by the CPU is supplied from the data bus 42 to the read address register in the internal register 46 and stored. Image data for writing is supplied to the transfer table 47 via the data bus 42 and stored therein, and furthermore, a trigger signal instructing the CPU to start access is supplied to the internal register 46 via the data bus 42 and stored therein.

Due to the input of the trigger signal, the memory access timing controller 50 reaches timing 4i 8 b.

Generates a write timing signal that becomes a trubel when all c and f are at L level, loads the address of the read address register into the address counter 80 when the write timing signal g is at L level, and increments it at a clock cycle. !7 is supplied to memory 1 for the 23 Q-inclusive address.

Before this, the read/write controller 54 Lt
In response to a control signal from the memory access timing controller 50, a read l-enable signal is supplied to the memory 1 from the terminal 54. In addition, the image data in the transfer table 47 is sequentially supplied to the transfer control circuit 53 every one cycle, and the image data selected here is sent to the switching circuit 61. The read/write switching circuit 61 is set to the write mode in response to the aill til 1ffi signal from the read/write controller 51, and supplies the image data "-" to the memory 1 from the terminal 58.

As a result, image data from the CPU is sequentially loaded into the memory 1 even during the horizontal display period.

Note that when image data of the same number of words as the number of transferred words is transferred to or read from the memory 1, the memory access timing controller 50 strongly sets the read/write timing signal 8 to L level, and this This causes the CPU to stop writing and reading from memory 1.

In this way, CI)U can supply the write address and read data of memory 1 to the CRTC when an access request for memory 1 is generated, and can perform the process of retransmission, improving the processing efficiency of the CPU. do. Further, since the CPU writes or reads data from the memory 1 during the horizontal display period, writing or reading is performed at high speed, and the use efficiency of the data bus and address bus between the CRTC and the memory 1 is improved. Furthermore, the configuration of the image display system can be simplified without requiring a circuit such as a multiplex display.

〔Effect of the invention〕.

As described above, according to the present invention, within the horizontal display period, the CPU
It is possible to load image data into the memory, to support the captain system, to improve the processing efficiency of the CPU, and to access the memory at high speed.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the CRT controller 1 to roller of the present invention, FIG. 2 is a block diagram of an embodiment of the CRT controller of the present invention, and FIG. 3 is a partial block diagram of the CRT controller shown in FIG. 1. FIG. 4 is a time chart of signals of various parts of the circuit shown in FIG. 3. FIG. 5 is a block diagram of an example of a conventional double edge display system. In the figure, 1 is a memory, 2 is a readout (stage), 3 is a storage means, 4 is a conversion means, 5 is a CRT, 46 is an internal register, 47 is a transfer table, 50 is a memory access timing controller, 51
is a read/write controller, 52 is an address counter and limiter, 53 is a transfer control circuit, 55 is an address controller, 57 is a read/write switching circuit, 61 is a D/A conversion circuit, 73 is a raster counter, 74 is a raster 76 is a pattern start address register, 77 is a color start address register, and 78 is an attribute address register. Honsai Yuzuki Harao! , Brotsu 7ff1 Character 1 Figure 1F73 Illustrated times 6 cheat fortune telling 4ν, eyebrow number η 24 M 2 Tweet happy 4 figure middle East f) 10 East 1 (Kin system 4Q7゛口・y2 工91
Figure 5

Claims (1)

[Claims] A memory in which at least one screen worth of image data representing one display block including color data, attribute data, and a plurality of pattern data is stored is sequentially accessed according to horizontal synchronization and vertical synchronization, and C converts the read image data into a video signal and displays it on a CRT
In the RT controller, one or both of the color data and attribute data of all display blocks in one row in the horizontal direction is read out during one horizontal blanking period for each scanning line number of the display block, and the above data is read out in each horizontal display period. reading means for sequentially reading out the remaining one of the color data and the attribute data and the pattern data in a time-sharing manner; and storing the data read out during the horizontal blanking period for a period of a horizontal scanning cycle equal to the number of scanning lines of the display block. A CRT controller characterized in that it has storage means for storing data read out during the horizontal display period for a predetermined period and simultaneously outputting the color data, attribute data, and pattern data.