JPS6350068A - Thin film transistor substrate - Google Patents

Abstract

PURPOSE:To make it possible to repair the disconnection of a gate electrode in a pattern at the same time of forming an electrode of display pixels, and prevent line defects at the time of display, by forming a gate electrode with two layers, one of which is made of the same material as the electrode of display picture elements. CONSTITUTION:A passivation film 2 and a semiconductor layer 3 are continuously deposited on a glass substrate 1, and the layer 3 only is subjected to patterning to form a desired semiconductor layer 3a. After a source electrode 4 and a drain electrode 5 are formed by vapor deposition of metal, a gate insulating film 6 is deposited. Another vapor deposition if Al and the like is done, a gate electrode 7 of a first layer is formed, and a contact hole 8 is formed. After that, the pattern of the gate electrode 7B of a second layer is formed. In this case, by dipping the diposited substrate in a resist parting agent applying a lift-off method, and exfoliating ITO in unnecessary parts together with the resist, the pattern of an electrode 9 of display pixels and the electrode 7B are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor substrate in which a large number of thin film transistors (TPTs) are arranged near intersections of matrix electrodes.

[Prior Art] Recently, flat displays have been actively developed in response to demands for office automation equipment terminals, portable televisions, and the like. Among these, in information display devices in which electrodes are arranged in rows and columns in order to accommodate large-capacity graphic displays, an active matrix system is being researched in which active elements are arranged at the intersections of the electrodes for driving. FIG. 2 shows a conceptual diagram of a liquid crystal panel display using a thin film transistor (TPT) as a thin film active element. 11 is a liquid crystal layer, and 12 is a switching TPT for driving the liquid crystal layer. 13 is a data line for applying a voltage necessary to drive the liquid crystal, and 14 is a selection signal line for suppressing the gate of the TFT 12. 15 and IC are transparent electrodes. FIG. 3 shows a plan view of a TPT having a conventionally known coplanar structure. 3a in the figure is a semiconductor layer made of amorphous silicon (a-3i), etc.
0 indicates the source line, and 4 indicates the source electrode of each TPT. These are made of metal such as AI. 7 is the gate electrode and gate line, which is connected to AI like the source electrode.
It is made of metals such as Reference numeral 8 denotes a contact hole, which is opened to insulate the source electrode 4 and the gate line 7, and which connects the drain electrode 5, the display electrode 5, and the display pixel electrode 9.
It is for connecting with. The display pixel electrode 9 is I
TO(I n203-8n02).

It is formed from a transparent conductive thin film such as 5n02.

[Problems to be solved by the invention] As mentioned above, the use of TPT makes it possible to display high-density information with good visibility, but since at least one TPT is required for each pixel, It is extremely difficult to produce a large number of TPTs without defects. For that reason T
It is necessary to simplify the PT manufacturing process as much as possible, and to suppress the occurrence of defects during the process as much as possible. In addition, despite such consideration, there is a problem in that the wiring pattern may be disconnected due to fine dirt, dust, etc. during the process. If the wiring is disconnected in this way, it will cause a line defect on the display, lowering the display quality and causing the device to lose its value as an information display device. This reduces the yield of information display devices and results in a cost difference compared to the conventional simple matrix method, posing a problem in the practical use of information display devices using thin film transistors.

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and includes forming a source electrode and a drain electrode on an insulating substrate, and further forming a source electrode and a drain electrode on the insulating substrate via an insulating film. Provided is a thin film transistor substrate in which a thin film transistor on which a gate electrode is formed is provided for each display pixel, characterized in that the gate electrode has two layers, one of which is made of the same material as the display pixel electrode. .

Furthermore, in the present invention, when forming the display pixel electrode and second layer gate electrode patterns, the patterns are formed not by the etching method but by the lift-off method.

The present invention can be applied to a thin film transistor having a structure in which a source electrode and a drain electrode are formed on an insulating substrate such as glass or plastic, and a gate electrode is formed thereon through an insulating film, and the gate electrode is arranged on the upper side. All you have to do is stay there. Note that the present invention can also be applied to a double-gate thin film transistor in which the gate electrode is divided into two parts and is also formed on the substrate side.

For the semiconductor layer of this thin film transistor, known materials such as amorphous silicon, polysilicon, and CdSe are used.

In the present invention, the gate electrode on this layer is made of two layers, and one layer and the display pixel electrode are formed of the same material. It is something that forms. By patterning this transparent conductive thin film using the lift-off method, it is possible to easily create a two-layer gate electrode, and even if there is a break in the first layer gate electrode, this defect can be prevented by the second layer gate electrode. This improves manufacturing yield. In particular, since the gate electrode of the first layer and the display pixel electrode are patterned and patterned in the same process, it also has the advantage that the number of manufacturing processes is not increased.

A brief explanation of the lift-off method will be added here.

As shown in FIG. 4, prior to depositing any thin film on the substrate 21, a fourth
A resist 22 is applied onto the substrate as shown in FIG. 4(a), and exposed as shown in FIG. 4(b) to form a desired resist pattern 22.
form a. After this, as shown in FIG. 4(c), the thin film 23a is
, 23b are deposited by a conventional CVD method, PVD method, or the like. Thereafter, as shown in FIG. 4(d), the substrate is immersed in a resist stripping solution to strip the resist and at the same time, the thin film on the resist is also stripped. At this time, it is desired that the patterned resist pattern 22a has an inversely tapered shape from the viewpoint of releasability. According to this method, it is possible to pattern a thin film on a substrate without immersing the substrate in an etching solution. As a result, a pattern can be formed without worrying about the interaction between the etching solution and the material constituting the pattern that has already been formed.

In addition, as mentioned above, the lift-off method removes the thin film on the resist together with the resist, so it is generally desirable that the part where the thin film remains is smaller than the part to be peeled off, so use the method according to this ratio. All you have to do is decide the type of resist you want to use.

FIG. 1 shows a procedure for manufacturing a thin film transistor according to the present invention, taking a coplanar structure as an example. A passivation film 2 and a semiconductor layer 3 are successively deposited on a substrate 1 such as a glass substrate by a p-CVD method (a). Thereafter, only the semiconductor layer is patterned to form a semiconductor layer 3a having a desired shape (b). Thereafter, a metal such as AI is deposited by EB deposition or the like and patterned to form a source electrode 4 and a drain electrode 5 (c). After this, a gate insulating film 6 is deposited by p-CVD method (d).

AI or the like is deposited again and patterned to form the first layer gate electrode 7 (e). Next, a contact hole 8 for connecting the drain electrode 5 and the display pixel electrode is opened (f).

After this, a pattern for a display pixel electrode and a second layer gate electrode 7B for double wiring is formed. This second layer gate electrode and display pixel electrode are usually ITO, 5n0
It is said to be a transparent conductive thin film of the second class, but it is a guest-host type LC.
In the case of D, etc., it can be made of chromium, aluminum, etc., and furthermore, it can also have a two-layer structure of a reflective metal such as chromium, aluminum, etc. and a transparent conductive thin film.

In this case, it is preferable that the second layer gate electrode and the display pixel electrode are patterned at the same time.
Although the lift-off method can be used, it is preferable from the viewpoint of reliability of the lift-off method.

To explain the case of forming using the lift-off method, first, a negative resist is applied to a substrate and exposed to light to form a resist pattern that is an inversion of the desired pattern. Thereafter, ITO for forming both electrodes is formed by EB evaporation or the like in an oxygen atmosphere. The vapor-deposited substrate is immersed in a resist stripping solution and unnecessary portions of ITO are stripped off together with the resist, thereby forming patterns for display pixel electrodes 9 and gate electrode portions 7B (g).

In the above explanation, we have only given an example of a negative type resist due to the balance between areas where the transparent conductive thin film ITO is left unpeeled and areas where it is not, and this method is not limited to negative type resists. There is no problem even if it is a positive type resist. In addition, in this explanation, ITO is used as the transparent conductive thin film, but this is not limited to ITO, and is not particularly limited as long as it is known as a transparent conductive thin film.

[Function] According to the thin film transistor substrate of the present invention, the defect of gate electrode disconnection contained in the already formed pattern is repaired at the same time as the display pixel electrode is formed, and the display can be performed without the need for a new process. It is possible to prevent line defects that are sometimes seen. This prevents an increase in production costs due to a decrease in manufacturing yield, and makes it possible to realize an information display device using TPT.

Furthermore, according to the method of the present invention, TPT can be formed more easily than in pattern formation of a transparent conductive thin film by conventional etching or the like.

The present invention is applicable to devices in which substrates on which electrodes are arranged are arranged so that the electrode surfaces face each other, and an electro-optic medium is sandwiched between them, such as liquid crystal display elements, electrochromic display elements, electrophoretic display elements, etc. .

[Embodiments] Examples of thin film transistor substrates using double wiring according to the present invention will be described below in the case of a TPT having a coplanar structure.

The structure and manufacturing process of TPT uses a glass substrate, and A is used for the source electrode, drain electrode, and first layer gate electrode.
Q was used, and the same structure and process as those shown in FIG. 1 described above were carried out.

Separately, as a sample for comparison, the gate electrode was
(A substrate was formed using a conventional process with only 21 layers.

A 50 mm square substrate was used as the substrate, and 2500 TPTs (50×50) were formed at a pitch of 800 μm. The thickness of each thin film constituting the TPT is as follows: the pad version film is 200 OA, the a-3i layer as a semiconductor layer is 3000 OA, the source and drain electrodes are 4000 OA, and the gate insulating film is 25 OA.
00 people, and 8000 people for the first layer gate electrode. Also,
The transparent conductive thin film used this time was ITO, and its thickness was 15
00 people. The number of substrates formed by each process was 10, and the processes were evaluated based on the shape of the TPT portion of each substrate, the resistance value of the metal wiring, etc.

In the conventional method, that is, in which the gate electrode was wired using a single layer of AQ, four disconnections, which were thought to be caused by dust, were observed in 10 substrates. On the other hand, not a single disconnection was observed on the board with two-layer wiring using the present method.

However, in the results of the resistive disconnection test, a deviation from the average resistance value of five of the 10 boards was observed. As a result of detailed observation of these wiring lines with different resistance values, we observed disconnection of the AQ of the first layer gate electrode in all lines, but it was confirmed that they were all connected by the ITO of the second layer wiring. It was done. The new process also resulted in almost no increase in the defect rate. Furthermore, no significant difference was observed in the transistor characteristics of the portion connected only in the second layer compared to the normal portion.

[Effects of the Invention] With the thin film transistor substrate of the present invention, it is possible to have two layers of wiring without increasing the number of processes.
The present invention is intended to reduce the high cost associated with the low yield of information devices using thin film transistors as switching elements, which has been a problem in the past, without changing the process.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the procedure for creating a TPT according to the present invention. FIG. 2 is a partially cutaway perspective view of a liquid crystal panel display using TPT. FIG. 3 is a plan view of the coplanar structure TPT. FIG. 4 is a sectional view illustrating the lift-off method. 1: Substrate, 2: Passivation film, 3: Semiconductor layer, 4: Source electrode, 5 Ni-drain electrode, 6: Gate insulating film, 7: Gate electrode, 7A: First layer gate electrode, 7B: Second layer gate Electrode, 8: Contact hole, . , -:2 m 7818- Agent inside Takuya 1121 '♀ + District procedure amendment October 1, 1986

Claims (4)

[Claims] (1) In a thin film transistor substrate in which a thin film transistor is provided for each display pixel, in which a source electrode and a drain electrode are formed on an insulating substrate, and a gate electrode is further formed thereon through an insulating film, the gate electrode is formed in two layers, A thin film transistor substrate characterized in that one layer thereof is made of the same material as a display pixel electrode. (2) The thin film transistor substrate according to claim 1, wherein one layer of the gate electrode and the display pixel electrode are formed of a transparent conductive thin film. (3) The thin film transistor substrate according to claim 2, wherein the transparent conductive thin film is patterned by a lift-off method. (4) The thin film transistor substrate according to any one of claims 1 to 3, wherein the thin film transistor is a coplanar thin film transistor.