JPS634941B2 - - Google Patents
Info
- Publication number
- JPS634941B2 JPS634941B2 JP57026124A JP2612482A JPS634941B2 JP S634941 B2 JPS634941 B2 JP S634941B2 JP 57026124 A JP57026124 A JP 57026124A JP 2612482 A JP2612482 A JP 2612482A JP S634941 B2 JPS634941 B2 JP S634941B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- solder
- solder foil
- silicon
- separated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000011888 foil Substances 0.000 claims abstract description 22
- 239000008188 pellet Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000000155 melt Substances 0.000 claims description 2
- 238000010309 melting process Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 34
- 229910052710 silicon Inorganic materials 0.000 abstract description 34
- 239000010703 silicon Substances 0.000 abstract description 34
- 238000002844 melting Methods 0.000 abstract description 10
- 230000008018 melting Effects 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 8
- 238000005520 cutting process Methods 0.000 abstract description 7
- 229910052759 nickel Inorganic materials 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000010419 fine particle Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000005453 pelletization Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に、半導体
ウエハ状態で半導体ペレツトとなる部分にはんだ
電極を形成しておき、半導体ウエハを切断して
固々の半導体ペレツトを得る製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, in which a solder electrode is formed in a portion of a semiconductor wafer that will become a semiconductor pellet, and the semiconductor wafer is cut to obtain solid semiconductor pellets. It is about the method.
従来、半導体ペレツトへはんだ電極を形成させ
る方法として、第１図から第３図に示すように、
まずpn接合を形成するための拡散等の工程が終
了したシリコンウエハ１の両面にニツケル層２を
設け、両面にシリコンウエハ１と同径のはんだ箔
３を塔載して還元性雰囲気、例えば水素雰囲気中
で加熱して一様に溶融接合させてから第２図のよ
うに格子状にスクライビングしてペレツト化して
いた。第３図はペレツト化されたシリコンペレツ
ト１ａの断面を示すものであるが、スクライビン
グ時にはんだ微分３ａが付着したり、切断部に歪
層が生ずるので、このままでは基板へボンデイン
グしても耐圧特性への悪影響があつた。このため
ペレツト化されたシリコンペレツトの側面付着物
と切断歪層をエツチング等で除去する工程が必要
である。しかしエツチング液残渣の有無の確認が
困難であると同時に、はんだ表面が汚れることか
らボンデイング不良、特に接合部にボイドが発生
するなどの問題が生じたり、はんだ箔３を接着さ
せたシリコンウエハ１をペレツト状にスクライビ
ングするのにかなりの時間が必要であるなど歩留
り上の問題も生じていた。 Conventionally, as a method for forming solder electrodes on semiconductor pellets, as shown in FIGS. 1 to 3,
First, a nickel layer 2 is provided on both sides of a silicon wafer 1 that has undergone processes such as diffusion for forming a p-n junction, and solder foil 3 having the same diameter as the silicon wafer 1 is placed on both sides in a reducing atmosphere, such as hydrogen. They were heated in an atmosphere to uniformly melt and bond, and then scribed in a grid pattern as shown in Figure 2 to form pellets. Figure 3 shows a cross section of the pelletized silicon pellet 1a, but since the solder differential 3a adheres during scribing and a strained layer is generated at the cut portion, the breakdown voltage characteristics will be poor even when bonded to a substrate. There was a negative impact on For this reason, it is necessary to remove the deposits on the side surfaces of the pelletized silicon pellets and the cut strain layer by etching or the like. However, it is difficult to confirm the presence or absence of etching solution residue, and at the same time, the solder surface becomes dirty, leading to problems such as defective bonding, especially voids at the joint, and the silicon wafer 1 to which the solder foil 3 is attached. Yield problems also arose, such as the considerable time required to scribe into pellets.
本発明の目的は、ペレツト化するためのはんだ
電極部の切断による歪やはんだ微粉の付着を生ず
ることがなく、電気特性不良が起きない半導体装
置の製造方法を提供するにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause distortion or adhesion of solder fine powder due to cutting of solder electrode portions for pelletizing, and does not cause defective electrical characteristics.
本発明製造方法の特徴とするところは、還元性
雰囲気中で半導体ウエハに仮付け固定したはんだ
箔と半導体ウエハをダブルビーム熱源線を用い
て、先ず、はんだ箔を溶融分離させる熱源線を走
らせ、次に、半導体ウエハを溶融切断する熱源線
を走査させることにある。 The manufacturing method of the present invention is characterized by first running a heat source line that melts and separates the solder foil and the semiconductor wafer using a double-beam heat source line between the solder foil temporarily fixed to the semiconductor wafer and the semiconductor wafer in a reducing atmosphere. The next step is to scan the heat source line for melting and cutting the semiconductor wafer.
以下、本発明の一実施例を第４図〜第７図によ
り説明する。 An embodiment of the present invention will be described below with reference to FIGS. 4 to 7.
第４図は、本発明のダブルビームレーザ光線装
置で半導体ウエハ上の仮付けはんだ箔と半導体ウ
エハを溶融分離、溶融切断する方法の説明図であ
る。 FIG. 4 is an explanatory diagram of a method for melting and separating and melting and cutting the temporary solder foil on a semiconductor wafer and the semiconductor wafer using the double beam laser beam apparatus of the present invention.
第５図は、ダブルビームレーザ光線装置と走査
方法との構成図である。 FIG. 5 is a configuration diagram of a double beam laser beam device and a scanning method.
両図に示すように、予め表面保護膜としてガラ
ス４、SiO24aを有し複数個のペレツトに分離さ
れ、表面に金属電極膜６、例えばNi，Cr―Ni―
Ag膜を有するシリコンウエハ１の両面に、前記
シリコンウエハ１と同等の外形寸法のはんだ箔５
（例えばPb―５％Sn―1.5％Agはんだ）を還元性
雰囲気中で加熱して仮付け固定したシリコンウエ
ハ１を、ダブルビームレーザ光線の一方のレーザ
光線１０で前記シリコンウエハ１上に仮付け固定
したはんだ箔５のみを溶融分離するように、矢印
にて示す如く走査させる。ついで他方のレーザ光
線８で溶融分離した間隙部からシリコンウエハ１
上のガラス４、シリコンウエハ１を溶融切断する
ように走査させることにより、前記シリコンウエ
ハ１上のはんだ箔５を複数個のシリコンペレツト
形状に分離し、シリコンウエハの状態でシリコン
ペレツトのはんだ電極を一括形成する。尚、１
ｂ，５ａは溶断部である。 As shown in both figures, the pellets are separated into a plurality of pellets with glass 4 and SiO 2 4a as a surface protection film, and a metal electrode film 6 such as Ni, Cr-Ni-
Solder foils 5 having the same external dimensions as the silicon wafer 1 are placed on both sides of the silicon wafer 1 having the Ag film.
A silicon wafer 1 which is temporarily fixed by heating (for example, Pb-5%Sn-1.5%Ag solder) in a reducing atmosphere is temporarily fixed onto the silicon wafer 1 using one laser beam 10 of a double beam laser beam. Scanning is performed as shown by the arrows so that only the fixed solder foil 5 is melted and separated. The silicon wafer 1 is then melted and separated by the other laser beam 8.
The solder foil 5 on the silicon wafer 1 is separated into a plurality of silicon pellet shapes by scanning the upper glass 4 and the silicon wafer 1 so as to melt and cut them. Form electrodes all at once. Furthermore, 1
b and 5a are fusing parts.
前記方法は、第５図に示すように、シリコンウ
エハ１上のはんだ箔５、ガラス４とシリコンウエ
ハ１の一部１ｂを、溶断が可能であるように、ビ
ーム光線１０，８の出力調整は、はんだ箔溶融分
離するビーム径は少なくてもシリコンウエハ１を
溶融切断するビーム径よりも大きくし、ビーム先
端がシリコンウエハ１のガラス４に接しない程度
に、ビーム発振装置１２，１３で調整できるよう
な装置によると容易に目的が達成できる。またビ
ーム光線８，１０のヘツド７，９が一体となつた
機構１１にすることにより高精度、高能力ではん
だ電極が形成できる。前記の溶融分離、溶融切断
を行う場合、レーザ光線ヘツド７，９の移動、あ
るいはシリコンウエハ１のホルダーの移動など、
いずれの方式でも本目的は達成し得るものであ
る。 In this method, as shown in FIG. 5, the output of the beams 10 and 8 is adjusted so that the solder foil 5 on the silicon wafer 1, the glass 4, and the part 1b of the silicon wafer 1 can be melted. The beam diameter for melting and separating the solder foil is at least larger than the beam diameter for melting and cutting the silicon wafer 1, and can be adjusted by the beam oscillation devices 12 and 13 to such an extent that the beam tip does not touch the glass 4 of the silicon wafer 1. With such a device, the purpose can be easily achieved. Furthermore, by forming the mechanism 11 in which the heads 7 and 9 of the beams 8 and 10 are integrated, solder electrodes can be formed with high precision and high performance. When performing the above-mentioned melting separation and melting cutting, there are various steps such as moving the laser beam heads 7 and 9 or moving the holder of the silicon wafer 1.
This objective can be achieved using either method.
第６図は、ダブルビームレーザ光線でペレツト
形状にスクライビングされたシリコンウエハ１の
断面構造図である。シリコンウエハ１の下面にも
ダブルビームレーザ光線を本発明に従つて走査し
ている。 FIG. 6 is a cross-sectional structural view of a silicon wafer 1 scribed into a pellet shape with a double beam laser beam. The lower surface of the silicon wafer 1 is also scanned with a double beam laser beam according to the present invention.
ダブルビームレーザ光線を走査させた場合、シ
リコンウエハ１に仮付け固定されたはんだ箔５
は、先行走査するビーム光線で局部的に溶融さ
れ、表面張力によつてペレツトの金属電極６側に
集つてはんだ溶断部５ａのようになり、はんだ電
極間に間隙が生ずる。この間隙を通して追従する
ビーム光線が走査することにより、前記はんだ箔
５を溶融切断することによるガラス４など表面保
護膜へのはんだ溶着が生ずることなく、スクライ
ビングができる。 When the double beam laser beam is scanned, the solder foil 5 temporarily fixed to the silicon wafer 1
is locally melted by the preceding scanning beam, and due to surface tension, gathers on the metal electrode 6 side of the pellet to form a solder fusion portion 5a, creating a gap between the solder electrodes. By scanning the following beam through this gap, scribing can be performed without causing solder welding to the surface protective film such as glass 4 due to melting and cutting of the solder foil 5.
第７図は、上記の工程で得たシリコンペレツト
１ｃを導電リード１４に組込んではんだ電極によ
りボンデイングした状態の断面構造図である。 FIG. 7 is a cross-sectional structural view of the silicon pellet 1c obtained in the above process incorporated into the conductive lead 14 and bonded with a solder electrode.
本発明製造方法によれば、第７図のように、シ
リコンペレツト１ｃ側面にはんだ微粉やエツチン
グ液残渣の付着はなく、従つて電気特性上の問題
もなく、接着はんだ部５ｂの厚さのばらつきも発
生しないので高信頼性の半導体装置を高歩留りで
得ることができる。 According to the manufacturing method of the present invention, as shown in FIG. 7, there is no adhesion of solder fine powder or etching solution residue to the side surface of the silicon pellet 1c, and therefore there is no problem with electrical characteristics, and the thickness of the adhesive solder portion 5b can be reduced. Since no variations occur, highly reliable semiconductor devices can be obtained at a high yield.
なお、ダブルビームレーザ光線の代りの熱源線
として、ダブルの電子ビームも可能であり、はん
だを分離する側の熱源としてアーク、光ビーム等
を組合わせることは可能である。 Note that a double electron beam can be used as a heat source instead of a double beam laser beam, and it is also possible to combine an arc, a light beam, etc. as a heat source for separating the solder.
第１図〜第３図は従来の半導体装置の製造方法
を工程毎に示す図、第４図〜第７図は本発明の半
導体装置の製造方法の一実施例を工程毎に示す図
である。
１…シリコンウエハ、１ａ，１ｃ…シリコンペ
レツト、１ｂ…溶断部、２…ニツケル層、３，５
…はんだ箔、３ａ…はんだ微粉、４…ガラス、５
…はんだ箔、５ａ…溶断部、５ｂ…接着はんだ
部、６…金属電極膜、７，９…レーザ光線ヘツド
部、８，１０…レーザ光線、１１…一体機構、１
２，１３…ビーム発振装置、１４…導電リード。
1 to 3 are diagrams showing each step of a conventional semiconductor device manufacturing method, and FIGS. 4 to 7 are diagrams showing each step of an embodiment of the semiconductor device manufacturing method of the present invention. . DESCRIPTION OF SYMBOLS 1...Silicon wafer, 1a, 1c...Silicon pellet, 1b...Fusion part, 2...Nickel layer, 3,5
...Solder foil, 3a...Solder fine powder, 4...Glass, 5
...Solder foil, 5a...Fuse part, 5b...Adhesive solder part, 6...Metal electrode film, 7, 9...Laser beam head part, 8, 10...Laser beam, 11...Integrated mechanism, 1
2, 13... Beam oscillation device, 14... Conductive lead.
Claims (1)
金属電極膜を設け、それ以外の部分には表面保護
膜を設けておいて、はんだ箔を仮付固定し、はん
だ箔のみを溶断する熱源線を走査してはんだ箔を
金属電極膜上にはんだ電極として溶断し、次に、
溶断した間に更に熱源線を走査して上記表面保護
膜および半導体ウエハを溶断し、半導体ウエハを
スクライブして半導体ペレツトを得ることを特徴
とする半導体装置の製造方法。1. A metal electrode film is provided on the part of the semiconductor wafer that will become the semiconductor pellet, and a surface protection film is provided on the other parts. Solder foil is temporarily fixed, and a heat source line that melts only the solder foil is scanned. The solder foil is melted as a solder electrode on the metal electrode film, and then,
A method for manufacturing a semiconductor device, which comprises further scanning a heat source line during the melting process to melt the surface protection film and the semiconductor wafer, and scribe the semiconductor wafer to obtain semiconductor pellets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57026124A JPS58143553A (en) | 1982-02-22 | 1982-02-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57026124A JPS58143553A (en) | 1982-02-22 | 1982-02-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58143553A JPS58143553A (en) | 1983-08-26 |
| JPS634941B2 true JPS634941B2 (en) | 1988-02-01 |
Family
ID=12184811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57026124A Granted JPS58143553A (en) | 1982-02-22 | 1982-02-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58143553A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100514075B1 (en) * | 1998-12-04 | 2005-11-25 | 삼성전자주식회사 | Cutting device for substrate and liquid crystal display panel using laser beam |
| US6562698B2 (en) * | 1999-06-08 | 2003-05-13 | Kulicke & Soffa Investments, Inc. | Dual laser cutting of wafers |
| US7772090B2 (en) | 2003-09-30 | 2010-08-10 | Intel Corporation | Methods for laser scribing wafers |
| JP2006269897A (en) * | 2005-03-25 | 2006-10-05 | Disco Abrasive Syst Ltd | Laser processing method of wafer |
| DE102011075328A1 (en) * | 2011-05-05 | 2012-11-08 | Interpane Entwicklungs-Und Beratungsgesellschaft Mbh | Apparatus and method for edge delamination and scoring of coated substrates |
| NL2026427B1 (en) | 2019-09-10 | 2021-10-13 | Tokyo Seimitsu Co Ltd | Laser machining apparatus |
| CN117840614B (en) * | 2024-03-07 | 2024-05-07 | 南京航空航天大学 | Multi-wavelength laser modified welding device and method based on shallow cladding of nano-welding wire |
-
1982
- 1982-02-22 JP JP57026124A patent/JPS58143553A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58143553A (en) | 1983-08-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5290986A (en) | Thermally assisted shorts removal process for glass ceramic product using an RF field | |
| US10315403B2 (en) | Method for cutting object to be processed | |
| JP3129728B2 (en) | Thin film semiconductor device | |
| JP5342772B2 (en) | Processing object cutting method | |
| US4404453A (en) | Laser bonding of microelectronic circuits | |
| US3672047A (en) | Method for bonding a conductive wire to a metal electrode | |
| US8890026B2 (en) | Method for cutting processing target | |
| JPH08148522A (en) | Semiconductor device, semiconductor device mounting body and method for replacing semiconductor device | |
| JP2003188294A (en) | Manufacturing method of electronic component | |
| JPS634941B2 (en) | ||
| JP3509985B2 (en) | Chip separation method for semiconductor device | |
| JPS634940B2 (en) | ||
| JPH08264819A (en) | Semiconductor device and manufacturing method thereof | |
| EP0040669B1 (en) | Method of eliminating solder pads remaining on a ceramic substrate after removing a semiconductor chip by absorption in a porous copper block, and use in reworking modules | |
| JPS5919356A (en) | Manufacture of semiconductor device | |
| JPS603134A (en) | Wire bonding method | |
| JPS6240119B2 (en) | ||
| JPH0729942A (en) | Repair method of electronic device | |
| JP2970636B2 (en) | Optical semiconductor module and manufacturing method thereof | |
| JPH07273133A (en) | Manufacture of semiconductor device | |
| JPH0757614A (en) | Electronic part for protection of micro thin film circuit | |
| JP3346169B2 (en) | Method of forming bump | |
| JPH11260847A (en) | Method of forming solder bumps | |
| JPH07122694A (en) | Machining method for outer lead | |
| JPH10261865A (en) | Mounting method of electric part |