[go: up one dir, main page]

JPH0729942A - Repair method for electronic device - Google Patents

Repair method for electronic device

Info

Publication number
JPH0729942A
JPH0729942A JP5173350A JP17335093A JPH0729942A JP H0729942 A JPH0729942 A JP H0729942A JP 5173350 A JP5173350 A JP 5173350A JP 17335093 A JP17335093 A JP 17335093A JP H0729942 A JPH0729942 A JP H0729942A
Authority
JP
Japan
Prior art keywords
substrate
wire
electronic component
residue
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5173350A
Other languages
Japanese (ja)
Inventor
Ryoichi Kajiwara
良一 梶原
Toshiyuki Takahashi
敏幸 高橋
Mitsuo Kato
光雄 加藤
Kazuya Takahashi
和弥 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5173350A priority Critical patent/JPH0729942A/en
Publication of JPH0729942A publication Critical patent/JPH0729942A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98Methods for disconnecting semiconductor or solid-state bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85014Thermal cleaning, e.g. decomposition, sublimation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 基板上に半導体チップ等が搭載され、そのチ
ップ等が基板とワイヤボンディングにより結線されてい
る電子装置において、そのチップ等が不良だった場合、
これを取り外して新たなチップを確実に搭載する。 【構成】 ワイヤ30をそのネック部31において切断
して、チップ20を基板10から取り除く()。基板
側パッド11上に残ったワイヤ残渣32をその上面が平
坦になるよう加工し()、ワイヤ残渣33及び基板側
パッド11の表面にレーザ41を照射してこれらを清浄
する()。その後、新たなチップを基板10上に固定
して、このチップのパッドと、平坦加工されたワイヤ残
渣33が残っている基板側パッド11とを新たなワイヤ
で結線する。
(57) [Summary] [Purpose] In an electronic device in which a semiconductor chip or the like is mounted on a substrate and the chip or the like is connected to the substrate by wire bonding, if the chip or the like is defective,
Remove this and mount a new chip securely. [Structure] The wire 30 is cut at its neck portion 31 to remove the chip 20 from the substrate 10 (). The wire residue 32 remaining on the board-side pad 11 is processed so that its upper surface becomes flat (), and the surfaces of the wire residue 33 and the board-side pad 11 are irradiated with a laser 41 to clean them (). After that, a new chip is fixed on the substrate 10, and the pad of this chip and the substrate-side pad 11 on which the flattened wire residue 33 remains are connected by a new wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップや各種デ
バイス(例えば、液晶表示デバイス等)が基板上に搭載
され、半導体チップ等と基板とがワイヤボンディングに
より電気的に結線されている電子装置のリペア方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device in which semiconductor chips and various devices (for example, liquid crystal display devices) are mounted on a substrate, and the semiconductor chip and the substrate are electrically connected by wire bonding. Repair method.

【0002】[0002]

【従来の技術】ワイヤボンディングは、半導体モジュー
ル又は半導体パッケージの組立て技術として最も普及し
た接続技術である。しかし、固相状態の接合法であるた
め、その接合性や接合品質は、接合される材料の表面状
態、すなわち酸化膜の有無、有機物・無機物・水分等の
吸着や付着の有無、表面粗さや硬さなどの影響を強く受
ける。このため、接合される半導体チップ、デバイス、
配線基板、リードフレーム等の最終処理と保管方法をき
びしく管理し、これらの表面が接合阻害物質で汚染され
たり、厚い酸化膜が成長したりすることが無いよう細心
の注意を払いっている。
2. Description of the Related Art Wire bonding is the most popular connection technology as an assembly technology for semiconductor modules or semiconductor packages. However, since it is a solid-state joining method, the joining property and joining quality depend on the surface state of the materials to be joined, that is, the presence or absence of an oxide film, the presence or absence of adsorption / adhesion of organic substances / inorganic substances / water, surface roughness and It is strongly affected by hardness. Therefore, the semiconductor chips, devices,
We strictly control the final treatment and storage method of wiring boards, lead frames, etc., and pay close attention to prevent their surfaces from being contaminated with bonding inhibitors and from growing thick oxide films.

【0003】従来の製品は、パッケージ内に1つの半導
体チップが内蔵されているシングルチップパッケージが
主であり、接合不良等が発生した場合には製品ごと廃棄
している。ところで、近年の状況として、電子装置の高
機能・高性能化を図るため高密度実装技術が要求され、
一枚の基板上に複数の半導体チップが搭載されるマルチ
チップモジュールの必要性(電子情報通信学会技術研究
報告 第92巻365号37ページに記載さている。)
が高まってきている。このようなマルチチップモジュー
ルでは、それが高価であるため、1個のチップの欠陥に
よりモジュールが不良となった場合、直ちにモジュール
ごと廃棄することはコスト的に大きな損失となる。この
ため、不良チップの交換がマルチチップモジュールを実
用化する上で必要不可欠な技術となる。
Conventional products are mainly single-chip packages in which one semiconductor chip is built in the package, and when a defective connection or the like occurs, the entire product is discarded. By the way, as a recent situation, high-density mounting technology is required to achieve high functionality and high performance of electronic devices,
Necessity of a multi-chip module in which a plurality of semiconductor chips are mounted on one substrate (described in Technical Report of the Institute of Electronics, Information and Communication Engineers Vol. 92, No. 365, page 37).
Is increasing. Since such a multi-chip module is expensive, if the module becomes defective due to the defect of one chip, immediately discarding the whole module causes a great cost loss. Therefore, replacement of defective chips is an indispensable technique for putting a multichip module into practical use.

【0004】一般的に、チップと基板等とを電気的に接
続するための技術としては、前述したワイヤボンディン
グの他に、テープキャリアボンディング(TAB)やフ
ィリップチップボンディング等がある。これらのボンデ
ィング技術のうち、フィリップチップボンディングによ
り接続されたチップをリペアする技術に関しては、例え
ば、特開昭63-107192号公報や特開昭57-52145号公報に
記載されているものがあるが、マルチチップモジュール
は、前述したように、近年になって、その必要性が求め
られてきているものであるため、これらのボンディング
技術により接続されたチップをリペアする技術に関して
は、十分に開発されていないのが現状である。
Generally, as a technique for electrically connecting a chip to a substrate or the like, there are tape carrier bonding (TAB), Philip chip bonding, etc. in addition to the above-mentioned wire bonding. Among these bonding techniques, as to the technique for repairing the chip connected by the Philip chip bonding, for example, there are those described in JP-A-63-107192 and JP-A-57-52145. As described above, the multi-chip module has been required in recent years, and thus the technology for repairing chips connected by these bonding technologies has been sufficiently developed. The current situation is not.

【0005】[0005]

【発明が解決しようとする課題】以上のように、従来技
術においては、ワイヤボンディングにより接続されたチ
ップをリペアする技術が十分に開発されていないため、
ワイヤボンディングにより接続されたチップを複数有す
るマルチチップモジュールは、1チップの欠陥によるモ
ジュール廃棄分も価格に添加され、製造コストが嵩むと
いう問題点がある。
As described above, in the prior art, the technique for repairing the chips connected by wire bonding has not been sufficiently developed.
A multi-chip module having a plurality of chips connected by wire bonding has a problem in that a module waste due to a defect of one chip is also added to the price and the manufacturing cost increases.

【0006】本発明は、このような従来の問題点に着目
してなされたもので、ワイヤボンディングにより接続さ
れたチップを有する電子装置のリペア方法を提供するこ
とを目的とする。
The present invention has been made in view of such conventional problems, and an object thereof is to provide a method for repairing an electronic device having a chip connected by wire bonding.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するため
の電子装置のリペア方法は、基板上に搭載されている電
子部品が不良である場合、電子部品側パッドと基板側パ
ッドとを結線するワイヤをその基板側パッド側のネック
部において切断して、前記電子部品を前記基板から取り
除き、前記基板側パッド上に残ったワイヤ残渣をその上
面が平坦になるよう加工し、該ワイヤ残渣及び該基板側
パッドの表面を清浄し、新たな電子部品を前記基板上に
固定して、該電子部品に形成されたパッドと、平坦加工
された前記ワイヤ残渣が残っている前記基板側パッドと
を新たなワイヤで結線することを特徴とするものであ
る。
According to a method of repairing an electronic device for achieving the above object, when an electronic component mounted on a substrate is defective, the electronic component side pad and the substrate side pad are connected. The wire is cut at the neck portion on the side of the board-side pad, the electronic component is removed from the board, and the wire residue remaining on the board-side pad is processed so that the upper surface thereof becomes flat. The surface of the board-side pad is cleaned, a new electronic component is fixed on the board, and the pad formed on the electronic component and the board-side pad on which the flattened wire residue remains are newly added. It is characterized in that the wires are connected with each other.

【0008】ここで、前記清浄は、レーザやプラズマ等
を用いて行うことが好ましい。また、前記電子部品が半
田材で前記基板上にダイボンディングされている場合に
は、前記電子部品が搭載されている部分を加熱して、前
記半田材を溶融させ、該電子部品を前記基板から取り除
き、不活性ガス又は還元性ガス雰囲気内で、前記基板上
に残っている半田残渣の表面にレーザを照射して、該表
面の酸化膜を除去し、前記基板上の前記電子部品が取り
除かれた部分に新たな半田材及び新たな電子部品を配
し、該新たな半田材及び前記半田残渣を溶融させて該新
たな電子部品を該基板上に再ダイボンディングすること
が好ましい。また、前記電子部品が有機接着剤で前記基
板上にダイボンディングされている場合には、前記電子
部品を前記基板上から機械的に剥離し、酸化性ガス雰囲
気内で、前記基板上に残っている有機接着剤残渣にレー
ザを照射し、該有機接着剤をほぼ完全に気化させて除去
し、前記基板上の前記電子部品が取り除かれた部分に新
たに有機接着剤を供給し、そこに新たな電子部品を配し
て、該新たな電子部品を該基板上に再ダイボンディング
することが好ましい。
Here, it is preferable that the cleaning is performed by using laser, plasma or the like. Further, when the electronic component is die-bonded on the substrate with a solder material, a portion where the electronic component is mounted is heated to melt the solder material, and the electronic component is removed from the substrate. The surface of the solder residue remaining on the substrate is irradiated with a laser in an atmosphere of an inert gas or a reducing gas to remove the oxide film on the surface, and the electronic component on the substrate is removed. It is preferable to dispose a new solder material and a new electronic component on the open portion, melt the new solder material and the solder residue, and re-die-bond the new electronic component on the substrate. Further, when the electronic component is die-bonded onto the substrate with an organic adhesive, the electronic component is mechanically peeled off from the substrate and left on the substrate in an oxidizing gas atmosphere. The organic adhesive residue present is irradiated with a laser to vaporize and remove the organic adhesive almost completely, and a new organic adhesive is supplied to a portion of the substrate where the electronic component is removed, and the organic adhesive is newly added there. It is preferable to dispose different electronic components and to re-die-bond the new electronic component onto the substrate.

【0009】[0009]

【作用】基板上に搭載されている不良チップを取り除く
場合には、まず、チップ側パッドと基板側パッドとを結
線しているワイヤを切断する必要がある。このワイヤを
切断する際、これを無作為に引張破断すると、チップ側
のボールネック部で破断する確率が高い。この場合、基
板側にワイヤの大部分が残ることになり、残ったワイヤ
が他の配線回路と接触し、短絡不良を誘発する可性が高
く、製品としての信頼性が確保できなくなる。これを防
ぐためには、基板側に残ったワイヤを基板側のボンディ
ング部近傍から切断除去すればよいが、直径が数十μm
と微細で任意の方向に屈曲したワイヤを自動的にチャッ
キングすることが難しいため、短時間でのワイヤ除去処
理ができない。そこで、ワイヤの両端が固定されいる状
態で、カッター等でワイヤの基板側ネック部を切断する
こと良い。
In order to remove the defective chip mounted on the substrate, it is necessary to first cut the wire connecting the chip side pad and the substrate side pad. When this wire is cut, if it is pulled and broken at random, there is a high probability of breaking at the ball neck portion on the chip side. In this case, most of the wires are left on the substrate side, and the remaining wires are likely to come into contact with another wiring circuit to cause a short circuit failure, and the reliability as a product cannot be ensured. In order to prevent this, the wire remaining on the substrate side may be cut and removed from the vicinity of the bonding portion on the substrate side, but the diameter is several tens of μm.
Since it is difficult to automatically chuck a fine wire bent in an arbitrary direction, the wire removal process cannot be performed in a short time. Therefore, it is preferable to cut the substrate side neck portion of the wire with a cutter or the like in a state where both ends of the wire are fixed.

【0010】ワイヤを切断して、電子部品の除去が終了
すると、新たな電子部品を基板上に置いて、ワイヤが残
っている基板側パッドと新たな電子部品の部品側パッド
とを新たなワイヤで結線する。この場合、ワイヤを切断
した状態においては、その切断面は、小さく且つ凹凸を
有している。このため、このような切断面が形成されて
いるワイヤ残渣、又はこのワイヤ残渣が残っている基板
側パッドに新たなワイヤを接続しようとしても、その接
続信頼性に欠けることになってしまう。そこで、再ワイ
ヤボンディングする前に、ワイヤ残渣をプレス加工し、
その上面が平坦で且つ広くなるようにする。
When the wire is cut and the removal of the electronic component is completed, a new electronic component is placed on the substrate, and the board-side pad where the wire remains and the component-side pad of the new electronic component are replaced with a new wire. Connect with. In this case, when the wire is cut, the cut surface is small and has irregularities. Therefore, even if an attempt is made to connect a new wire to the wire residue having such a cut surface or the board-side pad on which the wire residue remains, the connection reliability will be poor. Therefore, press the wire residue before re-wire bonding,
Make the top surface flat and wide.

【0011】また、再ワイヤボンディングする際の接続
信頼性は、単に、ワイヤ残渣をプレス加工したままで
は、プレス治具からボンディング面に付着した汚れ、あ
るいはモジュールの組立工程や各種検査工程を経る過程
でボンディング面に付着した汚れにより、低下してしま
う。そこで、プレス加工したワイヤ残渣及び基板側パッ
ド表面から有機物や無機物を取り除くべく、その表面を
清浄する。この清浄の具体的な方法としては、そこに、
プラズマ照射、レーザ照射、アーク放電等することが考
えられる。このように、清浄処理することにより、新た
なワイヤと基板側パッドとの接続信頼性を初期の基板側
パッドとワイヤとの接続信頼性と同等にすることができ
る。
Further, the connection reliability at the time of re-wire-bonding is simply the process of going through the dirt attached to the bonding surface from the pressing jig or the module assembling process and various inspection processes if the wire residue is still pressed. Therefore, the dirt attached to the bonding surface causes the deterioration. Therefore, in order to remove organic substances and inorganic substances from the pressed wire residue and the substrate-side pad surface, the surface is cleaned. As a concrete method of this cleaning,
Plasma irradiation, laser irradiation, arc discharge, etc. can be considered. By performing the cleaning process in this way, the connection reliability between the new wire and the board-side pad can be made equal to the initial connection reliability between the board-side pad and the wire.

【0012】一方、基板上に半導体チップがダイボンデ
ィングされた部分に関しては、半田材によるダイボンデ
ィングか有機接着剤によるダイボンディングかで、その
対応が異なる。半田付けの場合は、チップの除去を半田
のリフローにより行うが、チップ除去後のダイボンディ
ングパッド上には半田残渣が残り、その表面には厚い酸
化膜が形成される。その上に新しいチップを接続するに
は、半田表面の酸化膜を取り除くことが必要である。こ
の酸化膜を取り除く方法としては、フラックスを用いる
方法が考えられるが、脱フロン化が進み、フラックスを
用いることが難しい状況では、別の半田付け性改善手法
が必要である。そこで、本発明では、不活性ガスあるい
は還元性ガス雰囲気中において、半田残渣の表面にレー
ザ照射して、酸化膜を除去している。
On the other hand, regarding the portion where the semiconductor chip is die-bonded on the substrate, the correspondence differs depending on whether the die-bonding with a solder material or the die-bonding with an organic adhesive. In the case of soldering, the chip is removed by reflowing the solder, but a solder residue remains on the die bonding pad after chip removal, and a thick oxide film is formed on the surface thereof. In order to connect a new chip on it, it is necessary to remove the oxide film on the solder surface. As a method of removing this oxide film, a method of using a flux can be considered, but in a situation where it is difficult to use a flux due to the progress of defluoroization, another solderability improving method is necessary. Therefore, in the present invention, the surface of the solder residue is irradiated with laser in an inert gas or reducing gas atmosphere to remove the oxide film.

【0013】また、有機接着剤による場合は、チップ除
去後の接着剤残渣とチップ等とは接着性が悪いため、接
着剤残渣を完全に除去し、初期のダイボンディングパッ
ド表面と同等の状態にまで回復する必要がある。そこ
で、本発明では、酸化雰囲気中でレーザを照射すること
により、下の金属製ダイ面にはダメージを与えず接着剤
を効率的に気化させて除去している。
In the case of using an organic adhesive, since the adhesive residue after removing the chip and the chip etc. have poor adhesion, the adhesive residue is completely removed to obtain a state equivalent to the initial die bonding pad surface. Need to recover. Therefore, in the present invention, by irradiating a laser in an oxidizing atmosphere, the adhesive is efficiently vaporized and removed without damaging the metal die surface below.

【0014】[0014]

【実施例】以下、本発明に係る各種実施例を図面を用い
て詳細に説明する。まず、本発明に係る電子装置のリペ
ア方法を説明する前に、マルチチップモジュールの構成
について、図7を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments according to the present invention will be described in detail below with reference to the drawings. First, before describing the repair method for the electronic device according to the present invention, the configuration of the multi-chip module will be described with reference to FIG. 7.

【0015】同図に示すように、マルチチップモジュー
ルは、セラミック製多層基板10上に複数の半導体チッ
プ20,20,50が搭載されたものである。これらの
半導体チップ20,20,50は、一方の面(上面)に
複数のワイヤボンディングパッド21,21,51が形
成され、反対側の他方の面(下面)がダイボンディング
面として形成されている。各チップ20,20,50
は、基板10上のダイボンディングパッド12,12,
12に固定されている。チップ側ワイヤボンディングパ
ッド(以下、単にチップ側パッドとする。)21,2
1,51は、基板10上に形成されたワイヤボンディン
グパッド(以下、単に基板側パッドとする。)11,1
1,11とワイヤ30,30,30により接続されてい
る。
As shown in FIG. 1, the multi-chip module has a plurality of semiconductor chips 20, 20, 50 mounted on a ceramic multilayer substrate 10. In these semiconductor chips 20, 20, 50, a plurality of wire bonding pads 21, 21, 51 are formed on one surface (upper surface) and the other surface (lower surface) on the opposite side is formed as a die bonding surface. . Each chip 20, 20, 50
Is a die bonding pad 12, 12,
It is fixed at 12. Chip-side wire bonding pads (hereinafter, simply referred to as chip-side pads) 21,2
1, 51 are wire bonding pads (hereinafter, simply referred to as substrate-side pads) 11, 1 formed on the substrate 10.
1, 11 and wires 30, 30, 30 are connected.

【0016】次に、本発明に係る電子装置のリペア方法
の実施例について、図1及び図2を用いて説明する。半
導体チップ20は、図1のに示すように、フェイスア
ップで基板10上のダイボンディングパッド12に半田
材13で固定されている。チップ側パッド21とワイヤ
30とはボールボンディングされ、基板側パッド11と
ワイヤ30とはウェッジボンディングされている。な
お、このチップ20は、図7を用いて説明したマルチチ
ップモジュールを構成する複数のチップのうちの一つで
ある。
Next, an embodiment of a repair method for an electronic device according to the present invention will be described with reference to FIGS. As shown in FIG. 1, the semiconductor chip 20 is fixed face-up to the die bonding pad 12 on the substrate 10 with the solder material 13. The chip-side pad 21 and the wire 30 are ball-bonded, and the substrate-side pad 11 and the wire 30 are wedge-bonded. The chip 20 is one of a plurality of chips that form the multi-chip module described with reference to FIG.

【0017】各種検査を経て、図1のに示す半導体チ
ップ20自体又はその接続等に欠陥が認められた場合に
は、この不良チップ20を取り除く必要がある。そこ
で、まず、同図に示すように、各ワイヤ30をチップ
20から遠ざかる方向に引っ張り、基板側パッド11側
のネック部31で破断させる。続いて、ダイボンディン
グパッド12上の半田材13を加熱して溶融し、チップ
20を基板10上から除去する。
If defects are found in the semiconductor chip 20 itself shown in FIG. 1 or its connection after various inspections, it is necessary to remove the defective chip 20. Therefore, first, as shown in the figure, each wire 30 is pulled in a direction away from the chip 20 and broken at the neck portion 31 on the substrate pad 11 side. Then, the solder material 13 on the die bonding pad 12 is heated and melted, and the chip 20 is removed from the substrate 10.

【0018】次に、基板側パッド11上に残っているワ
イヤ残渣32をプレスして、同図に示すように、その
上面を平坦化すると共に上面の面積を大きくする。この
ように、ワイヤ残渣32の上面を平坦化することによ
り、ここに新たに接続するワイヤ30a(図2のに示
す。)との接触性を高めることができる。その後、同図
に示すように、上面が平坦化されたワイヤ残渣33及
び基板側パッド11にレーザ光を照射する。ここでは、
レーザとしてKrF(波長:249nm)のエキシマレ
ーザを用い、エネルギー密度が0.1J/cm2のパル
スを100パルス照射している。なお、レーザとして
は、この他に、XeF,ArF,XeCl,KCl,A
rClなどのエキシマレーザや、YAGレーザを用いて
もよい。このように、レーザ光を照射することにより、
組立や検査等のこれまでの工程で、付着した有機物や無
機物等が蒸発して去り、ワイヤ残渣及び基板側パッドの
表面を清浄することができる。この結果、ここに新たに
接続するワイヤ30aのボンディング性を高めることが
できる。
Next, the wire residue 32 remaining on the substrate-side pad 11 is pressed to flatten the upper surface and increase the area of the upper surface as shown in FIG. In this way, by flattening the upper surface of the wire residue 32, it is possible to improve the contact property with the wire 30a (shown in FIG. 2) newly connected thereto. Then, as shown in the figure, the wire residue 33 and the substrate-side pad 11 whose upper surfaces are flattened are irradiated with laser light. here,
A KrF (wavelength: 249 nm) excimer laser is used as a laser, and 100 pulses having an energy density of 0.1 J / cm 2 are irradiated. As the laser, other than this, XeF, ArF, XeCl, KCl, A
An excimer laser such as rCl or a YAG laser may be used. In this way, by irradiating with laser light,
In the steps such as assembling and inspecting so far, the attached organic substances and inorganic substances are evaporated and removed, and the wire residue and the surface of the substrate side pad can be cleaned. As a result, the bondability of the wire 30a newly connected here can be improved.

【0019】次に、図2のに示すように、非酸化性ガ
ス42の雰囲気、又は還元性ガスの雰囲気内に、このモ
ジュールを置いて、光学レンズ44で絞った高エネルギ
ーのエキシマレーザ43をダイボンディングパッド12
上に残っている半田残渣14に照射する。この半田残渣
14の表面は、比較的厚い酸化膜15が形成されている
ので、この酸化膜15にレーザ光を局所的かつ瞬間的に
照射し、酸化膜15を気化させて除去する。この際、レ
ーザ光のエネルギー密度を高めて、短時間で酸化膜を除
去することが好ましい。これは、短時間で酸化膜を除去
することにより、基板側への熱的影響を少なくすること
ができるからである。また、酸化膜15を除去するだけ
でなく、不要な半田材自体、例えば、局部的に凸状にな
っている部分の半田材も除去し、半田残渣14の高さバ
ラツキなくすよい。このように、酸化膜15を除去する
ことで、良品のチップ20aを再半田付けする場合に、
酸化膜の影響による半田付け不良の発生を防止すること
ができる。
Next, as shown in FIG. 2, this module is placed in the atmosphere of the non-oxidizing gas 42 or the atmosphere of the reducing gas, and the high energy excimer laser 43 focused by the optical lens 44 is set. Die bonding pad 12
The solder residue 14 remaining on the upper surface is irradiated. Since a relatively thick oxide film 15 is formed on the surface of the solder residue 14, the oxide film 15 is locally and instantaneously irradiated with laser light to vaporize and remove the oxide film 15. At this time, it is preferable to increase the energy density of the laser light and remove the oxide film in a short time. This is because removing the oxide film in a short time can reduce the thermal influence on the substrate side. Further, not only the oxide film 15 is removed, but also the unnecessary solder material itself, for example, the solder material in a locally convex portion is removed so that the height of the solder residue 14 does not vary. In this way, by removing the oxide film 15, when re-soldering the non-defective chip 20a,
It is possible to prevent defective soldering due to the influence of the oxide film.

【0020】次に、同図に示すように、Pb−Sn−
Agの半田材16と、ダイボンディング面にTi−Ni
−Agのメタライズ層22aを形成した良品チップ20
aとを、この順序でダイボンディングパッド12上に置
く。なお、半田材やメタライズ層の材質は他の組合せで
もよい。そして、同図に示すように、還元雰囲気に保
ちながらノズルから噴出させるホットガスやヒーター治
具等により、基板10の裏側からダイボンディングパッ
ド12に該当する位置を局所的に加熱しつつ、良品チッ
プ20aを水平に振動(スクライブ処理)させて、良品
チップ20aをダイボンディングパッド12上に半田付
けする。このように、不要の半田が除去された後を補充
する形で新しい半田の供給を行うため、良質の半田で再
半田付けを実施でき、接合部の品質を高くすることがで
きる。また、還元性雰囲気で半田付け、及びスクライブ
処理を行うことで、半田の濡れ不良欠陥やボイド欠陥の
発生を低減できる。さらに、局部加熱を行うことで他の
良品チップへの影響を防ぐことができる。その後、良品
チップ20aのチップ側パッド21aと基板側パッド1
1とを接続すべく、チップ側パッド21aにワイヤ30
aの一端をボールボンディングし、基板側パッド11の
ワイヤ残渣33にこのワイヤ30aの一部をウェッジボ
ンディングして、リペアを完了する。
Next, as shown in the figure, Pb-Sn-
Solder material 16 of Ag and Ti-Ni on the die bonding surface
Non-defective chip 20 on which a metallized layer 22a of Ag is formed
and a are placed on the die bonding pad 12 in this order. It should be noted that the solder material and the material of the metallized layer may be other combinations. Then, as shown in the figure, a hot gas ejected from a nozzle while maintaining a reducing atmosphere, a heater jig, or the like locally heats a position corresponding to the die bonding pad 12 from the back side of the substrate 10, and a non-defective chip. The non-defective chip 20a is soldered onto the die bonding pad 12 by vibrating (scribing) 20a horizontally. In this way, since new solder is supplied in a form that replenishes after unnecessary solder is removed, re-soldering can be performed with good-quality solder, and the quality of the joint can be improved. Further, by performing soldering and scribing in a reducing atmosphere, it is possible to reduce the occurrence of solder wetting defects and void defects. Furthermore, by performing local heating, it is possible to prevent the influence on other non-defective chips. After that, the chip side pad 21a of the non-defective chip 20a and the substrate side pad 1
1 to connect to the chip side pad 21a wire 30
One end of a is ball-bonded, and part of the wire 30a is wedge-bonded to the wire residue 33 of the board-side pad 11 to complete the repair.

【0021】本実施例によれば、ワイヤボンディングで
組み立てたマルチチップモジュールにおいて、組立て完
了後にチップの不良が発見され、モジュールの表面が有
機物や無機物等で汚染されボンディング性が劣化してい
る場合でも、新しい良品のチップを再度搭載する工程
で、初期の組立時と同等の品質及び信頼性を有するダイ
ボンディングやワイヤボンディングを行うことが可能と
なり、マルチチップモジュールの製造コストを低減する
ことができる。
According to the present embodiment, in a multi-chip module assembled by wire bonding, even if a defective chip is found after the assembly is completed and the surface of the module is contaminated with an organic substance or an inorganic substance, the bondability is deteriorated. In the process of mounting a new non-defective chip again, it is possible to perform die bonding or wire bonding with the same quality and reliability as those at the time of initial assembly, and it is possible to reduce the manufacturing cost of the multichip module.

【0022】なお、本実施例において、のワイヤボン
ディングパッド清浄化処理の後にのダイボンディング
パッド清浄化処理を行ったが、の処理との処理を還
元雰囲気の中で同時に行うようにしてもよい。また、
のワイヤボンディングパッド清浄化処理で、プレス加工
したワイヤ残渣の表面を清浄化しボンディング性の改善
を図る手段としてレーザ照射を用いたが、Ar雰囲気と
したチャンバー内にモジュールを入れてプラズマを発生
させて、有機物や無機物等の汚染物を除去するようにし
てもよい。更に、レーザの替わりにワイヤ残渣と放電電
極との間に非酸化性雰囲気を作ってアーク放電を発生さ
せる方法や、ボンディング残渣の上に対向電極を配置し
その電極相互間にアーク放電を発生させる方法を用い
て、ワイヤ残渣面を清浄化してもよい。
Although the die bonding pad cleaning treatment is performed after the wire bonding pad cleaning treatment in the present embodiment, the treatment and the treatment may be performed simultaneously in a reducing atmosphere. Also,
Laser irradiation was used as a means for cleaning the surface of the pressed wire residue and improving the bondability in the wire-bonding pad cleaning process in 1. However, a module was placed in a chamber in an Ar atmosphere to generate plasma. Alternatively, contaminants such as organic substances and inorganic substances may be removed. Further, instead of the laser, a method of generating an arc discharge by creating a non-oxidizing atmosphere between the wire residue and the discharge electrode, or by disposing an opposing electrode on the bonding residue and generating an arc discharge between the electrodes The method may be used to clean the wire residue surface.

【0023】次に、ワイヤ残渣の処理に関する他の例に
ついて、図3を用いて説明する。同図のに示すよう
に、図1のの工程と同様に、ボンディングワイヤをチ
ップから遠ざかる方向に引張って、ワイヤ残渣32の先
端がチップ側パッド11上からはみ出さないようにし
て、ワイヤを基板側パッド11側のネック部で破断させ
る。
Next, another example of the treatment of the wire residue will be described with reference to FIG. As shown in the same figure, as in the step of FIG. 1, the bonding wire is pulled in a direction away from the chip so that the tip of the wire residue 32 does not protrude from the chip side pad 11, and the wire is removed from the substrate. The neck portion on the side pad 11 side is broken.

【0024】次に、同図のに示すように、ワイヤ残渣
32及び基板側パッド11の上面にレンズ40で集光し
たエキシマレーザ41を照射し、表面を薄くアブレーシ
ョン処理して清浄する。そして、同図のに示すよう
に、清浄化されたワイヤ残渣32に、下面がフラットな
ウェッジボンディング用のツール45で熱及び超音波を
加えながら、圧力を加え、同図に示すように、ワイヤ
残渣33を平坦に加工する。その後、同図のに示すよ
うに、平坦なワイヤ残渣33にの工程と同じレーザ4
1を照射して表面を清浄化する。そして、同図のに示
すように、この面にリペア用の新たなワイヤ30aをボ
ンディングツール46でボンディングする。すなわち、
本実施例は、ワイヤ残渣を平坦化する前にワイヤ残渣に
レーザ光を照射するもので、それ以外は、先の実施例と
基本的に同様である。
Next, as shown in FIG. 5, the upper surface of the wire residue 32 and the substrate side pad 11 is irradiated with the excimer laser 41 focused by the lens 40, and the surface is thinly ablated and cleaned. Then, as shown in the same figure, pressure is applied to the cleaned wire residue 32 while applying heat and ultrasonic waves with a tool 45 for wedge bonding having a flat lower surface, and as shown in the same figure, The residue 33 is processed flat. After that, as shown in the same figure, the same laser 4 as in the step of forming the flat wire residue 33 is used.
Irradiate 1 to clean the surface. Then, as shown in the same figure, a new wire 30a for repair is bonded to this surface by a bonding tool 46. That is,
In this embodiment, the wire residue is irradiated with a laser beam before the wire residue is flattened, and other than that, it is basically the same as the previous embodiment.

【0025】ワイヤを引張って破断させる場合、破断部
分が延びて、残ったワイヤ残渣32の先端部分がヒゲ状
になる。このため、このような形状のワイヤ残渣32に
対してプレス加工すると、その過程でヒゲの部分が折れ
て、同図ののように、ワイヤ残渣32の表面相互が接
触してしまったり、ワイヤ残渣32の表面と基板側パッ
ド11の表面とが接触してしまう。従って、プレス加工
の結果、ワイヤ残渣32の表面相互が接触してしまった
部分や、ワイヤ残渣32の表面と基板側パッド11の表
面とが接触してしまった部分においては、両者の表面が
清浄化されていないと、両者の接合性が悪くなってしま
う。そこで、本実施例では、プレス加工前に、ワイヤ残
渣32及び基板側パッド11の表面をレーザで清浄化
し、ボンディング部の強度低下を防いでいる。なお、プ
レス加工後においても、再度清浄化処理を行うのは、ウ
ェッジボンディング用のツール45でプレス加工する
と、このツール45でワイヤ残渣32の表面が再度汚れ
てしまうからである。
When the wire is pulled and broken, the broken portion extends and the tip portion of the remaining wire residue 32 becomes a beard. Therefore, when the wire residue 32 having such a shape is pressed, the beard portion is broken in the process and the surfaces of the wire residue 32 come into contact with each other as shown in FIG. The surface of 32 and the surface of the substrate-side pad 11 come into contact with each other. Therefore, as a result of the press working, the surfaces of the wire residues 32 are in contact with each other, and the surfaces of the wire residues 32 and the substrate-side pad 11 are in contact with each other. If not made, the bondability between the two will deteriorate. In view of this, in this embodiment, the surface of the wire residue 32 and the substrate-side pad 11 is cleaned with a laser before pressing to prevent the strength of the bonding portion from decreasing. The reason why the cleaning process is performed again after the press working is that the surface of the wire residue 32 is soiled again by the tool 45 when the wedge bonding tool 45 is pressed.

【0026】次に、ワイヤ破断処理に関する他の例につ
いて、図4を用いて説明する。これまでの実施例では、
ワイヤ30を引っ張って、これを破断させていたが、本
実施例では、ワイヤ30の目的の位置にカッター47等
で機械的な剪断力を加えて、ワイヤ30を切断するもの
である。チップ側パッド21と基板側パッド11とを結
線しているワイヤ30と、不良チップ20との間に、こ
のチップ20の側面とほぼ平行になるように微小なカッ
ター47を挿入する。このとき、カッター47の高さ位
置は、基板側パッド11の上面より僅かに高い高さにす
る。次に、このカッター47を基板とほぼ平行に且つチ
ップ21から遠ざかる方向に移動させて、カッター47
でワイヤ30の基板側パッド11側のネック部31を切
断する。
Next, another example of the wire breaking process will be described with reference to FIG. In the examples so far,
Although the wire 30 was pulled to break it, in the present embodiment, the wire 30 is cut by applying a mechanical shearing force to the target position of the wire 30 with the cutter 47 or the like. A minute cutter 47 is inserted between the wire 30 connecting the chip side pad 21 and the substrate side pad 11 and the defective chip 20 so as to be substantially parallel to the side surface of the chip 20. At this time, the height position of the cutter 47 is set to be slightly higher than the upper surface of the substrate-side pad 11. Next, the cutter 47 is moved substantially parallel to the substrate and away from the chip 21, and the cutter 47 is moved.
Then, the neck portion 31 of the wire 30 on the substrate side pad 11 side is cut.

【0027】このように、ワイヤ30を引っ張って破断
させるのではなく、ワイヤ30に機械的な剪断力を加え
てワイヤ30を切断することにより、ワイヤ30の目的
の位置を確実に切断することができる。また、ワイヤ3
0の切断面は、基板に対して、ほぼ平行になり、ヒゲ状
の部分が形成されないので、先の実施例のように、ワイ
ヤ残渣の平坦化前にワイヤ残渣を清浄化する必要もなく
なる。さらに、本実施例では、チップ20の一辺側に設
けられている複数のワイヤ30,30,…を一度に全て
切断できるので、ワイヤ破断処理の効率化を図ることが
できる。
As described above, the wire 30 is not broken by pulling it, but the mechanical shearing force is applied to the wire 30 to cut the wire 30, whereby the intended position of the wire 30 can be surely cut. it can. Also, wire 3
Since the cut surface of 0 is almost parallel to the substrate and no beard-like portion is formed, it is not necessary to clean the wire residue before the flattening of the wire residue as in the previous embodiment. Further, in the present embodiment, since the plurality of wires 30, 30, ... Provided on one side of the chip 20 can be cut all at once, the efficiency of the wire breaking process can be improved.

【0028】次に、ワイヤ破断処理に関する更に他の例
について、図5を用いて説明する。同図に示すように、
ワイヤ30の基板側のボンディング部34を下面が平坦
なウェッジツール48で超音波と荷重を加えて圧壊す
る。次に、ワイヤ30をチップ20から遠ざかる方向に
引張り、断面が減少して強度の弱ったボンディング部3
4の付け根からワイヤ30を破断させる。
Next, still another example of the wire breaking process will be described with reference to FIG. As shown in the figure,
The bonding portion 34 of the wire 30 on the substrate side is crushed by applying an ultrasonic wave and a load with a wedge tool 48 having a flat lower surface. Next, the wire 30 is pulled in a direction away from the chip 20 to reduce the cross section and weaken the strength of the bonding portion 3.
The wire 30 is broken from the root of 4.

【0029】本実施例によれば、ワイヤ破断処理とワイ
ヤ残渣平坦化処理とを一度に行うことができ、リペアの
作業能率を大幅に向上させることができる。なお、本実
施例においても、カッター47でワイヤ30を切断する
場合のように、ウェッジツール48として、チップ20
の一辺の長さより大きい幅のものを用いることにより、
チップ20の一辺側に設けられている複数のワイヤ3
0,30,…を一度に全て切断することも可能である。
According to this embodiment, the wire breaking process and the wire residue flattening process can be performed at the same time, and the work efficiency of repair can be greatly improved. Also in this embodiment, as in the case where the wire 30 is cut by the cutter 47, the chip 20 is used as the wedge tool 48.
By using a width that is larger than the length of one side of
A plurality of wires 3 provided on one side of the chip 20
It is also possible to disconnect 0, 30, ... All at once.

【0030】次に、有機接着剤により半導体チップが基
板上にダイボンディングされているもののリペア方法に
関する実施例について、図6を用いて説明する。チップ
50は、図6のに示すように、フェイスアップで基板
10上のダイボンディングパッド12に有機接着剤17
で固定されている。チップ側パッド51とワイヤ30と
はボールボンディングされ、基板側パッド11とワイヤ
30とはウェッジボンディングされている。なお、この
チップ20は、図7を用いて説明したマルチチップモジ
ュールを構成する複数のチップのうちの一つである。各
種検査を経て、図6のに示す半導体チップ50自体又
はその接続等に欠陥が認められた場合には、まずの工
程に示すように、ボンディングワイヤ30を基板側パッ
ド11側のネック部31で破断させる。続いて、有機接
着剤17に剪断力を加えてチップ50を機械的に剥離す
る。このとき、ダイボンディングパッド12上には凹凸
のある接着剤残渣18が残る。
Next, an embodiment relating to a method for repairing a semiconductor chip die-bonded on a substrate with an organic adhesive will be described with reference to FIG. As shown in FIG. 6, the chip 50 has an organic adhesive 17 on the die bonding pad 12 on the substrate 10 face up.
It is fixed at. The chip-side pad 51 and the wire 30 are ball-bonded, and the substrate-side pad 11 and the wire 30 are wedge-bonded. The chip 20 is one of a plurality of chips that form the multi-chip module described with reference to FIG. When defects are found in the semiconductor chip 50 itself or the connection thereof shown in FIG. 6 after various inspections, as shown in the first step, the bonding wire 30 is attached to the neck portion 31 on the substrate pad 11 side. Break. Subsequently, a shearing force is applied to the organic adhesive 17 to mechanically peel the chip 50. At this time, the adhesive residue 18 having irregularities remains on the die bonding pad 12.

【0031】そこで、同図のに示すように、酸化性ガ
ス49の雰囲気内に、このモジュールを置いて、光学レ
ンズ64で絞った高エネルギーのエキシマレーザ63を
接着剤残渣18に照射し、この接着剤残渣18を瞬間的
に気化させて全て除去する。次に、同図のに示すよう
に、接着剤残渣18を全て除去したダイボンディングパ
ッド12上に新しい有機接着剤17aを供給し、そこに
新しい良品チップ50aを置いて軽く加圧した後、全体
を接着剤のキュア温度に加熱して接着剤16aを固め
る。その後、新たなチップ50aのチップ側パッド51
aと基板側パッド33とをワイヤボンディングで接続し
て、リペアを完成する。なお、ワイヤボンディングのリ
ペア方法に関しては、先の実施例と同様である。
Therefore, as shown in FIG. 3, the module is placed in an atmosphere of an oxidizing gas 49, and the adhesive residue 18 is irradiated with a high energy excimer laser 63 focused by an optical lens 64. The adhesive residue 18 is instantaneously vaporized and completely removed. Next, as shown in the same figure, a new organic adhesive 17a is supplied onto the die bonding pad 12 from which all the adhesive residue 18 has been removed, and a new non-defective chip 50a is placed there and lightly pressed, Is heated to the curing temperature of the adhesive to harden the adhesive 16a. Then, the chip side pad 51 of the new chip 50a
A is connected to the substrate side pad 33 by wire bonding to complete the repair. The method of repairing wire bonding is the same as in the previous embodiment.

【0032】本実施例によれば、レーザ63をダイボン
ディングパッド12上に局所的に照射して有機接着剤1
7を除去しているので、ダイボンディングパッド12や
他の部品に損傷を与えることなく有機接着剤残渣18を
完全に除去することができる。この結果、初期と同等の
有機接着性を確保できるため、良好な再ダイボンディン
グを行うことができる。
According to the present embodiment, the laser 63 is locally irradiated onto the die bonding pad 12 to apply the organic adhesive 1
Since 7 is removed, the organic adhesive residue 18 can be completely removed without damaging the die bonding pad 12 and other parts. As a result, it is possible to secure the same organic adhesiveness as in the initial stage, so that good re-die bonding can be performed.

【0033】以上、本発明に係るリペア方法の各種実施
例を説明してきたが、この技術は、基板10上に複数の
裸チップ20,20,50が搭載されているマルチチッ
プモジュール(図7に示す。)以外にも適用できる。例
えば、図8に示すように、1個の裸チップ20と複数の
半導体パッケージ70,70,…とが混在しているマル
チチップモジュールにも適用できる。このモジュールの
基板75は、有機多層基板本体76と、基板本体76に
形成される貫通孔77に収められているフィン付き金属
製基板構成部78とで構成されている。基板本体76上
には、複数の半導体パッケージ70,70,…が搭載さ
れ、フィン付き基板構成部78上には、裸チップ20が
半田材で固定されている。その裸チップ20のパッド2
1と基板本体76のパッド79とは、ワイヤ30で結線
されている。このように、基板75上に1個の裸チップ
20が搭載され、基板75と裸チップ20とがワイヤボ
ンディングにより電気的に接続されている場合でも、以
上において説明したリペア方法を適用することができ
る。但し、基板上に、1個の裸チップのみが搭載され、
その他に半導体部品がまったく搭載されない場合には、
わざわざ、その裸チップをリペアする労力をかけるより
も、このモジュールごと廃棄した方が効率が良いので、
チップリペアの有効性はあまりない。
Although various embodiments of the repair method according to the present invention have been described above, this technique is a multi-chip module in which a plurality of bare chips 20, 20, 50 are mounted on the substrate 10 (see FIG. 7). Applicable to other than For example, as shown in FIG. 8, it is also applicable to a multi-chip module in which one bare chip 20 and a plurality of semiconductor packages 70, 70, ... Are mixed. The substrate 75 of this module is composed of an organic multilayer substrate body 76 and a finned metal substrate forming portion 78 housed in a through hole 77 formed in the substrate body 76. A plurality of semiconductor packages 70, 70, ... Are mounted on the substrate body 76, and the bare chip 20 is fixed to the finned substrate forming portion 78 with a solder material. Pad 2 of the bare chip 20
1 and the pad 79 of the substrate body 76 are connected by the wire 30. Thus, even when one bare chip 20 is mounted on the substrate 75 and the substrate 75 and the bare chip 20 are electrically connected by wire bonding, the repair method described above can be applied. it can. However, only one bare chip is mounted on the board,
If no other semiconductor components are mounted,
Since it is more efficient to discard this module than to spend the trouble of repairing the bare chip,
Chip repair is not very effective.

【0034】また、以上の実施例におけるリペア技術
は、半導体チップのリペアのみならず、他のデバイス、
例えば、液晶表示デバイスにも適用できる。図9に示す
ように、基板80上に液晶表示デバイス85と複数の半
導体パッケージ70,70,…とが搭載されている。液
晶表示デバイス85は、2枚のガラス板86,87とこ
の間に封入されている液晶(図示されていない。)とを
有して構成されている。この液晶デバイス85のパッド
88と基板80のパッド81とは、ワイヤ84で結線さ
れている。このように、比較的高価な液晶表示デバイス
85が不良となった場合でも、先に説明したリペア方法
により、液晶デバイス85をリペアすれば、モジュール
基板80や半導体パッケージ70を捨てることなく有効
に使えるため、トータルとして製品コストを下げること
が可能となる。
Further, the repair technique in the above embodiments is not limited to the repair of the semiconductor chip, and other devices,
For example, it can be applied to a liquid crystal display device. As shown in FIG. 9, a liquid crystal display device 85 and a plurality of semiconductor packages 70, 70, ... Are mounted on a substrate 80. The liquid crystal display device 85 is configured to have two glass plates 86 and 87 and a liquid crystal (not shown) sealed between them. The pad 88 of the liquid crystal device 85 and the pad 81 of the substrate 80 are connected by a wire 84. As described above, even when the relatively expensive liquid crystal display device 85 becomes defective, if the liquid crystal device 85 is repaired by the repair method described above, the module substrate 80 and the semiconductor package 70 can be effectively used without being discarded. Therefore, it is possible to reduce the total product cost.

【0035】[0035]

【発明の効果】本発明によれば、不良電子部品を基板か
ら取り除いた後、基板側パッド上に残るワイヤ残渣を平
坦加工し、さらにその表面を清浄化処理しているので、
新たなワイヤとこれらとの接続信頼性を高めることがで
きる。また、基板と新たな電子部品とのダイボンディン
グにおいても、半田材残渣の酸化膜除去、又は有機半田
材の除去を行った後に、新たな電子部品を基板上に再ダ
イボンディングしているので、新たな電子部品を基板上
にしっかりと固定することができる。
According to the present invention, after the defective electronic component is removed from the substrate, the wire residue remaining on the substrate-side pad is flattened and the surface thereof is cleaned.
The reliability of connection between the new wire and these can be improved. Also, in die bonding between the substrate and the new electronic component, since the oxide film of the solder material residue is removed or the organic solder material is removed, the new electronic component is re-die-bonded on the substrate, New electronic components can be firmly fixed on the board.

【0036】このように、不良電子部品を取り除き、新
たな電子部品を確実に基板上に搭載することができる結
果、例えば、マルチチップモジュールのように、基板上
に複数のチップ等が搭載されているものでも、1チップ
に欠陥があっても、モジュールごと廃棄する必要がなく
なり、製造コストの低減を図ることができる。
In this way, defective electronic components can be removed and new electronic components can be reliably mounted on the substrate. As a result, for example, a plurality of chips or the like can be mounted on the substrate, such as a multichip module. However, even if one chip has a defect, it is not necessary to discard the entire module, and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る電子装置のリペア方法の一実施例
を説明するための説明図である(図2に続く。)。
FIG. 1 is an explanatory diagram for explaining an embodiment of a repair method for an electronic device according to the present invention (following FIG. 2).

【図2】本発明に係る電子装置のリペア方法の一実施例
を説明するための説明図である(図1から続く。)。
FIG. 2 is an explanatory diagram for explaining an embodiment of a repair method for an electronic device according to the present invention (continued from FIG. 1).

【図3】本発明に係るワイヤ残渣の処理方法の一実施例
を説明するための説明図である。
FIG. 3 is an explanatory diagram for explaining an example of a method for treating a wire residue according to the present invention.

【図4】本発明に係るワイヤ切断方法の一実施例を説明
するための説明図である。
FIG. 4 is an explanatory diagram for explaining an example of a wire cutting method according to the present invention.

【図5】本発明に係るワイヤ切断方法の他の実施例を説
明するための説明図である。
FIG. 5 is an explanatory view for explaining another embodiment of the wire cutting method according to the present invention.

【図6】本発明に係る電子装置のリペア方法の他の実施
例(有機接着剤によりダイボンディングされたものを対
象にしている。)を説明するための説明図である。
FIG. 6 is an explanatory diagram for explaining another embodiment of the repair method for an electronic device according to the present invention (targeted for die-bonding with an organic adhesive).

【図7】本発明に係るマルチチップモジュールの断面図
である。
FIG. 7 is a cross-sectional view of a multi-chip module according to the present invention.

【図8】本発明に係る他のマルチチップモジュールの断
面図である。
FIG. 8 is a cross-sectional view of another multichip module according to the present invention.

【図9】本発明に係る液晶表示モジュールの断面図であ
る。
FIG. 9 is a cross-sectional view of a liquid crystal display module according to the present invention.

【符号の説明】[Explanation of symbols]

10,75,80…基板、11,79,81…基板側パ
ッド、12…ダイボンディングパッド、13,13a…
半田材、14…半田材残渣、15…酸化膜、17,17
a…有機接着剤、18…有機接着剤残渣、20,50…
半導体チップ、21,51…チップ側パッド、22,2
2a…メタライズ層、30,30a…ワイヤ、31…ネ
ック部、32…ワイヤ残渣(平坦化前)、33…ワイヤ
残渣(平坦化後)、41,43,43a,63,63a
…エキシマレーザ、45…ウェッジボンディング用のツ
ール、46…ボンディングツール、47…カッター、4
8…ウェッジツール、70…半導体パッケージ、85…
液晶表示デバイス。
10, 75, 80 ... Substrate, 11, 79, 81 ... Substrate side pad, 12 ... Die bonding pad, 13, 13a ...
Solder material, 14 ... Solder material residue, 15 ... Oxide film, 17, 17
a ... Organic adhesive, 18 ... Organic adhesive residue, 20, 50 ...
Semiconductor chips 21, 51 ... Chip side pads 22, 22,
2a ... Metallized layer, 30, 30a ... Wire, 31 ... Neck part, 32 ... Wire residue (before planarization), 33 ... Wire residue (after planarization), 41, 43, 43a, 63, 63a
… Excimer laser, 45… Wedge bonding tool, 46… Bonding tool, 47… Cutter, 4
8 ... Wedge tool, 70 ... Semiconductor package, 85 ...
Liquid crystal display device.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 和弥 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuya Takahashi 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】半導体チップ又はデバイス(以下、電子部
品とする。)が基板上にダイボンディングされ、該電子
部品に形成されたパッド(以下、電子部品側パッドとす
る。)と基板に形成されたパッド(以下、基板側パッド
とする。)とがワイヤにより結線されている電子装置の
リペア方法において、 前記電子部品が不良である場合、 前記ワイヤをその基板側パッド側のネック部において切
断して、前記電子部品を前記基板から取り除き、 前記基板側パッド上に残ったワイヤ残渣をその上面が平
坦になるよう加工し、該ワイヤ残渣及び該基板側パッド
の表面を清浄し、 新たな電子部品を前記基板上に固定して、該電子部品に
形成されたパッドと、平坦加工された前記ワイヤ残渣が
残っている前記基板側パッドとを新たなワイヤで結線す
ることを特徴とする電子装置のリペア方法。
1. A semiconductor chip or device (hereinafter referred to as an electronic component) is die-bonded on a substrate to form a pad formed on the electronic component (hereinafter referred to as an electronic component side pad) and a substrate. A pad (hereinafter, referred to as a board-side pad) is connected by a wire in a method of repairing an electronic device, wherein when the electronic component is defective, the wire is cut at a neck portion on the board-side pad side. The electronic component is removed from the substrate, the wire residue remaining on the substrate-side pad is processed so that its upper surface is flat, and the wire residue and the surface of the substrate-side pad are cleaned, Is fixed on the substrate, and the pad formed on the electronic component and the pad on the substrate where the flattened wire residue remains are connected by a new wire. And a method of repairing an electronic device.
【請求項2】前記ワイヤを引張って切断する場合、 前記ワイヤの延性によりヒゲ状に形成される切断端部が
前記基板側パッド上からはみ出さないよう、該ワイヤを
引っ張ることを特徴とする請求項1記載の電子装置のリ
ペア方法。
2. When the wire is cut by pulling, the wire is pulled so that a cut end formed in a beard shape due to the ductility of the wire does not protrude from the substrate side pad. Item 1. A method of repairing an electronic device according to Item 1.
【請求項3】前記ワイヤ残渣を平坦加工する前に、該ワ
イヤ残渣の表面を清浄することを特徴とする請求項2記
載の電子装置のリペア方法。
3. The method for repairing an electronic device according to claim 2, wherein the surface of the wire residue is cleaned before the wire residue is flattened.
【請求項4】前記ワイヤを切断する場合、 切断刃にて、前記ワイヤの基板側パッド側のネック部を
機械的に切断することを特徴とする請求項1記載の電子
装置のリペア方法。
4. The method of repairing an electronic device according to claim 1, wherein, when the wire is cut, a neck portion of the wire on the substrate side pad side is mechanically cut by a cutting blade.
【請求項5】清浄する場所にレーザを照射して、前記清
浄を行うことを特徴とする請求項1、2、3又は4記載
の電子装置のリペア方法。
5. The method of repairing an electronic device according to claim 1, wherein the cleaning is performed by irradiating a place to be cleaned with a laser.
【請求項6】前記電子装置をチャンバー内に入れ、該チ
ャンバー内にプラズマを発生させて、前記清浄を行うこ
とを特徴とする請求項1、2、3又は4記載の電子装置
のリペア方法。
6. The method of repairing an electronic device according to claim 1, wherein the electronic device is placed in a chamber and plasma is generated in the chamber to perform the cleaning.
【請求項7】前記ワイヤ残渣が残っている前記基板側パ
ッド上に放電電極を配し、該基板側パッドと該放電電極
との間にアークを発生させて、前記清浄を行うことを特
徴とする請求項1、2、3又は4記載の電子装置のリペ
ア方法。
7. The cleaning is performed by disposing a discharge electrode on the substrate-side pad where the wire residue remains and generating an arc between the substrate-side pad and the discharge electrode. The method for repairing an electronic device according to claim 1, 2, 3, or 4.
【請求項8】前記ワイヤ残渣が残っている前記基板側パ
ッド上に2つの対向電極を配し、該対向電極相互間にア
ークを発生させて、前記清浄を行うことを特徴とする請
求項1、2、3又は4記載の電子装置のリペア方法。
8. The cleaning is performed by arranging two counter electrodes on the substrate-side pad where the wire residue remains and generating an arc between the counter electrodes. 2. The method for repairing an electronic device according to 2, 3, or 4.
【請求項9】前記ワイヤ残渣を平坦加工する場合、 端部が平坦なツールに熱のみ又は熱と超音波とを加えつ
つ、該ツールの平坦な部分を前記ワイヤ残渣に押し付け
て、該ワイヤ残渣をその上面が平坦になよう加工するこ
とを特徴とする請求項1、2、3、4、5、6、7又は
8記載の電子装置のリペア方法。
9. When flattening the wire residue, a flat part of the tool is pressed against the wire residue while applying only heat or heat and ultrasonic waves to the tool having a flat end, 9. The method for repairing an electronic device according to claim 1, wherein the upper surface is processed to be flat.
【請求項10】前記電子部品が半田材で前記基板上にダ
イボンディングされている場合、 前記電子部品が搭載されている部分を加熱して、前記半
田材を溶融させ、該電子部品を前記基板から取り除き、 不活性ガス又は還元性ガス雰囲気内で、前記基板上に残
っている半田残渣の表面にレーザを照射して、該表面の
酸化膜を除去し、 前記基板上の前記電子部品が取り除かれた部分に新たな
半田材及び新たな電子部品を配し、該新たな半田材及び
前記半田残渣を溶融させて該新たな電子部品を該基板上
に再ダイボンディングすることを特徴とする請求項1、
2、3、4、5、6、7、8又は9記載の電子装置のリ
ペア方法。
10. When the electronic component is die-bonded onto the substrate with a solder material, a portion where the electronic component is mounted is heated to melt the solder material, and the electronic component is attached to the substrate. The surface of the solder residue remaining on the substrate is irradiated with a laser in an inert gas or reducing gas atmosphere to remove the oxide film on the surface, and the electronic component on the substrate is removed. A new solder material and a new electronic component are disposed in the formed portion, the new solder material and the solder residue are melted, and the new electronic component is re-die-bonded onto the substrate. Item 1,
A method for repairing an electronic device according to 2, 3, 4, 5, 6, 7, 8 or 9.
【請求項11】前記電子部品が有機接着剤で前記基板上
にダイボンディングされている場合、 前記電子部品を前記基板上から機械的に剥離し、 酸化性ガス雰囲気内で、前記基板上に残っている有機接
着剤残渣にレーザを照射し、該有機接着剤をほぼ完全に
気化させて除去し、 前記基板上の前記電子部品が取り除かれた部分に新たに
有機接着剤を供給し、そこに新たな電子部品を配して、
該新たな電子部品を該基板上に再ダイボンディングする
ことを特徴とする請求項1、2、3、4、5、6、7、
8又は9記載の電子装置のリペア方法。
11. When the electronic component is die-bonded onto the substrate with an organic adhesive, the electronic component is mechanically peeled from the substrate and left on the substrate in an oxidizing gas atmosphere. Irradiating the organic adhesive residue which is being irradiated with a laser, vaporizing and removing the organic adhesive almost completely, and supplying a new organic adhesive to the portion of the substrate where the electronic component has been removed, By arranging new electronic parts,
The re-die-bonding of the new electronic component on the substrate is carried out.
8. The method for repairing an electronic device according to 8 or 9.
JP5173350A 1993-07-13 1993-07-13 Repair method for electronic device Pending JPH0729942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5173350A JPH0729942A (en) 1993-07-13 1993-07-13 Repair method for electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5173350A JPH0729942A (en) 1993-07-13 1993-07-13 Repair method for electronic device

Publications (1)

Publication Number Publication Date
JPH0729942A true JPH0729942A (en) 1995-01-31

Family

ID=15958792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5173350A Pending JPH0729942A (en) 1993-07-13 1993-07-13 Repair method for electronic device

Country Status (1)

Country Link
JP (1) JPH0729942A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6829818B2 (en) 2000-09-12 2004-12-14 Tdk Corporation Manufacturing method of a head gimbal assembly
WO2007105426A1 (en) * 2006-02-28 2007-09-20 Kabushiki Kaisha Toyota Jidoshokki Method for repairing semiconductor device and apparatus for repairing semiconductor device
JP2009021595A (en) * 2008-07-08 2009-01-29 Hitachi Chem Co Ltd Rework method
JP2023087742A (en) * 2021-12-14 2023-06-26 日亜化学工業株式会社 Manufacturing method of surface light source

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6829818B2 (en) 2000-09-12 2004-12-14 Tdk Corporation Manufacturing method of a head gimbal assembly
WO2007105426A1 (en) * 2006-02-28 2007-09-20 Kabushiki Kaisha Toyota Jidoshokki Method for repairing semiconductor device and apparatus for repairing semiconductor device
JP2009021595A (en) * 2008-07-08 2009-01-29 Hitachi Chem Co Ltd Rework method
JP2023087742A (en) * 2021-12-14 2023-06-26 日亜化学工業株式会社 Manufacturing method of surface light source

Similar Documents

Publication Publication Date Title
US5977512A (en) Multi-wavelength laser soldering device with substrate cleaning beam
JP4358502B2 (en) Semiconductor substrate cutting method
JPH10135220A (en) Bump-forming method
JPH05251516A (en) Exchange method for semiconductor chip
US7476597B2 (en) Methods and systems for laser assisted wirebonding
JP2002076043A (en) Bump forming method, semiconductor device, and bump forming device
JP2009146979A (en) Photoelectric conversion device
CN109950162A (en) Promote the laser surface treatment method of pad ultrasonic bonding quality
JP3721559B2 (en) Chip mounting method
JPH0729942A (en) Repair method for electronic device
JP3922870B2 (en) Implementation method
JPH088284A (en) Wire bonding structure and its reinforcing method
JP4599929B2 (en) Method for manufacturing power semiconductor device
JP2586811B2 (en) Solder bump formation method
JP3377411B2 (en) Flip chip mounting structure
JPH1022328A (en) Bonding method and apparatus therefor
JP2809207B2 (en) Semiconductor device repair method and repair device
JPH10190210A (en) Manufacture of circuit module
JPH10190209A (en) Manufacture of circuit module
JPH0737890A (en) Solder ball joining apparatus and joining method thereof
JP3676995B2 (en) Bump bonding method and apparatus
JP2005197760A (en) Cutting method for semiconductor substrate
CN119069372B (en) Wire bonding device and method based on ultrafast laser ablation
JP2001156441A (en) Method for repairing csp/bga
JP2596396B2 (en) Flip chip repair method and repair device