JPS634922B2 - - Google Patents
Info
- Publication number
- JPS634922B2 JPS634922B2 JP57001825A JP182582A JPS634922B2 JP S634922 B2 JPS634922 B2 JP S634922B2 JP 57001825 A JP57001825 A JP 57001825A JP 182582 A JP182582 A JP 182582A JP S634922 B2 JPS634922 B2 JP S634922B2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- trimming
- resistor
- terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009966 trimming Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 9
- 238000005259 measurement Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】
本発明は厚膜抵抗が二重の閉回路を構成してい
る厚膜混成集積回路における、厚膜抵抗のトリミ
ング方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for trimming thick film resistors in a thick film hybrid integrated circuit in which the thick film resistors form a double closed circuit.
厚膜混成集積回路の厚膜抵抗体は印刷により形
成されるが、一般にその精度が悪く、したがつて
トリミングにより所定の抵抗値にするのが一般的
である。厚膜抵抗をトリミングする場合は、通
常、厚膜抵抗の両端の電極パターンに測定用プロ
ーブを接触させ、電圧を加えて厚膜抵抗に微小電
流を流し、電圧と電流の比から自動的に抵抗値に
換算することにより、抵抗値を測定しながらトリ
ミングする。厚膜抵抗が閉回路を構成している場
合は、さらにもう一本のプローブを接触させて行
なう。これを第1図により説明する。第1図は厚
膜混成集積回路の回路図の一部を示すものであ
り、R1〜R3の厚膜抵抗が閉回路を構成している。
L1〜L3は厚膜抵抗R1〜R3を流れる電流であり、
T1〜T3は電極パターンによる端子を示す。この
ような回路で厚膜抵抗R1をトリミングする場合、
端子T2,T3を測定端子とし、さらに端子T1にガ
ードピンを接触させる。ガードピンにより、端子
T1と端子T3、あるいは端子T1と端子T2が同電位
となり、電流I2あるいはI3が零となり、抵抗R2や
R3の影響なく抵抗R1を測定することができる。
ガードピンの機能をもつトリミング装置あるいは
抵抗測定器は一般に数多く使用されており、第1
図のような回路の抵抗値測定およびトリミングは
容易に行なうことができる。 Thick film resistors of thick film hybrid integrated circuits are formed by printing, but the accuracy is generally poor, and therefore it is common to trim them to a predetermined resistance value. When trimming a thick film resistor, normally, a measuring probe is brought into contact with the electrode patterns at both ends of the thick film resistor, a voltage is applied, and a minute current is passed through the thick film resistor, and the resistance is automatically calculated based on the ratio of voltage and current. Trim while measuring the resistance value by converting it to a value. If the thick film resistor forms a closed circuit, connect another probe. This will be explained with reference to FIG. FIG. 1 shows a part of a circuit diagram of a thick film hybrid integrated circuit, in which thick film resistors R 1 to R 3 constitute a closed circuit.
L1 to L3 are the currents flowing through the thick film resistors R1 to R3 ,
T 1 to T 3 indicate terminals based on electrode patterns. When trimming the thick film resistor R 1 in such a circuit,
Terminals T 2 and T 3 are used as measurement terminals, and a guard pin is brought into contact with terminal T 1 . The guard pin allows the terminal
T 1 and terminal T 3 or terminal T 1 and terminal T 2 have the same potential, current I 2 or I 3 becomes zero, and resistance R 2 and
Resistance R 1 can be measured without the influence of R 3 .
Many trimming devices or resistance measuring instruments with guard pin functions are commonly used.
Resistance measurement and trimming of the circuit shown in the figure can be easily performed.
ところが、厚膜抵抗が二重の閉回路を構成して
いる場合には上記の方法では測定できない。第2
図は厚膜混成集積回路の回路図の一部であり、厚
膜抵抗R1〜R5が二重の閉回路を構成している。
このような回路で抵抗R1をトリミングする場合、
端子T2,T3を測定端子とし、端子T1をガード端
子としても抵抗R4,R5には電流が流れてしまい、
抵抗R1の正確なトリミングができない。端子T4
をガード端子とした場合は抵抗R2,R3に電流が
流れてしまい、やはり抵抗R1の正確なトリミン
グはできない。端子T1とT4を同時にガード端子
にすれば抵抗R1の正確なトリミングが可能であ
るが、ガードピンを2本もつトリミング装置は一
般にない。 However, if the thick film resistor forms a double closed circuit, the above method cannot be used for measurement. Second
The figure is a part of a circuit diagram of a thick film hybrid integrated circuit, in which thick film resistors R 1 to R 5 constitute a double closed circuit.
When trimming resistor R 1 in such a circuit,
Even if terminals T 2 and T 3 are used as measurement terminals and terminal T 1 is used as a guard terminal, current will still flow through resistors R 4 and R 5 .
Precise trimming of resistor R1 is not possible. Terminal T 4
If R is used as a guard terminal, current will flow through resistors R 2 and R 3 , and accurate trimming of resistor R 1 will not be possible. If the terminals T 1 and T 4 are used as guard terminals at the same time, accurate trimming of the resistor R 1 is possible, but there is generally no trimming device that has two guard pins.
そこでこのような二重の閉回路を含む厚膜混成
集積回路の場合、第3図のように、例えば端子
T4を端子T4′とT4″に分割して二重の閉回路をな
くしておき、厚膜抵抗のトリミング終了後、組立
てのときに、チツプコンデンサ等の部品を利用し
て端子T4′とT4″を接続する。第4図は厚膜混成
集積回路のパターン図の一部であり、上記の分割
パターンの接続方法を示している。第4図におい
て1はセラミツク基板、2は電極パターン、3は
チツプコンデンサ、4は半田である。厚膜抵抗の
トリミング時には端子T4′とT4″は非接続であり、
トリミング終了後、チツプコンデンサ3を搭載
し、半田4によりチツプコンデンサ3の電極とセ
ラミツク基板1上の電極2とを接続する時に、半
田4により端子T4′とT4″を接続する。 Therefore, in the case of a thick film hybrid integrated circuit including such a double closed circuit, for example, as shown in Figure 3, the terminal
Divide T 4 into terminals T 4 ′ and T 4 ″ to eliminate double closed circuits, and after trimming the thick film resistor, use components such as chip capacitors to connect terminal T 4 during assembly. ′ and T 4 ″. FIG. 4 is a part of a pattern diagram of a thick film hybrid integrated circuit, and shows a method of connecting the above-mentioned divided patterns. In FIG. 4, 1 is a ceramic substrate, 2 is an electrode pattern, 3 is a chip capacitor, and 4 is solder. When trimming thick film resistors, terminals T 4 ′ and T 4 ″ are not connected,
After trimming, the chip capacitor 3 is mounted, and when the electrode of the chip capacitor 3 and the electrode 2 on the ceramic substrate 1 are connected by the solder 4, the terminals T 4 ' and T 4 '' are connected by the solder 4.
ところが端子T4′,T4″は端子T5等の通常の部
品取付パターンと比較すると電極パターンとチツ
プ部品との重なり部分の面積が小さく、半田付性
が悪い。特に部品の搭載位置がずれた場合、端子
T4′あるいはT4″いずれかに半田がつかないとい
う半田付不良がおこるという欠点がある。 However, compared to normal component mounting patterns such as terminal T 4 ′ and T 4 ″, the overlapping area between the electrode pattern and the chip component is small, and the solderability is poor. In particular, the mounting position of the component may be misaligned. If the terminal
There is a drawback that soldering failure occurs in that the solder does not stick to either T 4 ′ or T 4 ″.
本発明の目的は厚膜抵抗が二重の閉回路を構成
している厚膜混成集積回路においても、組立時の
半田付性を悪化させず、しかも各々の厚膜抵抗を
精度良くトリミングできる、厚膜抵抗のトリミン
グ方法を提供することである。 The purpose of the present invention is to prevent the solderability during assembly from deteriorating even in a thick film hybrid integrated circuit in which thick film resistors form a double closed circuit, and to trim each thick film resistor with high precision. An object of the present invention is to provide a method for trimming a thick film resistor.
本発明は二重の閉回路内の厚膜抵抗の一部を分
割して直列接続し、分割した各々の厚膜抵抗を
別々にトリミングすることにより、閉回路を切断
することなく、トリミングを可能にするものであ
る。 The present invention enables trimming without cutting the closed circuit by dividing a part of the thick film resistors in a double closed circuit, connecting them in series, and trimming each divided thick film resistor separately. It is meant to be.
本発明の実施例を第5図,第6図により説明す
る。第5図は厚膜混成集積回路の回路図、第6図
はそのパターン図であり、第2図と等価である。
すなわち、第2図の抵抗R1を第5図では二本の
抵抗R1′とR1″に分割し、直列接続して、R1′+
R1″=R1となつている。このような構成にするこ
とにより、抵抗R1′をトリミングする場合は端子
T2とT5を測定端子とし、端子T3をガード端子に
することにより、他の抵抗の影響なくトリミング
可能である。また抵抗R1″をトリミングする場合
も同様に、端子T5とT3を測定端子とし、端子T2
をガード端子とすることにより、トリミング可能
である。その他の抵抗も同様の方法で、すべて、
他の抵抗の影響なくトリミング可能である。 An embodiment of the present invention will be explained with reference to FIGS. 5 and 6. FIG. 5 is a circuit diagram of a thick film hybrid integrated circuit, and FIG. 6 is a pattern diagram thereof, which is equivalent to FIG. 2.
That is, the resistor R 1 in Fig. 2 is divided into two resistors R 1 ′ and R 1 ″ in Fig. 5, connected in series, and R 1 ′+
R 1 ″=R 1. With this configuration, when trimming the resistor R 1 ′, the terminal
By using T 2 and T 5 as measurement terminals and using terminal T 3 as a guard terminal, trimming can be performed without being affected by other resistances. Similarly, when trimming the resistor R 1 ″, use terminals T 5 and T 3 as measurement terminals, and terminal T 2
By using this as a guard terminal, trimming is possible. In the same way, all other resistors are
It can be trimmed without being affected by other resistances.
本実施例によれば、端子を分割し、組立時にチ
ツプ部品を利用して分割パターンを接続するとい
う方法を用いていないので、半田付性を悪化させ
ることなく、すべての厚膜抵抗をトリミング可能
にできる。 According to this embodiment, all thick film resistors can be trimmed without deteriorating solderability because the method of dividing the terminal and connecting the divided patterns using chip components during assembly is not used. Can be done.
以上述べた本発明によれば、厚膜抵抗の二重の
閉回路を含む厚膜混成集積回路においても、二重
の閉回路のないものと同等の精度で厚膜抵抗をト
リミングでき、しかも閉回路内の端子を分割する
必要がなくなるため、組立時に搭載部品の半田付
性を悪くすることがない。したがつて、組立時の
半田付不良の低減の効果がある。 According to the present invention described above, even in a thick film hybrid integrated circuit including a double closed circuit of thick film resistors, the thick film resistor can be trimmed with the same precision as a circuit without a double closed circuit, and the Since there is no need to divide the terminals in the circuit, the solderability of the mounted components will not be impaired during assembly. Therefore, there is an effect of reducing soldering defects during assembly.
第1図〜第3図は厚膜混成集積回路の一部を示
す回路図、第4図は厚膜混成集積回路のパターン
図、第5図は本発明の厚膜混成集積回路の一部を
示す回路図である。第6図は第5図の回路図に対
応する厚膜混成集積回路のパターン図である。
1…セラミツク基板、2…電極パターン、3…
チツプコンデンサ、4…半田、5…抵抗体パター
ン。
Figures 1 to 3 are circuit diagrams showing a part of a thick film hybrid integrated circuit, Figure 4 is a pattern diagram of a thick film hybrid integrated circuit, and Figure 5 is a part of a thick film hybrid integrated circuit of the present invention. FIG. FIG. 6 is a pattern diagram of a thick film hybrid integrated circuit corresponding to the circuit diagram of FIG. 5. 1... Ceramic substrate, 2... Electrode pattern, 3...
Chip capacitor, 4...solder, 5...resistor pattern.
Claims (1)
回路を構成している厚膜混成集積回路において、
上記閉回路内の一本以上の厚膜抵抗を二本以上の
直列の厚膜抵抗に分割して形成し、各々の抵抗を
別々にトリミングすることを特徴とする厚膜抵抗
のトリミング方法。1. In a thick film hybrid integrated circuit in which thick film resistors formed by printing constitute a double closed circuit,
A method for trimming a thick film resistor, comprising dividing one or more thick film resistors in the closed circuit into two or more series thick film resistors, and trimming each resistor separately.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57001825A JPS58119608A (en) | 1982-01-11 | 1982-01-11 | Method of trimming thick film resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57001825A JPS58119608A (en) | 1982-01-11 | 1982-01-11 | Method of trimming thick film resistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58119608A JPS58119608A (en) | 1983-07-16 |
JPS634922B2 true JPS634922B2 (en) | 1988-02-01 |
Family
ID=11512335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57001825A Granted JPS58119608A (en) | 1982-01-11 | 1982-01-11 | Method of trimming thick film resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58119608A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58153704U (en) * | 1982-04-09 | 1983-10-14 | 関東自動車工業株式会社 | Mounting clips for automotive exterior parts |
JPS62174902A (en) * | 1986-01-28 | 1987-07-31 | 太陽誘電株式会社 | Trimming of thick film resistance element |
JPS62299002A (en) * | 1986-06-18 | 1987-12-26 | 松下電器産業株式会社 | Electric circuit with trimmed resistor |
-
1982
- 1982-01-11 JP JP57001825A patent/JPS58119608A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58119608A (en) | 1983-07-16 |
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