JPS6346439B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic performance device, and more particularly to an improvement in the process of setting sound generation timing (step timing).

Conventional automatic rhythm performance devices allow a performer to arbitrarily program the timing at which a sound should be sounded and the type of percussion instrument that should be sounded at that timing, and based on this program, perform an automatic rhythm performance that matches the performer's preference. better known.
Furthermore, automatic performance devices have been known in which data representing pitches are programmed in accordance with sound generation timings, and the pitch data is converted into musical tone signals during playback to generate sounds. However, in the conventional automatic performance devices described above, the resolution of sound timing (the minimum unit of sound timing; this is called a step) is fixed to a specific note such as an eighth note or a sixteenth note. It was impossible to play with shorter notes. By increasing the resolution of the pronunciation timing, it becomes possible to play fairly short notes, but this increases the number of steps that make up one measure or one pattern (for example, if you increase the resolution by one rank, you can change the performance from a 16th note to a 32nd note). , the number of steps that make up one measure or pattern doubles), and the device configuration increases accordingly. For example, if a step switch corresponding to each step is provided individually and the sound timing is programmed by operating this step switch, with conventional equipment, a large number of step switches must be prepared in order to ensure high resolution. Must be. but,
In reality, it is impossible to increase the number of step switches without limit in response to the demand for improved resolution in terms of installation space and cost. Therefore, in order to increase the resolution with a limited number of switches (number of steps), it is necessary to shorten one cycle of the performance pattern, and there is a risk that the performance will become monotonous. Furthermore, since performances that require high resolution are not always performed, many steps are wasted in performances that do not require high resolution. Also, since one step is fixed to a specific note, if you use tuplets and regular notes together in a single automatic performance sequence, the time signature will shift, and you cannot use tuplets and regular notes together. Ta.

This invention was made in view of the above points,
The present invention aims to provide an automatic performance device in which the resolution of sound generation timing can be changed arbitrarily without fixing it to a specific note. According to this invention, the number of steps corresponding to one beat is arbitrarily set as reference size information, and the cycle of one step is calculated based on this reference size information and tempo information (number of beats per unit time). The present invention is characterized in that the automatic performance steps are advanced at a speed corresponding to this calculation result. Assuming that the reference size information is Be, the tempo information is Tc, and an arbitrary calculation constant is K, the above calculation is performed according to the following formula.

Step period = K/Tc×Be...(1) Assuming that tempo information (number of beats per unit time) Tc is constant, as the reference size (number of steps per beat) Be increases, the step period becomes shorter; , when the reference size Be decreases, the step period becomes longer. Therefore, even if the reference size (number of steps per beat, ie, resolution of sound generation timing) changes during the performance, the tempo (length of one beat) of the song does not change, and no time signature deviation occurs. In the embodiments described later, the term "beat size" is used as the reference size. The beat size represents the number of quarter note steps.

By changing the reference size Be as appropriate, you can arbitrarily change the resolution of the sound timing (the type of note that corresponds to one step), so you can use the limited number of steps effectively and without waste. Automatic performance with high resolution or one cycle of a pattern can be performed automatically.
Furthermore, it becomes possible to use both tuplets and ordinary notes in a single automatic performance sequence, making it possible to create a free automatic performance program.

This invention is shown in functional block diagrams as shown in FIGS. 30 to 34.

FIG. 30 shows the first invention, which includes step setting means 100 for setting and storing steps at which musical tones are to be produced among a specific number of steps corresponding to each production pattern of a performance pattern; Beat size setting means 200 for setting a beat size representing the number of steps constituting a specific note)
and tempo setting means 300 for setting the performance tempo.
a calculation means 400 for determining a step progression speed based on the set performance tempo and the beat size; and a performance pattern set by the step setting means 100 according to the determined step progression speed. The apparatus includes a readout means 500 for sequentially reading out the setting state of each step, and a musical tone generating means 600 for generating a musical tone corresponding to the readout setting state of sound generation for each step.

Here, the step setting means 100 comprises a step storage section that stores steps to be sounded for each of a plurality of performance patterns having an arbitrary number of steps, and the beat size setting means 100
00 comprises a beat size storage unit that sets and stores a beat size for each performance pattern stored in the step storage unit, and the calculation means 400 is configured to set and store a beat size for each performance pattern stored in the step storage unit. The beat size set corresponding to the pattern is used for the calculation, and the reading means 500 is configured to read the step to be generated corresponding to the selected pattern from the step storage section. Can be done.

Further, the step setting means 100 includes a step selection means for selecting a desired step to be generated from a specific number of steps corresponding to each sound generation timing, and a step selection means for selecting a desired step to be generated from among a specific number of steps corresponding to each sound generation timing, and a step selection means for selecting a desired step to be generated from among a specific number of steps corresponding to each sound generation timing. The beat size setting means 200 includes a beat size selection means for arbitrarily selecting a beat size, and a beat size selection means for storing the beat size selected by the beat size selection means. and a rewritable beat size storage section.

The tempo setting means 100 also includes a tempo selection switch that selects the number of beats (or a specific number of notes) within a predetermined time, and a plurality of calculation keys that increase or decrease the number selected by the switch at a predetermined ratio. The arithmetic means 400 may be configured to be a means for calculating a step progression speed based on the beat size and the selected states of the tempo selection switch and the arithmetic key.

FIG. 31 shows the second invention, which includes a step setting means 101 for setting and storing steps at which musical tones are to be generated among a specific number of steps corresponding to each generation order of a performance pattern; A pattern size setting means 701 for setting a pattern size representing the number of steps forming a beat, a beat size setting means 201 for setting a beat size representing the number of steps forming one beat (or a specific note), and a tempo setting means 201 for setting a performance tempo. a setting means 301, an arithmetic means 401 for calculating a step progression speed based on the set performance tempo and the beat size, and a calculation means 401 for determining the step progression speed based on the set performance tempo and the beat size; A reading means 501 that sequentially reads out the setting state of each step of a performance pattern, a musical sound generating means 601 that generates a musical tone corresponding to each read step setting state, and the reading means 50
The pattern readout control means 801 sets one cycle of readout step progression according to the pattern size.

Here, the pattern readout control means 801
The readout means 501 may be configured to control the readout means 501 so as to return the step progress to the initial step when the readout steps by the readout means 501 have progressed to the number of steps represented by the pattern size.

Further, the step setting means 101 consists of a step storage section in which steps to be produced are stored in advance, the pattern size setting means 701 is comprised of a pattern size storage section in which pattern sizes are stored in advance, and the beat size setting means 201
can be configured to include a beat size storage section in which beat sizes are stored in advance.

Further, the step setting means 101 includes a step selection means for selecting a desired step to be generated from a specific number of steps corresponding to each sound generation timing, and a step selection means for selecting a desired step to be generated from among a specific number of steps corresponding to each sound generation timing, and for selecting a step selected by the step selection means. The pattern size setting means 701 includes a rewritable step storage section for storing pattern size, and a pattern size selection means for arbitrarily selecting a pattern size, and a pattern size selection means for storing the pattern size selected by the pattern size selection means. The beat size setting means 201 includes a beat size selection means for arbitrarily selecting a beat size, and a beat size selected by the beat size selection means. and a rewritable beat size storage section.

FIG. 32 shows the third invention, which includes a step storage section 102 that stores steps that should produce musical tones among a specific number of steps corresponding to each sound generation timing of a performance pattern, and one beat (or a specific note). ), a tempo setting means 302 for setting a performance tempo, and an arithmetic means 402 for calculating a step progression speed based on the performance tempo and the beat size. and reading means 502 for reading out the step storage section 102 according to the determined step progression speed;
Sound information regarding the sound to be generated is set corresponding to each step to be generated, and the sound information is stored in the step storage unit 1.
The tone setting means 702 outputs sound information in response to the read output of No. 02, and the musical sound generating means 602 generates musical tones based on the output sound information.

Here, the tone setting means 702 sets information representing the type of percussion instrument, information representing the intensity of the sound, and information representing the duration of the sound as information regarding the sound to be generated. The percussion instrument sound source can be configured to be driven based on the above information.

Further, the tone setting means 702 is configured to set information representing a pitch as information regarding the sound to be generated, and the musical tone generating means 602 is configured to be a means for generating scale tones based on the above information. can do.

Further, the musical tone generating means 602 includes a multi-channel speaker sounding means, and the tone setting means is configured to set at least information indicating the sound generation channel by the speaker sounding means as information regarding the sound to be generated. be able to.

The tone setting means 702 also includes a plurality of sound information selection means corresponding to a plurality of types of information regarding sounds to be generated, and a plurality of sound information selection means corresponding to each step in which the information selected by the sound information selection means is to be produced. and a rewritable tone storage section for storing the tone information.

FIG. 33 shows a fourth invention, which includes a sequence storage section 803 that stores information for sequentially instructing performance patterns as automatic performance progresses, and a pattern size that represents the number of steps constituting one performance pattern. a pattern size storage section 703 that stores a plurality of performance patterns and reads out a pattern size corresponding to the performance pattern specified by the information read out from the sequence storage section 803; a beat size storage section 203 that stores a beat size representing the number of steps constituting the beat size corresponding to each of the plurality of performance patterns; and a beat size storage section 203 that stores at least a step to be generated corresponding to each of the plurality of performance patterns. The pronunciation information storage unit 103 that has been set, a tempo setting unit 303 that sets the performance tempo, and a step based on the performance tempo set by the tempo setting unit 303 and the beat size read from the beat size storage unit 203. a calculation means 403 for calculating the progress speed; and a calculation means 403 for calculating the step progress speed according to the step progress speed determined.
The step memories of the pronunciation information storage section 103 corresponding to the performance pattern specified by the information read out from the playback section 103 are sequentially read out, and one cycle of the read step progress is stored in the pattern size storage section 7.
reading means 503 that is set based on the pattern size read out from the sound generation information storage section 103; The pronunciation information storage section 10
a sequence advancing means 903 that advances the readout of the sequence storage section 803 every time one cycle of the readout step progression of No. 3 is completed;
03, 203, 703, and 803, and a writing means 1003 for writing desired data.

Here, the sequence incrementing means 903 includes a sequence counter that specifies a read address of the sequence storage section 803, and includes a sequence counter that specifies a read address of the sequence storage section 703 and the beat size storage section 20.
3 reads out the stored contents using the performance pattern instruction information read out from the sequence storage section 803 as an address according to the contents of the sequence counter, and the pronunciation information storage section 103 reads out the performance pattern instruction information read out from the sequence storage section 803 according to the contents of the sequence counter. A pattern to be read is specified by the performance pattern instruction information, and the step memory corresponding to the specified pattern is read out according to the step progression speed determined by the calculation means 403, and the musical sound generation means 603 can be configured to generate a musical tone at the timing of the step to be generated based on this readout.

Further, the reading means 503 is configured to return the step progress to the initial step when the reading step from the pronunciation information storage section 103 has progressed to the number of steps represented by the pattern size read from the pattern size storage section 703. At the same time, the sequence counter can be configured to be incremented by one step at this time.

Further, the pronunciation information storage unit 103 includes a step storage unit that stores steps to be generated in correspondence with each of a plurality of performance patterns, and a step storage unit that stores sound information regarding sounds to be generated in correspondence with the steps to be generated. The reading means 503 can be configured to generate musical tones based on the tone information read from the tone storage section corresponding to the step to be generated.

FIG. 34 shows the fifth invention, which includes a step storage section 104 that stores steps at which musical tones are to be produced among a specific number of steps corresponding to each sound generation timing of a performance pattern, and one beat (or a specific note ), a tempo setting means 304 for setting a performance tempo, and an arithmetic means 404 for calculating a step progression speed based on the performance tempo and the beat size. a readout means 504 for reading out the step storage section in accordance with the determined step progression speed; a musical sound generation means 604 for generating a musical tone in response to the readout output of the step storage section 104; and a gradual change in volume. and a control means 704 that gradually controls the volume of the sound generated by the musical sound generating means 604 in accordance with the setting of the gradual volume change setting means 804.

Here, the volume gradual change setting means 804:
It consists of a gradual increase selection key, a gradual decrease selection key, and a rate of change selection switch, and the control means 704 is a circuit that generates a gradual increase type or gradual decrease type envelope signal in response to the selection operation of the selection key and the selection switch. , and a circuit that commonly controls the volume of the generated sound according to the envelope signal.

Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

DESCRIPTION OF THE OVERALL CONFIGURATION OF EMBODIMENT FIG. 1 is a schematic block diagram showing the overall structure of an embodiment of an automatic performance apparatus according to the present invention. 1st
In the automatic performance device 10 shown in the figure, a microcomputer 11 is used to control the overall operation of the device 10, such as writing an automatic performance program and executing automatic performance according to the program. The main panel 12 includes a program key switch for inputting data etc. for an automatic performance program, and a command key switch for instructing writing and reading of an automatic performance program (execution of automatic performance), etc. For example, as shown in FIG. These key switches are arranged as shown. The panel interface circuit 13 exchanges information with the microcomputer 11 via a data bus 14 and a command bus 15, and detects and scans the pressed state of each key switch on the main panel 12, or is provided corresponding to each key switch. The display drive of the light-emitting elements is performed. That is, when a scanning command is given to the command bus 15, the pressed state of each key switch on the main panel 12 is detected and scanned, and data representing the pressed keys is supplied to the data bus 14 and taken into the microcomputer 11. Also, command bus 1
When a display command is given to the key switch 5, the light emitting element of the key switch corresponding to the data given from the microcomputer 11 to the data bus 14 is driven for display.

Microcomputer 11 includes a central processing unit (CPU) 16 and a storage unit 17.
As is well known, a central processing unit (CPU) 16 decodes a control program stored in a storage unit 17 and controls reading or writing of the storage unit 17 or transmits information using the data bus 14 and command bus 15. It includes a control unit that controls transmission and reception, a calculation unit, a program counter, a register for temporary storage, etc. The storage unit 17 is a read-only memory (hereinafter referred to as read-only memory).
(hereinafter referred to as ROM) and random access memory (hereinafter referred to as
An example of the memory map of this storage unit 17 is shown in FIG.

The monitor panel 18 is generally provided as an accessory to a microcomputer, and key switches provided on the monitor panel 18 can also be used to write or read automatic performance programs. By operating this monitor panel 18, automatic performance data read from the microcomputer 11 can be recorded on an external recording device (magnetic tape, etc.) 19.
The automatic performance data given from the microcomputer 11 is written to the microcomputer 11.

The decoder 20 takes in data (data for generating musical tones) supplied from the microcomputer 11 to the data bus 14 based on instructions given from the microcomputer 11 via the command bus 15, and decodes this data.

X sound source channels 21-1 to 21-X
can generate one musical tone each, and if all sound source channels 21-1 to 21-X are driven, a maximum of X tones can be generated simultaneously. Incidentally, in this embodiment, it is assumed that the automatic performance device 10 is an automatic rhythm performance device. In the case of an automatic rhythm performance device, sound source channels 21-1 to 21-X
are provided corresponding to each percussion instrument. This device 10
For example, if the number of types of percussion instruments available in is 32,
X is 32, and 32 sound source channels 21-1 to 21-X (=32) are provided. Data on the data bus 14 is supplied to each of the sound source channels 21-1 to 21-X, respectively. The data taken into the decoder 20 from the data bus 14 includes sound source channel designation data (that is, percussion instrument type designation data).
The decoder 20 decodes this sound source channel designation data and generates any one of data ch1 to chx corresponding to each channel. Channel data ch1 to chx are separately supplied to corresponding sound source channels 21-1 to 21-X. Each of the sound source channels 21-1 to 21-X takes in data from the data bus 14 when channel data ch1 to chx are given, and generates musical sounds (percussion instrument sounds) based on this data.

The decoder 20 also generates a clock signal CK representing the minimum unit of sound generation timing, a crescendo signal CRS representing a gradual increase or decrease in volume, and a diminuendo signal DIM. The CRS/DIM envelope signal forming circuit 22 generates a predetermined gradually increasing or gradually decreasing envelope signal CRS/DIM in response to the cresciendo signal CRS or diminuendo signal DIM supplied from the decoder 20. Clock signal CK and envelope signal CRS/
DIM is all sound source channels 21-1 to 2
Commonly supplied to 1-X. Sound source channel 21
An example of -1 to 21-X is shown in FIG. 15, in which the CRS/DIM envelope signal forming circuit 22
An example is shown in FIG.

This automatic rhythm performance device 10 has two output channels and is capable of stereo performance. Therefore, each sound source channel 21-1 to 21-X is the right channel Rch and the left channel.
It has two Lch output channels. Right channel output of each sound source channel 21-1 to 21-X
The Rch is commonly mixed and applied to the variable resistor 23, and the left channel output Lch is also commonly mixed and applied to the variable resistor 24. Both variable resistors 23 and 24 are adjusted in conjunction with each other by operating the total volume knob Total VR. The musical tones of the left and right channels are generated via amplifiers 25 and 26 and speakers 27 and 28, respectively.

Outline explanation of automatic performance program In order to understand the outline of the automatic performance program, it will be explained with reference to FIGS. 2 to 6. An automatic performance unit of one measure to several measures is called a "pattern." A series of automatic performance steps is called a "sequence". A "sequence" consists of a sequential combination of "patterns". FIG. 2 omits the relationship between "pattern" and "sequence" and shows that "sequence" consists of sequential combinations of patterns a, b, . . . n.

As shown in FIG. 3, the procedure for assembling an automatic performance program is to first program various automatic performance patterns, and then to create a sequence program by sequentially selecting desired ones from among the generally programmed patterns.

The programmed automatic performance pattern is stored in a predetermined storage location. This storage location will be temporarily referred to as "pattern RAM.""pattern
The concepts of ``page'' and ``pattern'' are used to index (specify) the storage location of each pattern in ``RAM''. That is, programmed automatic performance patterns are indexed by a combination of "page" and "pattern." Figure 4 shows an example of the pattern RAM index concept.
Although 64 automatic performance patterns can be stored (programmed) in the RAM, there are only 8 types of indexes, PT1 to PT8, and the concept of ``pattern'' allows only 8 patterns to be indexed. However, the index concept of "page" has eight types from page 1 to page 8, and eight "patterns" can be indexed per page. Therefore,
By combining ``page'' and ``pattern,'' it is possible to index the storage locations for 64 types of automatic performance patterns.

The sequence program stores data representing "pages" and "patterns PT1 to PT8" for indexing desired automatic performance patterns in a dedicated storage device (temporarily referred to as sequence RAM).
are assembled by sequentially storing them. FIG. 5 is a diagram showing an example of the structure of a sequence program to be stored (written) in the sequence RAM, and "sequence number" indicates the sequence progression order. Each sequence number (abbreviation of sequence number, same below)
Desired page data and pattern PT1 corresponding to
~Sequence programming is performed by writing PT8 data. In Figure 5, the maximum is 128
Although a sequence can be programmed up to steps, the number of steps that make up one sequence is arbitrary.

When performing automatic performance, page data and pattern data are read out in order from each sequence number according to a sequence counter (not shown), and a pattern is created according to the read page data and pattern data.
An automatic performance pattern is read from RAM and musical tones are generated according to this pattern.

Next, programming of one automatic performance pattern will be explained with reference to FIG. In this embodiment, one automatic performance pattern can be programmed using a maximum of 64 steps. One step is the minimum unit of sound timing. The 64 steps shown in FIG. 6, steps 1 to 64, correspond to the time order. Step 1 appears the earliest and step 64 the slowest. Therefore, by specifying the step number, it is possible to specify the timing at which the sound should be produced (for example, at what beat the sound should be produced).

The note corresponding to one step in the automatic performance pattern you are trying to program and the length of that pattern are determined by the "beat size" and "pattern size".
Set by. "Beat size" represents the number of steps corresponding to the length of a quarter note, and "pattern size" represents the number of steps constituting one pattern. For example, if "Beat Size" is set to 4 steps, 1 step corresponds to a 16th note. Furthermore, when the "beat size" is set to three steps, one step corresponds to a triplet. The length of one step, that is, the step period, changes at any time depending on tempo information and beat size.
This step period is determined by the calculation formula (1) above.

For example, if you create a program that specifies the beat size as 4 steps, the pattern size as 16 steps, and the sound timing as steps 1, 5, 7, 9, 13, and 15, you will get a pattern as shown in Figure 6 using musical notes. It will be done. When programming an automatic performance pattern, in addition to the above-mentioned elements, the timbre (type of percussion instrument) of the sound to be generated at each sound generation timing, the length of the sound, and the intensity of the sound are also specified.

Explanation of Key Arrangement on Main Panel FIG. 7 is a top view of the main panel 12, and the small squares indicate the upper surfaces (key tops) of the keys on the key switch. A circle drawn above each key switch indicates a light emitting element corresponding to the key switch. The display drawn near the bottom or top of each key switch (STEP, ×2, ÷
2, etc.) represents the meaning (function) of the key switch. The hatched keys are command keys, which are used to issue commands for writing or reading automatic performance programs.
The other keys are program keys. However, the seesaw type switch labeled "Power SW" is the power switch, and the knob labeled "Total VR" is the variable resistor 23, 24 in Figure 1.
This is the overall volume knob for adjusting the
One is not a programming key.

(About command keys) The key displayed as "WT" is a light key, and is a key operated when instructing writing of an automatic performance program.

"CE" is the cancel enable key,
Some of the written data (size data described later,
Operated when erasing tone data, sequence data, etc.).

"CP" is a cancel pattern key, which is operated to erase all desired performance patterns from the written automatic performance program.

"RESET" is a reset key, which is operated when setting initial conditions for executing automatic performance or when stopping automatic performance and returning to initial conditions.

"RUN/STOP" is a run/stop key, which is operated to instruct reading of an automatic performance program, that is, execution of automatic performance. this key
By repeatedly pressing RUN/STOP, the RUN state (automatic performance execution) and STOP state (play stop) are alternately switched.

``BACK'' is a back key, and ``FWD'' is a forward key, which are operated to command forward or backward steps in a program. Back key BACK instructs to go backwards, forward key
FWD directs forward movement.

Light-emitting elements are provided for the cancel enable key CE and the cancel pattern key CP, and are not provided for the other command keys.

(About the program keys) The 64 keys arranged horizontally in the area labeled "STEP" are step keys, and each key has a number from 1 to 64 attached to the top surface. The step keys STEP from 1 to 64 correspond to steps 1 to 64, which correspond to the minimum unit of sound timing of the automatic performance pattern. The step key STEP is operated to specify the timing of sound production (step specification). The step key STEP is also used when setting the above-mentioned "beat size" and "pattern size". Furthermore, the light emitting element attached to the step key STEP not only displays the step or size, but also serves as the aforementioned "page" display. In the case of step (sounding timing) display, the step at which the light emitting element is lit corresponds to the sounding timing. In the case of size display, the number of the step where the light emitting element is lit corresponds to the number of steps in the "beat size" or "pattern size". In the case of page display, the number of the step where the light-emitting element lights up is the "page".
corresponds to the number. Therefore, in the case of page display, only the light emitting elements corresponding to any one of steps 1 to 8 are lit.

8 keys PT1 to PT8 arranged horizontally in the area where "PATTERN SELECT" is displayed
is the ``pattern'' index concept mentioned above.
This is a pattern select key for selecting and instructing PT1 to PT8.

The X keys (for example, 32 keys) arranged in the frame labeled "INSTRUMENT SELECT" are instrument select keys, and each key is generated in each sound source channel 21-1 to 21-X in Figure 1. It corresponds to the types of percussion instruments that can be used (cymbals, maracas, etc. as illustrated in FIG. 7). This key is operated to specify the type of percussion instrument sound to be generated at each sound generation timing.

The four keys arranged vertically in the area labeled "ACCENT" are accent keys, which are operated to specify the intensity of the sound to be generated at each pronunciation timing. The symbols "ff", "f", "n", and "p" displayed below each accent key represent the strength selected by those keys, such as "Fuortessimo (ff)" and "Fuortessimo (ff)" (f),” “normal (n),” and “piano (p).”

The four keys arranged vertically in the area labeled "DURATION" are duration keys, which are operated to specify the duration of the sound to be generated at each sound generation timing. The numbers "8" and "4" displayed on the bottom of each duration key,
"2" and "1" represent the length of the duration selected by those keys, and this number corresponds to the number of steps.

Four keys "SEQ", "SIZE", "PTRN" arranged in the frame labeled "PROGRAM",
"CHCK" is a mode key operated when creating (writing) a program.

The size mode key SIZE is operated when writing "beat size" and "pattern size". The pattern mode key PTRN is operated when writing an automatic performance pattern. The sequence mode key SEQ is operated when writing an automatic performance sequence. The check mode key CHCK is operated when checking a created program.

The three keys arranged in a row horizontally where "CHANNEL" is displayed are channel select keys, "L" is the key to select the left channel,
"R" is a key for selecting the right channel, and "C" is a key for selecting both channels. This key L,
By operating C and R, the output channel (Lch, Rch) of the sound that should be generated at each sound timing
Specify.

The key switch labeled "SSET" is a start set key, and is a mode key for setting the performance start position (sequence position and step position) in the RUN state (when performing automatic performance).

The key switch labeled "REPEAT" is a repeat key, which is operated to repeat the same pattern in the RUN state (while automatic performance is in progress), and serves as an interrupt function for the programmed automatic performance sequence. .

The knob labeled "TEMPO" is a tempo selection switch, and tempo information is generated according to the operating position of this tempo selection switch.
The two key switches arranged to the right of the tempo selection switch are for changing the tempo selected by the tempo selection switch to double or 1/2. When the key labeled "x2" is on, the tempo is doubled, and when the key labeled "÷2" is on, the tempo is halved.

"DIM" is the diminuendo selection key, "CRS"
is the cresciendo selection key. The knob labeled "RATE" is a rate selection switch that selects the deiminuendo or cresciendo rate.

Explanation of Memory Map FIG. 8 shows a memory map of the storage unit 17 in the microcomputer 11, and addresses are shown in hexadecimal notation. Memory unit 17
includes a RAM section and a ROM section, the control program is stored in the ROM section from addresses "0500" to "08FF", and the RAM section from addresses "0040" to "00FF" is used as a working area. , the RAM section from address "1000" to "18FF" is used as a data area.
Further, a monitor working area and a monitor program area are allocated for monitor devices (monitor panel 18, external recording device 19, etc.).

An example of writing in the working area is shown in FIG. In the working area, 16 bits (0 to F) of data can be stored per address (this applies not only to the working area but also to the entire area of the storage unit 17). The storage location (address) of each bit can be specified by the address (upper address) written in the left column of FIG. 9 and the 16 lower addresses from 0 to F. In the following, when simply referring to an address, it refers to the address (upper address) written in the left column of FIG. 9 (or FIG. 8). If the 16-bit lower address is used for one piece of data, the upper address (ordinary address) alone is sufficient to identify the storage location of that data, but if the 16-bit lower address is different When different types of data are used, a lower address is required in addition to an upper address (normal address) to specify the address of each data.

In the "Name" column of FIG. 9, an abbreviation symbolizing the nature of the data stored at each address is written.
In the "Remarks" column, the meaning of the data stored in each address or the function of the address position is abbreviated.

Address 40-4 in the working area
Up to 7 is used as a display memory section (DISP). This display memory section (DISP)
stores data corresponding to each key on the main panel 12 (FIG. 7). That is, when a key is turned on, "1" is stored in the storage location corresponding to that key. Further, the lighting display of the light emitting elements corresponding to each key on the main panel 12 is performed based on the memory in the display memory section DISP. The 64-bit storage locations from addresses 40 to 43, ie, from DISP 0 to DISP 3, correspond to each step key STEP. address 44 i.e.
Each bit of DISP4 is a start set key.
SSET, repeat key REPEAT, check mode key CHCK, size mode key SIZE, pattern mode key PTRN, sequence mode key
SEQ, and pattern select (PATTERN)
SELECT) corresponds to eight keys PT1 to PT8, respectively. Addresses 45 and 46 ie
The 32-bit memory location of DISP 5 and 6 is for instrument select (INSTRUMENT
SELECT) corresponds to each of the 32 keys.
Each bit of address 47, DISP7, is a tempo double key (x2), a tempo 1/2 key (÷2), a diminuendo selection key DIM, a crescendo selection key CRS, and a channel select key L, C, R. , duration key DURATION8,
4, 2, 1, accent key ACCENT ff, f,
They correspond to n and p, respectively.

Seven bits from bit 9 to F of address 59 (NSEQ) are used as a register to display the sequence number. A sequence number of 128 steps (from 00 to 7F in hexadecimal notation) can be displayed using 7-bit binary data. The combination of an arithmetic unit (ALU) within the central processing unit 16 and the register function at this address 59 constitutes a sequence counter. The sequence number stored at this address 59 (NSEQ) therefore corresponds to the current count value of the sequence counter. .

Seven bits from bit 9 to F of address 5A (CSTEP) are used as a register to display the step count value of the step counter. This step counter (CSTEP) is used to instruct the performance step during the performance RUN state. However, the display of the step counter (CSTEP) does not represent the performance steps themselves, but the number of remaining steps. The maximum number of remaining steps is
64 (hexadecimal 40), which is represented by the 7-bit binary value "1000000". As the playing steps progress, the value of the step counter (CSTEP) is decreased. In Figure 9, “40” in hexadecimal
~01'' indicates that this step counter (CSTEP) is a down counter. Of course, the calculation unit (ALU) within the CPU 16 is responsible for the actual calculation.

The 8 bits from bits 0 to 7 of address 5B are the tempo data buffer register (DTEMPO).
used as. Data corresponding to the step period calculated according to equation (1), ie, tempo data, is stored here. Bit C of address 5B is used as a storage section for the continuation flag CFLG. The continuation flag CFLG is set when the content of DTEMPO, that is, the value of tempo data changes.

The step timing is formed within the central processing unit (CPU) 16 based on the value of tempo data (DTEMPO). There are two timers (oscillators) in the CPU 16 with a 10ms cycle and a 1ms cycle.
The output of either of these timers is selected according to the calculated step cycle size.
The selected timer output is appropriately frequency-divided according to the value of tempo data (DTEMPO) to form a clock (CK) representing step timing.

Bits E and F of address 5B are used as a flag storage section for the 10 ms timer and 1 ms timer.

Bit B of address 5B is used as a storage section for run flag RFLG. This run flag RFLG is set during the performance RUN state.

Address 5C (DSTART) is a part that stores data instructing the start position of automatic performance, 7 bits from bits 2 to 8 store data (DSTEP) representing the performance start step, and bit 9
Data representing a performance start sequence number (SSEQ No.) is stored in the 7 bits from to F.
These start data are input by operating the main panel 12.

Address 5D (DPAGE) is a buffer register that stores page data, and bits A, B,
Any page data from 0 (“000”) to 7 (“111”) is stored in the 3 bits of C. "000" corresponds to one page, and "111" corresponds to eight pages.

The 64 address locations (DSEQ) from address 68 to A7 are used as sequence RAM (see FIG. 5). The sequence RAM stores "page" and "pattern" data, which are index concepts of automatic performance patterns programmed corresponding to each sequence number during sequence programming. Bit 0 of lower address
7 to 7 are storage locations corresponding to odd sequence numbers, and bits 8 to F of the lower address are storage locations corresponding to even sequence numbers. Since two sequence numbers (odd and even) correspond to one address, page data and pattern data corresponding to 128 sequence numbers can be stored using 64 addresses from address 68 to A7. this sequence
The address position for each sequence number in the RAM (DSEQ) is specified by the contents of the sequence counter (NSEQ) at address 59. Note that data ATOP, ASIZE, and ADTA at addresses 55, 56, and 57 shown in parentheses in FIG. 9 will be described later.

FIG. 10 shows the format of data written to the data area (FIG. 8). The type of data written to the data area is "WSIZE",
There are 3 types: "WSTEP" and "WTONE", these 3
One performance pattern is programmed based on the type of data. In other words, the data area corresponds to the pattern RAM described above (see FIG. 4).
The initial "W" in "WSIZE,""WSTEP," and "WTONE" stands for "WORD." 1
A word corresponds to one address (upper address), and is composed of 16-bit data from bits 0 to F. Each bit 0 to F within one word can be specified by a lower address in the same way as the working area described above.

Two bits, bits 0 and 1, are used as mark bits representing the data type. As shown in the diagram, “11” is “WSIZE” and “10” is “WSTEP”
“00” represents “WTONE”.

In "WSIZE," 6 bits from bits 2 to 7 are used to write the "beat size," 7 bits from beat 9 to F are used to write the "beat size," and 7 bits from beat 9 to F are used to write the "beat size." Bits are used to write the "pattern size". In other words, the storage location where "WSIZE" is stored corresponds to the "beat size and pattern size storage section." The data written as the beat size starts from “000001” (01 in hexadecimal, 1 in decimal),
It can be any value up to "100000" (20 in hexadecimal, 32 in decimal), and the maximum beat size is 32 steps. The data written as the pattern size is anything from “0000001” (01 in hexadecimal, 1 in decimal) to “1000000” (40 in hexadecimal, 64 in decimal), and the maximum value of the pattern size is It has 64 steps.

In "WSTEP", 7 bits from 9 to F
Bits are used to write step numbers. The step number corresponding to the desired sound generation timing is written in this "WSTEP". That is,
The storage location where "WSTEP" is stored corresponds to the "step storage section".

Information regarding the sound to be generated at the step specified by the above-mentioned "WSTEP" is written in "WTONE". Five bits from bits 3 to 7 are used to write data INSTR. representing the type of percussion instrument selected by the instrument select key (INSTRUMENT SELECT). Two bits, bits 8 and 9, are used to write data CHAN. representing the output channel (L, C, R). Two bits, A and B, are used to write data ACC. representing accent information (ff, f, n, p) selected by the accent key (ACCENT). The four bits C to F are data DURAT representing the duration (8, 4, 2, 1) of the note selected by the duration key (DURATION).
It is used for writing. Further, bit 2 is used as a storage section for data flag DFLG. The data flag DFLG indicates that data has been written to "WTONE".
The storage location of "WTONE" corresponds to the "tone storage section".

Data area (address of storage unit 17)
Examples of writing from 1000 to 18FF) are shown in FIGS. 11 and 12. As shown in FIG. 11, in the initial setting, 64 "WSIZE" are written in advance at the lowest 64 address positions (that is, addresses 18BF to 18FF). At this stage, the specific data for "WSIZE" is undetermined, so only the "WSIZE" marking ("11") is performed, and the beat size and pattern size bits are all set to "0".
i.e. as WSIZE, data “C000” (hex)
Write. One "WSIZE" corresponds to one performance pattern, and writing positions for 64 performance patterns are secured by writing 64 "WSIZE". Each of the eight "WSIZE" corresponds to pages 1 to 8 in descending order of addresses.
Furthermore, within one page, patterns PT1 to PT8 correspond to patterns PT1 to PT8 in ascending order of address.

Specific "WSIZE" and "WSTEP",
Writing of "WTONE" is performed as follows. First, a specific "WSIZE" is selected by page designation and pattern designation PT1 to PT8. Write the desired beat size and pattern size in the selected “WSIZE” position. Next, that "WSIZE"
Push up all the data above (younger addresses) one address at a time (move to a younger address), including ``WSTEP''. and the desired step number. Next, all the data above it, including "WSTEP", is pushed up one address at a time to free up an address position for writing "WTONE", and the data of "WTONE" is written in the vacant address position. It's crowded. If you want to produce multiple percussion instrument sounds in the same step, provide as many ``WTONE'' as there are. Thereafter, "WSTEP" and "WTONE" corresponding to the next pronunciation timing are sequentially written in the same manner as described above. When "WSTEP" and "WTONE" related to all sound generation timings in one pattern are written in this way, writing of the program related to one performance pattern is completed.

FIG. 12 shows a state in which writing of the data area is in progress. Under one “WSIZE”, the same number of “WSTEP” as the number of sound timings (#1, #2, #3,
...) are written, and below each "WSTEP" a number of "WTONE"(#1,#2, ...) corresponding to the percussion instrument sound to be sounded at the sounding timing is written. The period from one "WSIZE" to just before the next "WSIZE" corresponds to one pattern.

As writing progresses, the address position of the upper data (stored at a younger address position) is pushed up (to a younger address position) in order. However, by always storing the address where the first data in the data area (that is, "WSIZE" of the first pattern PT1 of one page is located in the pointer register and counting the number of "WSIZE" from this first address position), it is possible to The performance pattern (that is, the one indexed by the page and pattern selection data PT1 to PT8) can be searched.

FIG. 13 shows the structure of data output from the microcomputer 11 to the data bus 14 during the performance RUN state. The types of data output to the data bus 14 are "WTONE" and "WCLOCK". The composition of "WTONE" is the first
As shown in FIG. 0, "WTONE" data read from the data area of the storage unit 17 in response to predetermined steps is supplied to the data bus 14. "WCLOCK" is data that is supplied from the central processing unit 16 to the data bus 14 at each step occurrence timing (regardless of whether or not sound is generated in that step). “WCLOCK” has bit 0 as “1”,
By detecting that bit 0 becomes "1" on the data bus 14, the step timing, that is, the sending timing of the data WCLOCK can be known. Also, bits A and B of WCLOCK contain working area address 47 (DISP
7) The diminuendo signal DIM and cresciendo signal CRS stored in (see FIG. 9) are assigned.

Data WTONE output to data bus 14
and WCLOCK are supplied to the decoder 20 and sound source channels 21-1 to 21-X (see FIG. 1). The decoder 20 decodes the 5-bit instrument select data INSTR. included in the data "WTONE", and generates any one of channel data ch1 to chx corresponding to each percussion instrument as a decoded output. Further, the decoder 20 decodes the data WCLOCK and outputs a step clock signal CK representing the minimum unit of sound generation timing (that is, step timing), and a diminuend signal DIM or a crescendo signal CRS. On the other hand, data "WTONE" is included in each of the sound source channels 21-1 to 21-X from the data bus 14. Channel selection data CHAN, accent data ACC, and duration data DURAT are respectively supplied.

CRS/DIM envelope signal forming circuit In the CRS/DIM envelope signal forming circuit 22 shown in Fig. 14, the decoder 20 (Fig. 1)
The clock signal CK output from the latch circuit 2
9 strobe input (S). Cresciendo signal also output from the decoder 20
CRS or diminuend signal DIM is applied to the data input (D) of latch circuit 29. Therefore,
Signal CRS or DIM is latched in latch circuit 29 in synchronization with the timing at which data WCLOCK is output. The signal CRS or DIM latched in the latch circuit 29 is sent to the ramp waveform generating circuit 30.
is input to specify the slope direction (polarity) of the ramp waveform. Signal CRS specifies rising and signal DIM specifies falling.

The slope rate of the ramp waveform generated from the ramp waveform generation circuit 30 is determined by the main panel 12 (FIG. 7).
The selection is made by rate selection switches RATE arranged in .

With the above configuration, when the diminuendo selection key (DIM) or cresciendo selection key (CRS) is pressed during automatic performance, the slope rate selected by the rate selection switch RATE is used to select the falling type or rising type. A CRS/DIM envelope signal is generated from ramp waveform generation circuit 30. This CRS/DIM signal is commonly input to all sound source channels 21-1 to 21-X.

Description of sound source channels FIG. 15 is a diagram showing an example of one sound source channel 21-1, but other sound source channels 21-
2 to 21-X also have the same configuration. However, the channel data ch1 to chX corresponding to the individual sound source channels 21-1 to 21-X are input.

The sound source channels 21-1 to 21-X include a sound source oscillator 31 that generates a sine wave, a sawtooth wave, or a square wave, and a noise generator 32,
The sawtooth wave or square wave oscillation output is mixed with a signal passed through a voltage controlled filter (hereinafter referred to as VCF) 33, the sine wave oscillation output, and the output of the noise generator 32 at an appropriate ratio using mixing resistors 34, 35, and 36. signal on that channel 21
-1 as a percussion instrument sound source signal. In the other channels 21-2 to 21-X, the mixing ratios by the mixing resistors 34, 35, and 36 are different, and percussion instrument sound source signals of corresponding tones are formed.

Channel data ch1 output from the decoder 20 (FIG. 1) is applied to the preset data load input of the counter 37 and also to the strobe input (S) of the one shot circuit 38 and the latch circuit 39. Duration data DURAT. is supplied to the preset data input of the counter 37 via the data bus 14. Latch circuit 3
9 data input (D) receives output channel data CHAN. and accent data via data bus 14.
ACC. is supplied. The one-shot circuit 38 generates one pulse with a constant time width in synchronization with the rising edge of channel data ch1.

Channel data ch1 is obtained by decoding WTONE, and WTONE is read out only once at the timing of one sound. Therefore, channel data ch1 is a signal that is generated only at the beginning of sound. channel data ch
1 is generated, the data bus 14 is supplied with the WTONE data that generated the channel data ch1, so the duration data DURAT. included in the WTONE data is preset in the counter 37, and
The 2-bit output channel data CHAN. and the 2-bit accent data ACC. included in the WTONE data are latched in the latch circuit 39.

Counter 37 is a down counter, and a clock signal CK from decoder 20 (FIG. 1) is applied to the count input. Every time the clock signal CK is generated, that is, every step, the counter 3
7 subtracts 1 from the preset value (DURAT.),
When the count value becomes 0, the subtraction is stopped. The counter 37 outputs "1" when the count value is a certain value other than 0, and outputs "0" when the count value is 0. Therefore, the output of the counter 37 is the number of steps (8,
4, 2 or 1). For example, if the duration data DURAT. is "1", it is 1.
The output of the counter 37 becomes "1" only during the step, and when the data DURAT. is "8", the output of the counter row becomes "1" during the 8 steps.

Output of counter 37 and one shot circuit 38
The outputs of are input to envelope generators 40 and 41. The envelope generators 40 and 41 generate an envelope waveform called an ADSR (Attack, Decay, Sustain, Release) waveform. For example, when the output of the counter 37 is "1" and the output of the one-shot circuit 38 is "1". At this time, the attack and decay portion waveforms are generated, and then the sustain portion waveforms are generated until the output of the counter 37 falls to “0”, and after the counter 37 output falls to “0”, the release portion waveforms are generated. occurs.

The envelope generators 40 and 41 have different characteristics of generated envelopes. envelope generator 4
The envelope waveform generated from 0 is applied to the oscillation frequency control input of the sound source oscillator 31 and the cutoff frequency (or Q) control input of the VCF 33, and changes the sound source frequency and filter characteristics over time. The envelope waveform generated by the envelope generator 41 is applied to gain control inputs of a voltage controlled amplifier (hereinafter referred to as VCA) 42 for the right channel and a VCA 43 for the left channel. VCA
A mixing resistor 3 is connected to the signal inputs 42 and 43.
The sound source signals mixed at 4 to 36 are input. In addition, the gain control input of VCA42 and 43 has a 14th
Given from the ramp waveform generation circuit 30 shown in the figure.
CRS/DIM signal is input.

Of the 2-bit channel data CHAN. latched in the latch circuit 39, the data R of the bit that selects one, that is, the right channel, is applied to the control input of the VCA 42 for the right channel, and the data L of the bit that selects the other channel, that is, the left channel. Added to the control input of VCA43 for the left channel. VCA4
2 or 43 is turned off when channel data R or L applied to the control input is "0",
Cuts off the input musical tone signal. Also, it is turned on when channel data R or L applied to the control input is "1", and the amplitude of the input musical tone signal is controlled according to the control signals (envelope waveform, CRS/DIM signal, accent signal) applied to other control inputs. Control. When specifying the right channel, data R is “1” and data L is “0”; when specifying the left channel, data R is “0” and data L is “1”; when specifying both channels, data R, Both L's are "1".

The 2-bit accent data ACC. latched in the latch circuit 39 is input to the digital-to-analog converter 44, and the degree of accent (ff, f,
n, p). The output of the digital-to-analog converter 44 is VCA4
2 and 43 control inputs. VCA42
The output of VCA4 is used as the right channel output Rch.
The output of No. 3 is supplied to variable resistors 23 and 24 (FIG. 1) as the left channel output Lch.

Outline of Control Program The flowchart shown from FIG. 16 onwards shows an outline of the control program executed by the microcomputer 11.
This is stored in the control program area No. 7 (FIG. 8). Writing and reading of the automatic performance program is controlled according to this control program.

FIG. 16 is a flowchart of the main program, in which initial setting processing "INITIAL LOAD" is performed after "START".

The processing performed in "INITIAL LOAD" is mainly as follows.

After all the working areas (addresses 0040 to 00FF) of the storage unit 17 are cleared, the data at the predetermined address position is set to the initial value.

In the data area of the storage unit 17, the initial settings (64
Write the WSIZE mark).

A predetermined address of the working area (e.g.
0055, 0056, 0057) are data ATOP, ASIZE,
It is designed to be used as a register for ADTA (Fig. 9). ATOP (first address) is data representing the address where the first data is stored in the data area. ASIZE (size address) is data representing an address where WSIZE data of a pattern designated for writing or reading in the data area is stored. ADTA (data address) is data representing a write or read address in the data area. These data ATOP, ASIZE,
The contents of ADTA change when the write state or read state of the data area changes. In the initial settings, these data ATOP, ASIZE, ADTA
is set to “18BF” (in hexadecimal). 11th
As is clear from the figure, this address "18BF" corresponds to the address of the first data of the initialized data area, and also corresponds to the address of WSIZE of one page, first pattern PT1.

After "INITIAL LOAD", the tempo setting subroutine "ASTEMPO" is executed.
In this subroutine "ASTEMPO", the above (1)
The step period is calculated according to the formula, but since it is not very important at this stage, the details will be described later.

“ASTEMPO” is followed by “DISPLAY”
``SCAN'' and ``KEY SCAN'' processes are executed.

In "DISPLAY SCAN" (display scan processing), the working area (Figure 9)
Display memory section DISP0 to 7 (address
The memory of each bit (0040 to 0047) is read out by scanning at high speed, and the light emitting element (see main panel 12 in FIG. 7) corresponding to the key in which "1" is stored is displayed by lighting. Immediately after "INITIAL LOAD", all of the display memory sections DISP0 to DISP7 are cleared, so the light emitting elements are not turned on.
The reason for performing this “DISPLAY SCAN” process is
This is to notify the operator of the storage status of the display memory units DISP0 to DISP7, that is, the key input status.

In "KEY SCAN" (key scan processing), each key switch (7th
(Figure) is scanned at high speed to detect the on/off state of each key. If there is a key that is turned on, the key input judgment (key input?) will be YES, and the process will proceed to the key group detection distribution process "KEY GROUP TRAP". If no key is turned on, the key input judgment is NO, and the display scan process "DISPLAY
Return to SCAN.

Therefore, only when a key is pressed on the main panel 12, the key group detection distribution process "KEY
GROUPTRAP", and at other times display scan and key scan are repeated at high speed.

Key group detection distribution process “KEY
GROUPTRAP", it is determined whether the pressed key is a command key (the shaded key in FIG. 7) or a program key, and leads to the processing program for each key group.
If the pressed key is a programming key (PRK), the program moves to the programming key processing shown in block 45, where processing corresponding to the pressed key is performed, and then jumps to "IDL" (idling). The position of idling IDL is the starting position of the display scan process "DISPLAY SCAN" of the main program (FIG. 16). A detailed example of the program key processing indicated by block 45 is shown in FIG.

If the pressed key is a command key (CMK), it is determined whether the key is a RUN/STOP key or a RESET key (block 46), and if YES, command key distribution processing "COMMAND" is performed. KEY TRAP”
If NO, “RUN FLG”
ON? ” (block 47). "RUN
FLG ON? '', it is determined whether the run flag RFLG (FIG. 9) stored in bit B of address 5B of the working area is ``1''. If “RUN FLG ON?” is NO, move to “COMMAND KEY TRAP” and YES
When , it jumps to idling IDL. The reason for providing judgment blocks 46 and 47 is that automatic performance
When in the RUN state (run flag RFLG is ON), command keys other than the RUN/STOP key or the RESET key (BACK, FWD, CP, CE,
This is to disable WT). In other words, RUN
Sometimes these command keys BACK, FWD, CP,
If CE and WT are pressed, decision block 46
is NO, 47 is YES, and the state is returned to idling IDL.

Command key distribution processing “COMMAND KEY
TRAP”, the pressed key is the command key.
BACK, FWD, RESET, CP, CE, WT,
Detects whether it is RUN/STOP,
Guides you to a program that corresponds to the type of key you press.

The pressed key is the BACK key, FWD key,
If it is the RESET key, CP key, or CE key, the process moves to command key processing shown in block 48, where the pressed key (either BACK to CE) is pressed.
After executing the corresponding processing, jumps to idling IDL. A detailed example of command key processing block 48 is shown in FIG.

If the pressed key is the write key WT, the process moves to the write program WTP shown in FIG. 19. Press key is RUN/Stop key RUN/
If it is STOP, the program moves to the run/stop program R/STP shown in FIG.

In FIG. 17, the key distribution process “KEY
TRAP", the type of program key (PRK) pressed (STEP, SSET, REPEAT,
...) and guides you to a program appropriate for that type. "CHANGE DISPLAY" is a display change processing block, which sets the memory bit corresponding to the pressed key in the display memory section DISP0 to DISP7 (Fig. 9) of the working area to "1" (changes from "0" to "1"). process). For example, if the accent key ACCENT (Fig. 7) corresponding to fortissimo "ff" is pressed, the key shown in block 49 of Fig. 17 is
Address 47 by CHANGE DISPLAY processing
"1" is stored in bit C (see FIG. 9) of (DISP7), and it is stored that the accent key ACCENT of "ff" has been pressed.

In the CHANGE DISPLAY processing block 50 for the tempo double key "x2" and the 1/2 key "÷2", "x2" and "÷2" are stored exclusively. In other words, if one of the keys "×2" or "÷2" is already stored and the other key "÷2" or "×2" is pressed, the previous memory will be canceled and a new one will be created. Only the pressed keys are memorized. Therefore, the display memory section
In DISP7, "1" is never stored in the "x2" and "÷2" storage bits at the same time.
Dayminuendo key DIM and Cresciendo key
The CHANGE DISPLAY processing block 51 for CRS also exclusively processes the storage of "DIM" and "CRS" in the display memory section DISP7, similar to the block 50 described above.

In the KEY TRAP output display in Figure 17,
"REP." is the repeat key REPEAT,
"PTRNSLCT" is the pattern select key
PATTERN SELECT, "INSTR." is the instrument select key INSTRUMENT
SELECT, "CHAN." is the channel select key CHANNEL, "DURAT." is the duration key DURATION, "ACC." is the accent key
ACCENT is omitted.

In Fig. 17, size mode keys SIZE,
The pattern mode key PTRN and sequence mode key SEQ are collectively referred to as "PGM" (meaning program mode). In addition, "DISP ON?" in the judgment block indicates the display memory section DISP0~ of the working area.
7, it is determined whether or not "1" is stored. Therefore, decision block 52
and 53 “PGM DISP ON?” indicates whether any of the program mode keys SIZE, PTRN, SEQ is pressed, that is, SIZE, PTRN,
Working area address 4 corresponding to SEQ
Bits 5, 6, and 7 of 4 (DISP4) (see Figure 9)
This means determining whether "1" is stored in any of the fields.

The input process of the step key STEP will be explained. When the press of the step key STEP is detected in ``KEY TRAP'', it is determined in block 52 whether ``PGM DISP ON?'', and if YES, the process moves to ``CHANGE DISPLAY'' in block 54, and the pressed step key STEP is displayed. "1" is stored in the corresponding display memory sections DISP0-3, and then jumps to idling IDL.
If block 52 is NO, "CHANGEDISPLAY" is not performed and jumps to idling IDL. That is, the press of the step key STEP is stored in the display memory sections DISP0-3 only when the press of any one of the program mode keys SIZE, PTRN, and SEQ is stored.

The subroutine “WAITWT” indicated by block 55 in the processing path of the start set key SSET
is a subroutine for detecting whether or not the light key WT is pressed. When the light key WT is pressed (YES WT), the "DSTART SET" process indicated by block 56 is performed.
In "DSTART SET", start data DSTEP is placed at address 5C (DSTART) of the working area.
and SSEQNo. are written.

Command key processing block 48 shown in FIG.
In "COMMANDKEY TRAP" (first
Based on the distribution in FIG. 6), a predetermined command processing program corresponding to the pressed command key is executed. A detailed explanation of FIG. 18 will be given later.

Next, with reference to the control programs shown in FIGS. 16 to 27, key operation procedures for writing and reading a desired automatic performance program and the associated operation of the apparatus will be described in detail.

Writing an automatic performance program (1) Initial setting When the power switch Power SW (Fig. 7) is turned on, the control program (Fig. 16) starts.
The aforementioned initial setting process "INTIAIL LOAD" is executed.

(2) Program size (WSIZE) writing Γ Address set Index concept (pages and patterns PT1~
PT8) to set the address (data area address) of the program size (WSIZE) to be written. Therefore, the operator performs key operations to specify pages and patterns PT1 to PT8, and inputs them to the microcomputer 1.
1 performs the operation of converting into the address number of the data area within the storage unit 17.

The page is designated by pressing the back key BACK or the forward key FWD. Patterns PT1 to PT8 are specified by pressing a desired key among the eight pattern select keys PATTERN SELECT.

(Pattern specification) Pattern select key on main panel 12
Desired pattern PT from PATTERN SELECT
Press the keys corresponding to 1 to PT8. As a result, the pattern select key PTRN SLCT is detected in "KEY TRAP" in Figure 17, and block 6 is detected.
0 "CHANGE DISPLAY" process, the pressed pattern select key (PATTERN
Display memory section compatible with “SELECT”
The storage bit of DISP4 (FIG. 9) is set to "1". This state can be changed to “PTRN SLCT DISP
"ON".

(Page specification) Address 5D of working area (Figure 9)
The 3-bit data stored in (DPAGE) represents the page. This page data is set to "000" by initial setting, and specifies the first page. Therefore, if the first page is sufficient, there is no need to perform any key operations to specify the page. However, if you want to change to another page, press the size mode key SIZE and specify the pattern described above, then press the back key BACK or the forward key FWD. When you press the forward key FWD, you can advance the page by the number of presses. In the case of the back key BACK, the page moves backward by the number of times the key is pressed.

First, press the size mode key SIZE to display the display memory area DISP in the working area.
4 (FIG. 9), SIZE is stored. This is the first
According to the process of block 57 in FIG. This state is called "SIZE DISP ON". Pressing the back key BACK or forward key FWD
It is detected by COMMAND KEY TRAP (Fig. 16) and processed as shown in Fig. 18. In other words, when the back key BACK is pressed, the back flag BACK FLG is set (block 5).
8) If the forward key FWD is pressed, the forward flag FWD FLG is set (block 59). The decision "SEQ DISP" following the flag setting by processing block 58 or 59
ON? ” is the display memory section DISP4 (9th
Determine whether or not there is memory of pressing the sequence mode key SEQ in Figure). In this case, the answer is NO, so the decision is "PTRN SLCK DISP ON?" Here, the pattern select key PTRN SLCT is placed on the display memory section DISP4.
A determination is made as to whether or not there is a press memory (omission of PATTERNSELECT), that is, whether or not patterns PT1 to PT8 have been specified. In this case, the answer is YES, so we move on to the decision "SIZE DISP ON?" Since the size mode key SIZE was pressed, this is also YES, and the process moves to "CHANGEDPAGE" shown in block 61.

In "CHANGE DPAGE", address 5D of the working area (Figure 9)
1 per press of forward key FWD for page data stored in DPAGE.
The value of the page data of DPAGE is rewritten by adding or subtracting 1 each time the back key BACK is pressed. In other words, BACK FLG5
When 8 is set, subtract (-1),
When FWD FLG59 is set, add (+1). In this way, the 3-bit page data of DPAGE (page buffer register) is rewritten.

In the process of block 62 following "CHANGE DPAGE", the display memory sections DISP0-3 for the step key STEP are cleared, and the page data stored in DPAGE is set in the display memory section DISP0. That is, 3-bit page data is decoded, and the decoded result (page data) is stored in any of storage bits 0 to 7 corresponding to steps 1 to 8 of DISP0.
Then jumps to idling IDL,
The light emitting element (7th
(see figure) to display the page lighting.
At this time, press the pattern select key PATTERN.
A lighting display of SELECT is also performed.

With the above steps, the page data and pattern select data necessary for specifying the address of the data area will be transferred to DPAGE and DISP4 (PTRN) of the working area.
SLCT DISP”.

Γ Write In the above-mentioned “address set” state, that is, “SIZE DISP ON” and “PTRN SLCTDISP ON”
In this state, use the step key STEP to set "Beat Size" and "Pattern Size". 64
Among the step keys STEP, the key with the step number corresponding to the desired "beat size" and the key with the step number corresponding to the desired "pattern size" are pressed simultaneously. Next, press the write key WT to command writing.

At ``KEY TRAP'' in FIG. 17, pressing of the step key STEP is detected, and the process moves to the judgment ``PGM DISP ON?'' shown in block 52. "SIZE
DISP ON”, so this judgment is YES.
The process ``CHANGE DIS PLAY'' (block 54) is carried out. As a result, the memory in the display memory sections DISP0-3 corresponding to the step key STEP is rewritten to the ``beat size'' step and the ``pattern size'' step.

Based on the press of the light key WT, “KEY
In GROUP TRAP (Figure 16), the command key is
CMK is detected, decision block 46 is NO, decision block 47 is NO, and "COMMAND KEY" is detected.
TRAP” and detects the press of the light key WT. And the writing program shown in Fig. 19
Moving on to WTP.

In the program WTP shown in FIG. 19, the subroutine APTRN (pattern address search) is first processed. Pattern address search APTRN uses page data stored in DPAGE and
The desired WSIZE address (ASIZE) is determined based on the pattern selection data stored in the DISP 4. A flowchart of this pattern address search APTRN is shown in FIG.

“X ₁ ←
(DPAGE+PTRNSLCT)" is 3-bit page data (data that represents DPAGE and pattern select data in 3 bits (000 to 111))
Combine PTRNSLCT into 6-bit data,
This means storing this in register _X1 .
This 6-bit data corresponds to the serial number of the pattern, that is, the number of WSIZE counted from the first data (ATOP) of the data area.

“X ₀ ←ATOP” means that the address ATOP of the first data of the data area stored at address 55 of the working area is stored in the register X ₀ . ATOP is initially set to "18BF" and is sequentially rewritten as the writing of the data area progresses (a flowchart of data rewriting of this ATOP is not particularly shown).

The gist of the processing after processing block 63 is to count the number of WSIZE in order from the first data (ATOP) of the data area (Figures 11 and 12), and when the number matches the value of DPAGE + PTRNSLCT, the address number is Detect. Strictly speaking, DPAGE
Not when it matches the value of +PTRNSLCT, but
This is when DPAGE+PTRNSLCT+1 is matched. Because the first pattern on page 1 (PT1)
This is because the value of DPAGE+PTRNSLCT corresponding to is "000000".

“R ₀ ←X ₀ ” means that the address data (initially ATOP) stored in register X ₀ is stored in register R ₀ . "R ₀ = WSIZE?" determines whether data WSIZE is stored at the address stored in register R ₀ . If YES, the process moves to "X ₁ -1<0?"; if NO, the process moves to "X ₀ +1". “X ₁ −1<0?” is a register
Subtract 1 from the memory of X ₁ and the result is 0 or 0
Determine which is smaller. The result of the subtraction is stored in the register.
This becomes X ₁ 's new memory content. "X ₀ +1" means adding 1 to the contents stored in register X ₀ .
The addition result becomes the new storage content of register _X0 .

If “X ₁ −1<0?” is NO, “X ₀ +1”
Move to. After the processing of "X ₀ +1", the processing moves to "R ₀ ←X ₀ ".

In this way, each time WSIZE is detected, "DPAGE
1 is subtracted one after another from ``+PTRNSTCT'', and 1 is added one after another to the address ATOP of the first data in the data area until the result of the subtraction becomes YES (X ₁ -1<0?). Therefore, “X ₁ −1<0?”
is YES, data representing the address of the pattern specified by the page data (DPAGE) and pattern select data (PTRNSLCT) is stored in register _X0 . The address data of this _register
Store in the storage locations of ASIZE (size address) and ADTA (data address).

ASIZE represents the address where the WSIZE of the performance pattern to be written or read is stored, and ADTA specifies the address to be written or read.

When the pattern address search APTRN is completed, the program returns to the write program WTP (FIG. 14).
“SEQ DISP ON?” is NO, “PTRN SLCT
DISP ON? ” is YES, “PTRN DISP ON?”
is NO, “SIZE DISPON?” is YES,
Size writing program SIZE shown in Figure 21
Move to WT.

In FIG. 21, "RESET SIZE DISP" means clearing the memory of the size mode key SIZE in the display memory section DISP4.

In "GET STEP DISP?", the step key STEP is set in the display memory section DISP 0 to 3.
Determine whether the person has a memory of If the step key STEP is pressed to set "Beat size" and "Pattern size", "GET STEP" is pressed.
DISP? " is YES, and if the step key STEP is not pressed at all, it is NO. If NO, the process “R ₂ ←“2040”” shown in block 64 is executed.

“R ₂ ← “2040”” sets “2040” to register R ₂ .
(displayed in hexadecimal). The upper data "20" (32 in decimal) corresponds to the beat size, and the lower data "40" (64 in decimal) corresponds to the pattern size. That is, when the step key STEP is not pressed, the maximum steps 32 and 64 of the beat size and pattern size are set as the respective size setting values.

Processing of block 65 performed when “GET STEP DISP?” is YES “PSIZE←MAX,
BSIZE←MIN”, the pressed step key
Select the pattern size (PSIZE) that corresponds to the maximum step (MAX) among STEPs,
Select the minimum step (MIN) as the beat size (BSIZE). After processing block 65, the number of steps selected as the beat size (BSIZE) reaches the maximum step 32 of the beat size.
(“20” in hexadecimal notation) is determined as “BSIZE≦“20””. When this judgment is YES, the process moves to block 66, but when it is NO, the process moves to block 66 after performing the process of "BSIZE←"20''. In "BSIZE←"20", processing is performed to change the beat size (BSIZE) to "20" (in hexadecimal notation), that is, the maximum step 32.

Processing of block 66 “R ₂ ←BSIZE, PSIZE”
Now, the beat size selected as above
Store the data of BSIZE and pattern size PSIZE in register _R2 . Block 66 or 64
After the processing, perform the processing of "WSIZE (ADTA)←R ₂ ". In this process, the data address (ADTA) stored in address 57 of the working area is
The beat size BSIZE and pattern size PSIZE stored in the register _R2 are written to the address position specified by , according to the format of WSIZE shown in FIG.

(3) WSIZE writing check In the same way as WSIZE writing described above, specify the desired page, select the pattern using the pattern select key (PTRN SLCT), and press the size mode key SIZE. Then, press the check mode key CHCK. Check mode key CHCK with "KEY TRAP" shown in Figure 17.
is detected, and a determination is made as to "SIZE DISP ON?" This is YES and then “PTRN
SLCT DISP ON? ”, and this also
Since the answer is YES, the process moves to block 67.
The processing in block 67 searches for an address in the data area based on the specified page data and pattern select data (data address (ADTA) stored in address 57 of the working area), and searches for a data area address corresponding to the desired performance pattern.
Read WSIZE (beat size and pattern size) and write the read beat size (BSIZE) and pattern size (PSIZE) to the display memory sections DISP0 to DISP3 of the step key STEP. After this processing, the process returns to idling IDL, and the beat size and pattern size are displayed by lighting using the light emitting elements corresponding to the step key STEP.

(4) WSIZE Cancel In the same way as when writing WSIZE above, specify the page and select the pattern (PTRN SLCT), then press the size mode key SIZE. Moreover,
Cancel enable key CE and light key WT
Press.

Pressing of the cancel enable key CE is detected by "COMMAND KEY TRAP" (FIG. 16), and based on the detection of the key CE, the subroutine "WAIT WT" is executed (FIG. 18). As described above, in this "WAIT WT", it is determined whether the light key WT is pressed. In this case, "WAIT WT" is YES, the following "SEQ DISP ON?" is NO, and "PTRN SLCT" is YES.
DISP ON? ” is YES, “PTRN DISP ON?”
is NO, “SIZE DISP ON?” is YES,
Block 68 processing “CLEAR SIZE DATA”
leading to. In "CLEAR SIZE DATA",
Search the address of the data area based on the specified page data and pattern select data, specify the address where the desired WSIZE is stored, and clear the beat size and pattern size stored at that address.

(5) Writing performance patterns (WSTEP, WTONE) Γ Address setting Address setting is performed by page designation and pattern selector in the same way as when writing WSIZE described above.

Γ Write While pressing pattern mode key PTRN,
Operate the step key STEP to instruct the step corresponding to the pronunciation timing. In this case, for steps that have the same percussion instrument type, accent, duration, and output channel, those keys can be pressed at the same time (they do not have to coincide completely in time). i.e. instrument select key
Selectively press the desired keys of INSTRUMENTSELECT (INSTR.), accent key ACCENT (ACC.), duration key DURATION (DURAT.), and channel select key CHANNEL (CHAN.), and then use the step key STEP to specify Specify the "percussion instrument type", "sound strength", "sound duration" and "output channel" of the generated sound at the sound generation timing. The instrument select key INSTR. can also be used to simultaneously press keys corresponding to one or more percussion instruments that are sounded at the same timing. but,
If the "sound intensity" etc. is different, press separately. Next, press the write key WT to instruct writing.

Pressing of the pattern mode key PTRN is detected at "KEY TRAP" in FIG. 17, and bits 5 and 5 of the display memory section DISP4 are
The memory of program mode key (PGM) areas 6 and 7 will be cleared once (therefore, the old SIZE
(If there is a memory of DISP ON, this will be cleared) and the pattern mode key PTRN will be memorized.
This allows “PTRN DISP ON” and “PGM
DISP ON” status. Also, similarly “KEY
TRAP” STEP, INSTR., CHAN.,
The DURAT. and ACC. key presses are detected, and the respective presses are stored in the display memory sections DISP0-7.

Pressing of the light key WT is detected in "COMMAND KEY TRAP" in FIG. 16, and the program moves to the write program WTP shown in FIG. 19. In the program WTP of FIG. 19, the pattern address search APTRN is first processed, and the address of WSIZE specified by the page designation and pattern selection is stored as ASIZE and ADTA. Next, “SEQ DISP ON?” NO,
“PTRN SLCT DISP ON?” YES, “PTRN
DISP ON? (Has the pattern mode key PTRU been pressed?)" YES is determined, and the process moves to the pattern writing program PTRNWT shown in FIG. 22.

In the pattern writing program PTRNWT, first the processing and judgment shown in block 69 "SCAN
DISP/GET STEP? ”

In "SCAN DISP/GET STEP?", each step key of display memory section DISP 0 to 3 is displayed.
The STEP memory status is scanned in order from the lowest step number (step 1), and when a step in which a key press is stored is detected, scanning is stopped midway,
Based on the YES display, the process moves to "WSTEP write". Also, if this "SCAN DISP/GET STEP?" is entered while scanning is stopped midway, scanning will be stopped and resumed from the step number.

Regarding the "WSTEP write" process, a schematic flowchart of the process is shown in block 70. "R ₀ ← Detection step" means that the step number detected in block 69 is stored in register R ₀ . "ADTA+1" adds 1 to the data address ADTA to increase the value of ADTA.
As mentioned above, the value of ADTA is initially ASIZE
It is the same as (WSIZE address).
"WTONE?" moves to the address position increased by 1.
Determine whether WTONE is stored.
"WTONE?" If YES, add 1 to ADTA and advance the address. If “WTONE?” is NO, move on to “WSTEP?”. “WSTEP?”
determines whether data WSTEP is stored at the address location specified by ADTA. “WSTEP?” If YES, “WSTEP=
_R0 ? ”, and if “WSTEP?” is NO, then move to “ADTA-1”. "WSTEP?" NO means "WSIZE" has been detected.
``WSTEP=R ₀ ?'' determines whether the step number of WSTEP currently specified by ADTA matches the step number (R ₀ ) detected in the process of block 69. When this is YES, block 71 is written without writing WSTEP.
Move to. “WSTEP=R ₀ ?” If NO, move to “WSTEP>R ₀ ?” Here, it is determined whether the step number of WSTEP currently designated by address ADTA is greater than the step number detected in block 69.
"WSTEP>R ₀ ?" If NO, "WSTEP<R ₀ "
It means "ADTA+1".

“WSTEP>R ₀ ?” If YES, “ADTA−
1" and sets the data address ADTA to 1.
Subtract. As a result, the step number detected in block 69 is stored in WSTEP 1.
The previous address is specified by ADTA.
In addition, here, sometimes, each address position above (lower address number) from the address specified by ADTA (including the address specified by ADTA)
Data stored in (WSIZE, WSTEP,
WTONE) sequentially higher (younger or one smaller)
Move forward to the address position and rememorize it,
Leave the address location specified by ADTA vacant. At the same time, “ATOP-1” and “ASIZE-1”
Then, the values of the start address ATOP and the size address ASIZE are each decreased by 1. This is because the stored data was moved up.

In "WRITE WSTEP (R ₀ )", the above ADTA
data at the address location specified by
The WSTEP mark and the step number stored in register _R0 (ie, the step number detected in block 69) are written in accordance with the WSTEP format shown in FIG.

“SCAN DISP/GET” shown in block 71
INSTR.? ”, the display memory section DISP
5 and 6 instrument select keys INSTR.
When the instrument select key whose key press is stored is detected, the scanning is interrupted and the process of block 72 "Write WTONE" is executed.
Move to.

Regarding the "Write WTONE" process, an outline of the process flowchart is shown in block 72. “R ₀ ←Detected INSTR.” is the instrument select key data detected in block 71.
It means to store INSTR. into register _R0 . "ADTA+1" adds 1 to the data address ADTA to increase the value of ADTA. Initially, this ADTA indicates the address of the WSTEP written most recently. ``WTONE?'' determines whether WTONE is stored at the address position increased by 1. "WTONE?" If YES, the process moves to the determination of "WTONE=R _0. " “WTONE＝
_R0 ? ' is now specified by ADTA
It is determined whether the instrument data INSTR. of WTONE matches the data stored in register _R0 . If it doesn't match, it's NO;
Return to "ADTA+1" and add 1 to ADTA to advance the address.

"WTONE?" If NO, by ADTA
WSTEP or WSIZE is specified and
The process moves on to “ADTA-1 (ATOP-1, ASIZE-1)”. This process is the same as that of block 70, and returns ADTA to the previous address.
Specify the address (ADTA) for writing WTONE, push up the stored data above that address, and make the ADTA position after "ADTA-1" blank. After this process, “WRITE WTONE
(R ₀ ). “WTONE=R ₀ ?” If YES, “WRITE
WTONE (R ₀ )”.

In "WRITE WTONE (R ₀ )", the above ADTA
data at the address location specified by
WTONE mark, instrument select data INSTR in register _R0 , channel data CHAN., and duration data stored in display memory section DISP7 (Figure 9)
DURAT. and accent data ACC. are written according to the WTONE format shown in FIG.

As described above, one WTONE is written by the processing of block 72. When the processing of block 72 is completed, the process returns to block 71.
Display memory section DISP5 from the interrupted position,
6 (FIG. 9) is resumed. Then, when a press of an instrument select key INSTR. different from the previous one is detected, "WTONE writing" is performed again in block 72. In this way, "WTONE" is written as many times as there are pressed instrument select keys INSTR.

1 scan of display memory section DISP5 and 6
Once completed, block 71 “SCAN DISP/
GET INSTR.? ” becomes NO, and block 69
Return to processing.

Block 69 “SCAN DISP/GET”
STEP? ”, select the step key STEP display memory section DISP 0 to 3 from the last interrupted position.
resumes scanning, and when it detects that the step key STEP has been pressed, the scanning is interrupted and "WSTEP writing" is started.
Move to 70. WSTEP writing is performed in the same manner as described above, and further WTONE writing is performed. In this way, the steps with the lowest numbers are
WSTEP and WTONE are written. Moreover, due to the processing in block 70 ("WSTEP>R ₀ ?"),
WSTEP and WTONE with a step number lower than the step number of the already stored WSTEP are written (to a lower address) before that WSTEP (WSTEP with a larger step number). Therefore, one
The WSTEPs in WSIZE are arranged in ascending order of step number.

Display memory section for steps DISP0~
When one scan of step 3 is completed, "SCAN DISP/GET STEP?" of block 69 becomes NO.
Jumps to idle IDL.

(6) WSTEP, WTONE writing check As with the WSIZE writing described above, specify the desired page, select the pattern using the pattern select key (PTRN SLCT), and press the pattern mode key (PTRN). This results in the "PTRN SLCT DISPON" and "PTRN DISP ON" states. Moreover,
Press the step key STEP to specify the step to be checked, and then press the forward key FWD. The forward flag (FWD FLG) is set in response to the forward key FWD being pressed (block 59 in Figure 18), and the “SEQ DISP” is set.
ON? ”NO, “PTRN SLCT DISP ON?”
YES, “SIZE DISP ON?” NO, “PTRN
DISP ON? ” YES, the process reaches block 73, ``WTONE pronunciation.''"WTONEpronunciation"
In the process, the specified WTONE data in response to pressing the forward key FWD (WTONE data initially stored at the youngest address in the specified step (WSTEP): see Figure 12)
is read from the data area and the read WTONE
A corresponding percussion instrument sound is generated based on the data. Every time you press forward key FWD
The designation of WTONE changes, and the next WTONE data stored in the data area is read out. In this way, by pressing the food key FWD, you can
The WTONE data is read out one by one and the corresponding percussion instrument sounds are generated. In this case, it will be read
If you want to move the WTONE data back one step, press the back key BACK instead of the forward key FWD. Furthermore, when the last WTONE data in the designated step is read out, the process moves to the next step. In addition, step specification and WTONE
When reading data and generating sound, the light emitting elements attached to the step key STEP corresponding to the designated step and the instrument select key (INSTR.) corresponding to the generated percussion sound (contents of WTONE data) are lit.

In addition, if "PTRN DISP ON?" is NO,
This means it is not in program mode. That is, this is because the sequence mode key SEQ, size mode key SIZE, and pattern mode key PTRN are all off. In this case, block 1
00 processing, the WSTEP corresponding to the step specified by the step key STEP is
Read all WTONE data and
Produce percussion instrument sounds based on WTONE data.

(7) Cancel WSTEP, WTONE Pattern mode key PTRN, pattern select key PTRN SLCT, and desired step key
Press STEP and then cancel enable key
Press CE and light key WT. This results in
WSTEP data and WTONE of the step (sound timing) specified by the step key STEP
Data is cleared.

Pressing of the cancel enable key CE is detected in COMMAND KEY TRAP in FIG. 16, and the state reaches "WAIT WT" shown in FIG. 18. Since the light key WT is pressed, YES WT
"SEQ DISP ON?" NO, "PTRN
SLCT DISP ON? ” YES, “PTRN DISP
ON? ” YES, then block 74 “SCAN
DISP/GET STEP? ”. This process “SCAN DISP/GET STEP?” is the same as the process of block 69 in FIG.
Find the step specified by STEP.

In “CLEAR WSTEP WTONE”,
WSTEP data that stores the step number corresponding to the detected step and the WSTEP data
Clear all WTONE data. After that, return to the processing of block 74 again and press the step key.
WSTEP for each step specified by STEP
Clear data and WTONE data.

(8) Writing of sequence program The sequence program is written to addresses 68 to A7 (DSEQ) of the working area (FIG. 9), that is, the sequence RAM. At this time, the write address is specified by address 59 (NSEQ), ie, the data stored in the sequence counter.

Γ Address Set During initial setting (INITIAL LOAD), the sequence counter (NSEQ) is set to all "0" (this corresponds to sequence number 1). Further, when the reset key RESET is pressed, the sequence counter (NSEQ) is set to the value corresponding to sequence number 1 (hole "0"). That is, in the process path of the reset key RESET shown in FIG. 18, if the start set key SSET is not pressed, the judgment "SSET
DISP ON? ” is NO, and the process of block 76 “NSE←Sequence No. 1” is reached. This causes the sequence counter NSEQ to change to sequence number 1.
will be reset to

The contents of the sequence counter NSEQ are changed by pressing the back key BACK or the forward key FWD while pressing the sequence mode key SEQ. Figure 18 key
In the BACK or FWD processing path,
``SEQ DISP ON?'' is determined to be YES, and the process moves to ``CHANGE NSEQ (±1)'' shown in block 77. In the processing of this block 77, the back key is
Subtract 1 from the value of NSEQ each time BACK is pressed, and each time the forward key FWD is pressed
Add 1 to the value of NSEQ. Then block 62
Then, the content of the page data is displayed by lighting.

Γ Write To specify the page, press the BACK key while pressing the size mode key SIZE, just as when writing the program size (WSIZE) described above.
Or by pressing the forward key FWD. This results in address 5D (Figure 9)
Desired page data (DPAGE) is set in .

Specify the pattern using the pattern select key
This is done by selectively pressing the PTRN SLCT.
As a result, the desired pattern selection data is stored at address 44 (Fig. 9), and "PTRN SLCT
DISP ON” status.

After specifying the page and pattern, press the sequence mode key SEQ and the light key WT. In the writing program WTP shown in FIG. 19, it is determined that "SEQ DISP ON?" is YES, and the sequence writing program shown in FIG.
Move on to SEQWT.

In the sequence writing program SEQWT, the value of the sequence counter NSEQ is registered.
X ₀ (X ₀ ← NSEQ), and determine whether _the contents _of this register
≦7F? ). “X ₀ ≦7F?” If NO, the value of the sequence counter NSEQ is the maximum sequence number 128.
(“7F” in hexadecimal), so a sequence program impossible warning is issued. This warning is given by lighting all keys of the pattern select key PTRN SLCT.

"X ₀ ≦7F?" If YES, sequence programming is possible, and it is determined whether the pattern select key has been pressed (pattern designation has been made) (PTRN SLCT DISP ON?). YES
In the case of , page data DPAGE of address 5D
and pattern select key at address 44
The data (PTRN SLCT(4)) which encodes the memory contents of PATTERN SELECT into a 4-bit binary code (0001 to 10000) is stored in an 8-bit register.
Store in parallel in X ₁ (X ₁ ←DPAGE+
PTRNSLCT(4)). Also, “PTRN SLCT DISP
ON? ” If NO, register X ₁ is all “0”
(X ₁ ← 0).

"WRITE DSEQ←(X ₁ )" sets register X ₁
The page data and pattern select data stored in are transferred to addresses 68 to A7 in the sequence RAM specified by the sequence counter NSEQ.
(DSEQ). As aforementioned,
Memory bits 0 to F of each address 68 to A7 are divided into two and used depending on whether the value of the sequence counter NSEQ is even or odd. Thereafter, 1 is added to the value of the sequence counter NSEQ (NSEQ+1), and the sequence number is advanced.

In this manner, writing of page data and pattern select data corresponding to one sequence number is completed. Next, specify the desired page and select the pattern, and press the sequence mode key SEQ and light key WT again. The page data and pattern select data will be stored in the address position (DSEQ) in the sequence RAM corresponding to the next sequence number. is written.

(9) Sequence program cancellation Set the sequence counter NSEQ to a desired value in the same manner as in the case of address setting, and press the sequence mode key SEQ, the write key WT, and the cancel enable key CE. In the processing path of key CE in Figure 18, “SEQ
DISP ON? ” is YES, and the process moves to “CLEAR DSEQ” shown in block 78. “CLEAR
DSEQ'' erases the page data and pattern select data stored in the sequence number specified by the value of the sequence counter NSEQ in DSEQ in the working area, and then sets the value of NSEQ to 1.
Decrease.

(10) Program Cancel To erase the entire program of one performance pattern, use the cancel pattern key CP. First, press the size mode key SIZE and operate the back key BACK or forward key FWD to set the page buffer register (DPAGE).
(FIG. 9), set the desired page data.
Furthermore, the pattern select key (PTRN SLCT)
Select patterns PT1 to PT8 by selecting . Then, press the light key WT and cancel pattern key CP.

In the processing path of the cancel pattern key CP in FIG. 18, "WAIT WT" is YES WT, "PTRN SLCT DISP ON?" is YES,
Performs "CLEAR DATA AREA" processing. This process "CLEAR DATA AREA" clears the data area for one performance pattern specified by the combination of the page data stored at address 5D (DPAGE) of the working area and the pattern select data stored at address 44. All storage data WSIZE, WSTEP, WTONE
Erase.

Executing automatic performance (1) Setting performance conditions Automatic performance according to the sequence program is executed by pressing the RUN/STOP key to set the performance RUN state.
Select the desired tempo using the tempo selection switch (TEMPO), and then press the tempo doubling key (x2) or tempo halving key (÷2) as desired. These switches (TEMPO, × 2, ÷
2) can be effectively operated even during a performance, and the tempo can be changed during a performance. You can also select the deiminuendo (DIM) or cresciendo (CRS) rate with the rate selection switch (RATE) and press the deiminuendo selection key (DIM) or cresciendo selection key (CRS) at any point during the performance. From this point on, you can apply a deiminuendo or cresiendo effect. key (×2, ÷2,
DIM, CRS) is detected in the "KEY TRAP" processing (Fig. 17), and in the "CHANGE DISPLAY" processing of block 50 or 51, "x2" is stored in the display memory section DISP7 of the working area (Fig. 9). Or “÷2”,
"DIM" and "CRS" are stored.

(2) Start address specification Γ DSTART set First, press the reset key RESET and set the contents of the sequence counter NSEQ (address 59 in Figure 9) to the value corresponding to sequence number 1 (“0000000”)
Reset to . This is block 76 in Figure 18.
This is done through the process of

Next, while pressing the sequence mode key SEQ, press the back key BACK or the forward key FWD as appropriate to rewrite the contents of the sequence counter NSEQ to a value corresponding to the desired performance start sequence number. This is based on the processing of block 77 in FIG.

Next, press the step key STEP corresponding to the desired performance start step. By pressing the sequence mode key SEQ, the decision block 52 "PGMDISP ON?" in FIG. It is rewritten and the performance start step is stored.

Next, press the start set key SSET.
As a result, "SSET" is stored in the display memory section DISP4 by the "CHANGE DISPLAY" process in the SSET processing path of FIG. 17 (see FIG. 9), and the state becomes "SSET DISP ON". Press the light key WT at the same time,
Set to DSTART write state. By pressing the light key WT, "WAIT WT" shown in block 55 of FIG. 17 becomes YES WT, and "DSTART"
SET” processing. In "DSTART SET", address 5 of the working area (Figure 9)
At the position of the start data DSTART of C, write the encoded data of the storage steps of the display memory section DISP0 to 3 as the play start step data DSTEP, and write the contents of the sequence counter NSEQ at address 59 as the play start sequence number data SSEQNo. Write.

Γ Start address set Press the reset key RESET while the “SSET DISP ON” status remains. Shown in Figure 18
In the RESET key processing path, "CLEAR"
NSEQ&INSTR. DISP", the contents of the sequence counter NSEQ and the display memory section
Clear the memory contents of the instrument select keys (INSTR.) of DISP5 and 6. The next judgment "PTRN DISP ON?" is the pattern mode key.
PTRN is not pressed, so NO,
“REPEAT DISP ON?” is also a repeat key
Since REPEAT is not pressed, it is NO,
"SSET DISP ON?" is YES, block 79
Move on to processing.

In the process "NSEQ←SSEQ No." in block 79, the performance start sequence number SSEQ No. stored at address 5C (DSTART) is set in the sequence counter NSEQ at address 59. After that, the process moves to "DISPLAY DSEQ".

In "DISPLAY DSEQ", the sequence number specified by the contents of the sequence counter NSEQ (in this case, the play start sequence number) is used as an address to read data corresponding to the sequence number from the sequence RAM (DSEQ at addresses 68 to A7). Read the stored page data and pattern select data, write the read page data to the page buffer register (DPAGE) at address 5D, and use the pattern select key (PATTERN SELECT) at address 44 (DISP4) according to the read pattern select data.
Rewrite the memory of. After that, “DISP0~3←
DSTEP” processing.

In "DISP0-3←DSTEP", the step corresponding to the performance start step number DSTEP stored in DSTART of address 5C is stored in the step display memory section DISP0-3. Then, reset the run flag (RUN FLG) and jump to idling IDL.
When processing "DISPLAY SCAN" (Fig. 16), the performance start pattern PT1 of the performance start step is
~PT8 is displayed lit.

(3) Instructing to start playing After specifying the start address as described above, press the RUN/STOP key,
Instructs to start playing. "COMMAND KEY"
TRAP” (Figure 16) to run/stop key
When RUN/STOP is pressed, the program moves to the run/stop program R/STP shown in FIG.

In the run/stop program R/STP, first a determination is made as to ``RUN FLG ON?''.
Here, it is checked whether the run flag (RFLG) at address 5B in the working area (FIG. 9) is set. Since the run flag was reset based on the press of the reset key RESET in the above-mentioned "start address set" processing, the "RUN FLG ON?" answer is NO, and the program moves to the RUN program. Furthermore, when "RUN FLG ON?" is YES, that is, when the run flag is set, STOP will occur when the RUN/STOP key is pressed.
Move on to the program.

In the RUN program, pattern address search "APTRN" is first processed. As mentioned above, "APTRN" processes according to the procedure shown in FIG. Through this "APTRN" processing, the address of the data area storing the size data WSIZE of the first performance pattern is found, and this address is used as the size address ASIZE and the data address ADTA as addresses 56 and 57 of the working area. (Fig. 9). In other words, the page data and pattern select data that specify the performance pattern corresponding to the performance start sequence number are DPAGE and DISP ₄ (PTRNSLCT).
In the "APTRN" process, the address of the data area (that is, pattern RAM) is found based on these data (DPAGE+PTRNSLCT).

In "GET WSISE (Bs, Ps)?", after the above "APTRN" processing, the data address is
It is determined whether the beat size B _B and pattern size P _S are stored in the WSIZE data position specified by ADTA. If YES, set the run flag (RFLG at address 5B) to “1” (RUN FLG set) and reset the continuation flag CFLG at address 5B in the working area to “0” (CFLG←“0”). .

Next, the tempo setting subroutine "ASTEMPO"
Move to.

(4) Tempo setting (ASTEMPO) In the tempo setting subroutine ``ASTEMPO'', calculations based on the above-mentioned equation (1) are executed to obtain data corresponding to the cycle of one step. sought 1
Select the timer (10ms or 1ms) for setting the sound timing according to the length of the step cycle,
Set the timer flag ``10ms'' or ``1ms'' at address 5B in the working area (Figure 9). Also, calculate the frequency division ratio of the timer output based on the obtained step cycle and the cycle of the timer used (10ms or 1ms), and store the data corresponding to the frequency division ratio at address 5B of the working area as tempo data DTEMPO. . Furthermore, if the newly calculated tempo data DTEMPO is different from the old tempo data (DTEMPO) previously stored at address 5B, the continuation flag CFLG at address 5B in the working area is reset to "0". The above is an overview of the processing in "ASTEMPO". The data set in this “ASTEMPO” (DTEMPO, 10ms or
1ms), the step progression speed of automatic performance is determined, and the sound timing is set.
The processing procedure of "ASTEMPO" is shown in FIG.

In Figure 25, “READ TEMPO SW←
_R1 '' reads the output of the tempo selection switch TEMPO on the main panel 12 and stores this switch output in the register _R1 .

"READ Ts (address R ₁ ) ← R ₀ " selects the tempo selection switch stored in register R ₁ above.
Using the output of TEMPO as an address signal, tempo information Ts is read from a tempo information table (not shown), and the read tempo information Ts is set in register _R0 . This tempo information Ts is 4 times per unit time.
Corresponds to the number of diacritics.

In "READ Bs (address ASIZE) ← R ₂ ",
The beat size data Bs included in WSIZE is read from the data area using the size address ASIZE stored in the working area address 56 (FIG. 9) as an address signal, and this beat size data Bs is set in register _R2 .

In "R ₁ ← R ₀ × R ₂ (Ts × Bs)", register R ₀
The tempo information Ts stored in the register R2 is multiplied by the beat size data Bs stored in the register _R2 , and the multiplication result is stored in the register _R1 .

Next, it is checked whether the tempo doubling key (x2) or halving key (÷2) has been pressed. In other words, "x2DISP ON?" determines whether the press of the tempo doubling key (x2) is stored in the display memory section DISP ₇ (Figure 9), and if YES, the contents of register _R1 are Rewrite it to twice the value (that is, (Ts×2)×Bs) (“R ₁ ×2”). “÷
2DISP ON? "In the display memory section DISP ₇
Determine whether or not the press of the tempo halving key (÷2) is stored, and if YES, rewrite the contents of register _R1 to the value of 1/2 (i.e. (Ts x 1/2) x Bs). (“R ₁ × 1/2”). _The tempo doubling key (×2) or the halving key (÷2) is used to effectively expand the range of the tempo selection switch TEMPO, so it _is The processing can be regarded as modifying the value of the tempo information Ts by 2 times or 1/2.

The tempo information Ts represents the number of quarter notes per unit time, and the beat size Bs represents the number of quarter note steps. Therefore, the value Ts×Bs (or (Ts×2)×Bs or (Ts×1/2)×Bs) held in register _R1 represents the number of steps per unit time. When the unit time is k, the step period is the value (k/Ts×Bs) divided by k by the contents of register _R1 .

In decision block 80, the contents of register _R1 (that is, the number of steps per unit time Ts x Bs)
Since then, it has been used as a reference oscillator for setting the sound timing.
Decide whether to use a timer with a 10ms cycle or a timer with a 1ms cycle. That is,
If the contents of register _R1 are larger than the predetermined reference value REF ( _R1 >REF? is YES), a flag of a 1ms cycle timer is set (1msFLG set). Furthermore, if the contents of register _R1 are smaller than the predetermined reference value REF ( _R1 >REF? is NO), a flag of a 10ms cycle timer is set (10msFLG set). Note that when setting either the 1ms or 10ms flag, be sure to reset the other flag. If a 10ms timer is selected, multiply the contents of register R ₁ by 10 (R ₁ × 10).

In the process of "R ₂ ←k/R ₁ ", the constant k corresponding to the unit time is divided by the contents of register R ₁ to obtain data for setting the step period, that is, tempo data, and this is stored in register R ₂ to be memorized. Therefore,
The contents of register _R2 are (k/Ts×Bs) when the 1ms timer is selected, and (k/Ts×Bs×10) when the 10ms timer is selected. Looking at this in relation to equation (1) above, if a 1ms timer is selected, k is used as the constant K,
If a 10ms timer is selected, this means that k/10 is used as the constant K. This is because the step timing is set by appropriately dividing the timer output according to the value of the tempo data, so it is necessary to switch the calculation constant of the tempo data (DTEMPO) according to the timer period.

In "DATA CHANGED?", the tempo data stored in register R ₂ (data obtained by this calculation) and the tempo data stored in address 5B of the working area
DTEMPO (data obtained from the previous calculation)
and if they change (if they don't match)
It is judged as YES, and if there is no change, it is judged as NO. If YES, the continuation flag (CFLG) at address 5B is reset; if NO, the continuation flag is set. Thereafter, the value of the tempo data DTEMPO at address 5B in the working area is rewritten to the newly calculated tempo data stored in the register R ₂ (DTEMPO←R ₂ ).

When the "ASTEMPO" process is completed, the program returns to the run/stop program R/STP (Fig. 24).
The processing of "LOOPA STEP", "ADTA+1", and "CSTEP set" is executed to reach the timer interrupt subroutine "TINT".

(5) Data area address set and step counter set In the process of "LOOPASTEP" in FIG. 24, the address position of WSTEP that stores the same step number as the performance start step number DSTEP is searched from the data area. The processing procedure of this subroutine "LOOPASTEP" is shown in FIG.

In FIG. 26, block 81 contains a data address that specifies the address of the data area.
Add 1 (ADTA+1) to the value of ADTA (stored at address 57 in the working area) and advance the specified address in the data area by one. To start with,
The program size (WSIZE) of the first pattern to be played is determined by the processing of “APTRN” in Figure 24.
The address specifying the storage location of is set in ADTA.

In the next judgment "WTONE?",
It is determined whether WTONE data is stored at the address position specified by the data ADTA added by 1. Since the purpose of this "LOOPASTEP" is to search for WSTEP,
“WTONE?” If YES, press “ADTA+1” again.
Return to , add 1 to ADTA, and proceed to the next address. If “WTONE?” is NO, move on to “WSTEP?”. "WSTEP?" determines whether WSTEP data is stored at the address location specified by data ADTA.

"WSTEP?" If YES, the process moves to block 82. Here, the step number (see Figure 10) included in the WSTEP data is read out, and this step number (WSTEP) is changed to the performance start step number DSTEP (stored at address 5C in the working area, and also (WSTEP < DSTEP?) (which is also stored in the display memory units DISP0-3 through processing). As mentioned above, in the data area, the WSTEP data attached to one WSIZE are arranged in ascending order of step number, so if "WSTEP <DSTEP?" is YES, the WSTEP corresponding to the playback start step number DSTEP is still ahead. This means that it is at the (larger number) address position of
Increase the value of ADTA. “WSTEP<DSTEP?”
If NO, move on to the judgment "WSTEP = DSTEP?"

In "WSTEP=DSTEP?", the address
It is determined whether the step number of WSTEP read by ADTA matches the performance start step number DSTEP. If YES, return to the original program (Figure 24). If YES,
WSTEP that ADTA corresponds to the play start step
is instructing. If NO, WSTEP＞
This means that the playback start step number DSTEP does not correspond to the WSTEP. In this case, “ADTA
-1", the original program (second
Return to Figure 4). Also, if "WSTEP?" is NO, the "ADTA-1" process is performed. “WSTEP?”
If NO, WSIZE is stored at the address next to size address ASIZE, i.e.
corresponds to WSIZE dictated by ASIZE
This means that neither WSTEP nor WTONE is programmed.

In Figure 24, after "LOOPASTEP",
“ADTA+1” processing, i.e. data address
Add 1 to ADTA. If there is a WSTEP corresponding to the start step DSTEP (if WSTEP = DSTEP in Figure 26 is YES), the data address ADTA increased by 1 is the address position next to that WSTEP, that is, the start step corresponding to that WSTEP. If the WSTEP corresponding to the start step DSTEP does not exist (see Figure 26),
(If WSTEP=DSTEP is NO), it indicates the address of "WSTEP" corresponding to the step number larger than DSTEP and closest to DSTEP.

In the "CSTEP set" process, the data of the pattern size (Fig. 10) is read from the address position of the data area where the WSIZE data specified by the size address ASIZE is stored, and the play start stop DSTEP is started from this pattern size data Ps.
Subtract , then add 1 to get "Number of remaining steps"
(Ps-DSTEP+1) is determined, and this "number of remaining steps" is set to address 5A (CSTEP) of the working area (FIG. 9). “Number of remaining steps” stored in CSTEP and starting step DSTEP
(i.e. the step you are about to pronounce)
The relationship can be expressed schematically as shown in FIG. 29a. As is clear from Figure 29a, CSTEP
(ie, step counter) stores the number of remaining steps including the next step to be sounded.

(6) Sound generation processing Sound generation is performed by the processing of the timer interrupt subroutine "TINT".

The control program progresses within the microcomputer 11 based on the tempo data DTEMPO obtained by the above-mentioned "ASTEMPO" processing and the output of the timer (10ms or 1ms) selected by the "ASTEMPO" processing as well. Regardless of this, calculations (frequency division) are performed to obtain the step clock. When a step clock is generated, it acts on the control program as an interrupt command and causes the timer interrupt subroutine "TINT" to be executed.

A circuit for generating a step clock is conceptually shown in FIG. The outputs of the 1 ms or 10 ms timers 83 and 84 are selected by a selector 85 in accordance with the contents of the timer flag (1 ms, 10 ms) at address 5B in the working area and are input to a variable frequency divider 86. The frequency division ratio of this variable frequency divider 86 is set by the tempo data DTEMPO at address 5B of the working area. Variable frequency divider 8
The output of 6 is a step clock (corresponding to WCLOCK or CK), which acts as an interrupt instruction and causes the timer interrupt subroutine "TINT" to be executed. Therefore, "TINT" is executed for each step.

The processing procedure of the timer interrupt subroutine "TINT" is shown in FIG. In the "PUSH register", the contents of the register are stored in another location. This is because "TINT" is an interrupt subroutine, so while a program is running in another mode other than performance mode, you may switch to sound mode and execute this "TINT", in which case the program in progress will be temporarily interrupted. This is because it is necessary to store the contents of registers related to the program in another location in order to do so. In "WCLOCK output", WCLOCK data having the configuration shown in FIG. 13 is output to the data bus 14 (FIG. 1). this
Based on the WCLOCK output, the decoder 20 (first
The step clock signal CK and, depending on the case, the crescendo signal CRS or diminuendo signal DIM are output from the sound source channel 2.
Counter 37 of 1-1 to 21-X (Figure 15)
is given a downcount pulse, and
A signal CRS or DIM is applied to the CRS/DIM envelope signal forming circuit 22 (FIG. 14).

Continuation flag is determined by “CFLG=1?”
It is determined whether CFLG is "1" or not. If NO, the contents of the tempo data DTEMPO have been changed, so the timer cycle is changed according to the contents of the timer flag (1ms or 10ms).

“RUN FLG ON?” (block 87)
Determine whether or not the RUN flag is set, and if YES, proceed to the process for generating sound (processing after "WTONE?" in block 88), and if NO
In this case, the process moves to the process for stopping the sound generation (the process after "CSTEP-1=O?" in block 89).

In Block 88's "WTONE?"
Determine whether WTONE data is stored at the address position of the data area specified by data address ADTA, and if YES, "WTONE
"Output" processing. In "WTONE output", based on data address ADTA
Read the WTONE data and read out the WTONE data to the data bus 14 (Figure 1) (Figure 13)
Output. given to data bus 14
Decoder 20 based on the instrument selection data INSTR in the WTONE data
(Fig. 1), a channel signal (one of ch1 to chX) corresponding to the type of percussion instrument is output, and the counter 3 is output from the sound source channels 21-1 to 21-X corresponding to the channel signals ch1 to chX.
7 (Figure 15) shows the duration data.
Preset DURAT and latch circuit 39
Accent data ACC. and output channel selection data CHAN. are latched (Fig. 15).
In addition, the relevant sound source channels (21-1 to 21-
one shot circuit 38 (the first
5) is operated, and the envelope generators 40 and 4
An envelope signal is generated from 1. In this way, the relevant
The percussion instrument sound specified by the WTONE data is produced.

After outputting one WTONE data to the data bus 14, in the "ADTA+1" process, 1 is added to the data address ADTA, and this addition result is used to rewrite the memory of a new ADTA to advance the read address of the data area. And again block 8
Return to step 8 “WTONE?” and press “WTONE?”
By repeating the processing of "WTONE output" and "ADTA+1", all the WTONE data continuously stored in the data area are read out and sounded.

For example, one page of pattern PT1 (see Figure 12) is set by the performance start sequence number SSEQNO.
is specified, and WSTEP of (#1) of pattern PT1 of this one page is specified by start step DSTEP.
(see Figure 12), the address storing this (#1) WSTEP is set as the data address ADTA in the process of ``LOOPASTEP'' in Figure 24, and the next ``ADTA+1'' is set as the data address ADTA. ” process (#1) Stored in the next address of WSTEP
To the address of WTONE (#1) (Figure 12)
The value of ADTA is set. Then, in the process of "TINT" in FIG. 27, "WTONE?" of block 88 is YES, and WTONE (#1)
The percussion instrument sound set by is produced. Next, when it becomes "ADTA+1", WTONE (#2) is stored in the address next to WTONE (#1) ((#1) of PT1 on page 1 in Figure 12).
(See WSTEP), “WTONE?” YES again
The percussion instrument sound set by this WTONE (#2) is produced. Next is “ADAT+1”
Then, in the example shown in Figure 12, (#2) WSTEP is stored at the address following WTONE (#2), so "WTONE?" becomes NO, and the sound generation process is stopped ("WTONE output" is (not enough). In this way, consecutive WTONE data (#1 and #2)
are all read out and pronounced. “WTONE?”
Since the processing of "WTONE output" and "ADTA+1" is performed at high speed, the percussion instrument sounds corresponding to consecutive WTONE data (WTONE (#2) and (#1)) are heard as being sounded simultaneously.
In this way, the process for producing one step is completed.

If the data address ADTA already indicates data other than WTONE (WSTEP or WSIZE) when entering the interrupt subroutine "TINT", for example "LOOPASTEP" in Figure 24.
In the process, the start step DSTEP cannot be found, and in the next "ADTA+1", the memory address of "WSTEP" corresponding to the step number larger than DSTEP and closest to DSTEP is set.
Block 8, such as when instructed by ADTA.
Judgment number 8 “WTONE?” was NO from the beginning,
At that time, nothing is produced at the step corresponding to "TINT" (for example, the step corresponding to DSTEP).

If ``WTONE?'' is NO, the process moves to block 90 to determine ``CSTEP-1=O?'' to determine whether or not the pattern has ended. “CSTEP-1=
O? '', subtract 1 from the remaining step number (i.e., step counter) CSTEP stored at address 5A of the working area (Figure 9),
Determine whether or not the subtraction result is O, and use the subtraction result as a new CSTEP at address 5A.
Rewrite the contents of. If YES, the remaining number of steps is O, meaning that one performance pattern has been completed. If NO, it means that there are still steps left and the pattern is not finished. The processing after this "CSTEP-1=O?" is a preparatory process for the sounding of the first step, and in the path of "CSTEP-1=O?" YES, processing is performed to advance the sequence to the next step. In the NO path, calculation processing is performed to switch the tempo display as the step progresses.

First, we will explain the NO route, that is, the case where there are still steps remaining. “STEP′=Ps−
In the process of ``CSTEP-1'', the remaining step number CSTEP, which has been subtracted by 1 in the process of block 90, is subtracted from the pattern size Ps of the address specified by the size address ASIZE, and
Furthermore, 1 is subtracted to find the number of steps STEP' at which sound generation has been completed, which does not include the step currently processed for sound generation.
The relationship of this calculation formula is schematically shown in FIG. 29b.

In the process of "X ₁ ← Bs × [STEP' / Bs] i + 1", the number of steps STEP' at which sounding ends is divided by the beat size Bs read from the address specified by size unres ASISE. ,
Calculation of multiplying the integer part [STEP′/Bs]i of the division result by the beat size Bs and then adding 1 (Bs×
[STEP'/Bs]i+1) is executed and the calculation result is set in register _X1 . In the above calculation formula, [STEP'/Bs]i represents the number of completed quarter notes, and Bs[STEP'/Bs]i represents the number of steps corresponding to the number of completed quarter notes. Therefore,
(Bs×[STEP'/Bs]i+1) represents the first step number of the newest (currently playing) quarter note. This relationship is schematically shown in FIG. 29c.

In block 91 "DISP0~ ₃ ← _X1 ", the contents of register
Rewrite the memory of 0 to 3 with the contents of X ₁ ). As a result, the light emitting element corresponding to the step key STEP is lit for each first step of a quarter note by the process of "DISPLAY SCAN" (FIG. 16), and serves as a tempo display.

In "WSTEP?", the data address
Determine whether WSTEP data is stored at the address location specified by ADTA. If YES, move to "Ps=CSTEP+WSTEP-1?"
If NO, it means that ADTA specifies WSIZE data (because "WTONE?" in block 88 was NO), and means that there are no more steps to sound. If NO, the process skips the process performed if YES and goes to "ASTEMPO".

"Ps=CSTEP+WSTEP-1?" indicates the step number of WSTEP read from the address specified by data address ADTA and the number of remaining steps.
It is determined whether the value obtained by adding CSTEP and subtracting 1 matches the pattern size Ps.
If YES, it means that the next step matches the step number of WSTEP read by ADTA (i.e. the next step is the step to be sounded); if NO, the step number read by ADTA The step number of the WSTEP that is displayed means that it exists before the next step (that is, the next step is not the step that should be sounded). This relationship is schematically shown in FIGS. 29d and e.

If "Ps=CSTEP+WSTEP-1?" is YES, "ADTA+1" processing is performed, 1 is added to data address ADTA, and the addition result is set as new ADTA. ADTA added by 1 is
It indicates the next address of WSTEP, that is, the address of WTONE. If NO, “ADTA+
Skip step 1 and move on to ASTEMPO. Therefore, if the next step is a step that should be sounded, data address ADTA indicates the first WTONE data corresponding to that step, but if the next step is not a step that should be sounded, data address ADTA indicates the next step. It indicates WSTEP corresponding to the step to be pronounced.

When the above-mentioned preparation process for the next step is completed, the tempo setting subroutine "ASTEMPO" (see FIG. 25) is executed. In other words, constant calculation for setting the tempo for each step (Equation 1)
is executed and the tempo data DTEMPO etc. are updated. Therefore, the tempo can be changed by operating the tempo selection switch (TEMPO) or keys (x2, ÷2) at will during the performance. "ASTEMPO"
After that, process the "POP register" and return to the original program. In the "POP register", the register contents stored in another location in the "PUSH register" at the beginning of "TINT" are returned to the original register.

In Figure 24, when the processing of the timer interrupt subroutine "TINT" is completed, the idling IDL (first
Return to Figure 6). When the next step timing is reached, a step clock is generated and the program enters the timer interrupt subroutine "TINT". If this step is the one that should produce a sound, the data address ADTA specifies the address of WTONE as described above, so "WTONE?" in block 88 (Figure 27) is YES, and the sound based on the WTONE data is It will be done. If this step is not a step that should be sounded, as described above, the data address ADTA indicates the address of WSTEP, so ``WTONE?'' in block 88 is NO from the beginning, and no sound is generated. Whether a sound is produced or not produced in this step, the processing in block 90 (CSTEP-1=O?) is executed, and preparations are made to proceed to the next step as described above.In this way, at each step timing ( Each time a step clock occurs, the timer interrupt subroutine "TINT" is executed, and percussion instrument sounds are produced according to the programmed performance pattern.

At the final step of the performance pattern, the number of remaining steps CSTEP is 1, and "CSTEP-1=O?" in block 90 of FIG. 27 is YES.
Perform processing to end the pattern. “REPEAT
DISP ON? ” determines whether the repeat key REPEAT is pressed. repeat key
If REPEAT is not pressed, “REPEAT
DISP ON? ” The process advances the sequence counter (NSEQ) using the NO route, but if the repeat key REPEAT is pressed, the process moves to pattern address search “APTRN” (block 92) without proceeding with the process of advancing the sequence, and the same pattern as the previous one is performed. repeat the performance.

"REPEAT DISP ON?" If NO, first set O in register R ₀ (R ₀ ← O), then add 1 to the sequence counter value NSEQ at address 59 in the working area, and add 1 to that value NSEQ. Rewrite to new value (NSEQ+1). This advances the sequence.

In "DISPLAY DSEQ", the page data and pattern select data are read from the sequence RAM (DSEQ at addresses 68 to A7 of the working area) using the content NSEQ of the sequence counter after incrementing by 1 as an address, and the read page data is used as the address. 5D, and write the pattern select data to the memory location of the pattern select key (PATTERN SELECT) in the display memory section DISP4.

In "R ₀ = O?", it is determined whether the contents of register R ₀ are O or not. At first, the answer is always YES since the register _R0 is set to O, and after performing the process " _R0 ←1" which sets the register _R0 to 1, the process moves to "GET DSEQ?".

In "GET DSEQ?", the sequence specified by the sequence counter NSEQ is
It is determined whether page data and pattern select data (DSEQ) are stored in the storage location of RAM. If the data is stored (in the case of YES), the sequence is still continuing and the process moves to the next process "APTRN". 1 if no data is stored (that is, if page data and pattern select data are all “0”)
This means that the series of sequences (that is, one song) has ended, and the process returns to "NSEQ+1" to further increment the sequence counter NSEQ by one. ``GET DSEQ?'' By NO, ``NSEQ+
1", "DISPLAY DSEQ", and "RO=O?", the contents of register R ₀ is set to 1, so this second judgment "R ₀ = O?"
is always NO, and the process moves to block 93 (RUN FLG reset) to end the performance.

On the other hand, the contents of the process "APTRN" of block 92 executed to continue the sequence are as follows.
As shown in Figure 0, the above-mentioned “DISPLAY
Based on the page data (DPAGE) and pattern select data (PTRN SLCT) of the new performance pattern set in the processing of ``DSEQ'', the WSIZE address corresponding to these data is found, and the found address is set as ASIZE.
Set to ADTA. Also, “REPEAT DISP
ON? "APTRN" of block 92 is also executed when "YES", but in this case, the page data (DPAGE) related to the previous performance pattern is executed.
Since the pattern select data (PTRN SLCT) remains uncleared, the same ASIZE and ADTA as the previous performance pattern are set.

GET WSIZE(Bs,Ps)? In ``
It is determined whether the beat size Bs and pattern size Ps are stored at the WSIZE data position specified by ADTA, and if NO, the performance end process of block 93 ("RUN FLG reset") is performed.
If YES, the process moves to "CSTEP←pattern size Ps".

In "CSTEP←pattern size Ps", WSIZE specified by data address ADTA
Read the data of pattern size Ps from the data,
This pattern size data Ps is sent to the step counter (CSTEP) at address 5A in the working area.
Set to . Therefore, the remaining step number CSTEP
is initially the number of steps corresponding to the pattern size Ps. After that, 1 is added to the data address ADTA.
Add and increment address ADTA (ADTA+
1). Next, in the process of "X ₁ ← 1", 1 is set in register X ₁ . Next, the processing of block 91 "DISP0-3←X ₁ " is performed. Therefore, at the beginning of the performance pattern, as a tempo display,
The light emitting element corresponding to step 1 is turned on. From then on, in the same way as above, "WSTEP?", "Ps=CSTEP
+WSTEP-1? ” and “ADTA+1”, preparatory processing is executed to determine whether the next step (step 1 at the beginning of the performance pattern) is the step to be sounded.

(7) Performance termination processing Performance termination may be performed automatically or manually. First, the automatic case will be explained.

If the performance is to be ended automatically as described above, the process of block 93 in FIG. 27 is performed. In block 93, the RUN flag is reset,
And the remaining step number CSTEP of address 5A is set to "10" (in hexadecimal notation), that is, "16" in decimal. This is the duration of the last generated sound.
This is to secure time for 16 steps. After that, it goes through processing such as "ADTA+1" and reaches "RETURN". At the next step timing, the "TINT" process is executed again, but this time the block 87 "RUN FLG ON?" is NO, and the block 89 process "CSTEP-1=O?"
Do the following. This is the same as the processing in block 90, and it is determined whether the value obtained by subtracting 1 from the remaining step number CSTEP is O or not, and the result of the subtraction is set as the new remaining step CSTEP. If NO, it will go through “ASTEMPO” and then “RETURN”. In this way, after resetting the RUN flag,
When the time for 16 steps has elapsed, block 89
The judgment "CSTEP-1=O?" becomes YES, and the remaining step number CSTEP is set to 1 by processing "CSTEP+1", and then the timer is stopped.

To stop the performance manually, press the RUN/STOP key. Figure 24 Run/
In the stop program R/ST P, “RUN
FLG ON? ” is YES and goes to the STOP processing path. So, first of all, "RUN FLG reset,"
CSTEP←“10” (hexadecimal display)” processing.
This is the same as the processing in block 93 of FIG. 27, in which the run flag is reset and the remaining step number CSTEP is set to 16 steps.

In "ADTA-1", the data address
The value obtained by subtracting 1 from ADTA is set as the new data address ADTA. In other words, address ADTA is incremented backwards. If WTONE is stored at the address position specified by this new ADTA, "WTONE?" is YES, and the process returns to "ADTA-1" and further steps backward. Move ADTA backwards until "WTONE?" becomes NO, then "WTONE?" becomes NO.
Then move on to “WSIZE?” If WSIZE data is not stored at the address location specified by ADTA (WSTEP is stored)
"WSIZE?" is NO, and the process moves to "X ₁ ← WSTEP". Here, based on ADTA
Read the step number from WSTEP and set this step number in register _X1 . “WSIZE?”
If YES, perform the process "X ₁ ← 1" and set step 1 in register X ₁ . Next “DISP
0 to 3←X ₁ '', the step number of register X ₁ is stored in the step display memory section
- Set to 3. At the next step timing, the timer interrupt subroutine "TINT" is executed, but since the RUN flag has been reset, the judgment at block 87 in FIG. 27 is NO, and the processing at block 89 "CSTEP-1=O?"Let's do it. Therefore, in the same manner as described above, the subtraction in block 89 of "TINT" is repeated for 16 steps, and when the subtraction is completed, the timer is stopped.

Note that the stopped timer is restarted when the RUN flag is set.

Modification Example In the above embodiment, the automatic performance device 1 of the present invention
0 is shown as a stand-alone device, it may also be integrated with another electronic musical instrument (eg, a keyboard electronic musical instrument). In that case, a synchronized start function can be added so that automatic performance (rhythm performance) starts in synchronization with key operations.

Although the automatic performance device 10 of the embodiment is configured as an automatic rhythm performance device, it can also be changed to a device that automatically plays scale notes such as an automatic bass, an automatic chord, an automatic arpeggio, or a melody. That is, on the main panel 12, some of the instrument select keys (INSTRUMENT SELECT) correspond to instruments other than percussion instruments such as piano or flute, and new keys are provided for inputting pitch information. When a musical instrument is selected, the pitch information input key is operated instead of the accent key (ACCENT) or the duration key (DURATION) to input the desired pitch information. In the storage unit 17, a display memory section for pitch information may be newly provided in the working area, but a display memory section for accent or duration may also be used in common with pitch information. In sound source channels (some of 21-1 to 21-X) corresponding to musical instruments other than percussion instruments, pitch information latched in a latch circuit (corresponding to latch circuit 39 in Figure 15) is converted into an analog signal, and this The oscillation frequency of the sound source oscillator (VCO) 31 is controlled by analog pitch information. The above changes enable automatic performance of scale tones (melody).

Although the above embodiment shows an automatic performance device whose performance pattern can be programmed, the present invention can also be applied to an automatic performance device that cannot be programmed. For example, the parts of the working area from addresses 68 to A7 (DSEQ) in Figure 9, that is, the sequence RAM section, are converted into ROM, and the data area is also converted into ROM, and the predetermined WSIZE and WSTEP are set in advance in correspondence with the 64 performance patterns. , WTONE, the automatic performance device 10 of the embodiment is changed to a non-programmable device.
In the RUN state, the step period is calculated according to the above equation (1) by the "ASTEMPO" processing,
It is possible to provide an automatic performance device in which the resolution of sound generation timing (step) is not fixed to a specific note.

Effects As explained above, according to the present invention, the resolution of pronunciation timing (step timing) is not fixed to a specific note, but is changed as appropriate according to tempo information and reference size (beat size).
A limited number of performance steps can be used effectively without waste. For example, when trying to obtain the highest resolution in the embodiment, the beat size Bs
All you have to do is set it to 32 steps, and in this case, one step can correspond to a 128th note. In addition, for performances that do not require high resolution, you can set the beat size Bs to about 1 or 2 steps so that 1 step corresponds to a quarter note or eighth note, and set the pattern size Ps to a maximum number of steps of 64. , one performance pattern can include 16 or 8 measures of 4/4 time. Therefore, one cycle of the performance pattern can be made extremely long, making it possible to perform complex automatic performances.

Further, according to the present invention, tuplets and ordinary notes can be used together within one sequence (one song) without causing a time signature shift. To give an example of this point, when using a tuplet measure (or phrase) and a normal note measure (or phrase) as separate performance patterns in one sequence, when using a triplet, In the performance pattern, the beat size Bs is assumed to be 3 steps, for example. On the other hand,
In a normal tuplet performance pattern, the beat size Bs is assumed to be 4 steps. In the tuplet pattern, the period of one step is (K/Ts x 3) from equation (1) above, and the length of one beat consisting of a triplet is (K/Ts x 3 x 3 = K/Ts ). In a normal note pattern, the period of one step is (K/Ts x 4), and the length of one beat, or quarter note, is (K/Ts x 4 x 4 = K/Ts). Therefore, the length of one beat is the same, and even if a tuplet pattern and a normal note pattern are used together, no time signature difference will occur.

Further, according to the present invention, when programming an automatic performance pattern, the length of the pattern can be set arbitrarily by the pattern size Ps, and the length of one beat (4
Since the length of a diacritic note can be set arbitrarily by the beat size Bs, it is possible to easily program special performance patterns in which the length of one measure is not an integral multiple of a beat. Further, by arbitrarily setting the beat size or pattern size of each performance pattern within one sequence (one song), it is possible to program a free form of performance.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of the overall configuration of an embodiment of the automatic performance device of the present invention, FIGS. 2 to 6 are diagrams for explaining the outline of an automatic performance program, and FIG. 2 shows an automatic performance pattern. FIG. 3 is an explanatory diagram that omits the relationship between the automatic performance program and the sequence. FIG. 3 is an explanatory diagram that schematically shows the procedure for creating an automatic performance program. FIG. Figure 5 is an explanatory diagram showing an example of the program configuration of an automatic performance sequence using the index concepts of 'page' and 'pattern'. Figure 6 is an explanatory diagram showing an example of the program configuration of an automatic performance sequence using FIG. 7 is a top view showing an example of the key arrangement of the main panel in FIG. 1. FIG. 8 is a diagram showing the memory map of the storage unit in the microcomputer in FIG. 1. FIG. 9 is a memory map showing an example of writing in the working area in FIG.
Figure 0 is a diagram showing the format of data written to the data area shown in Figure 8, Figure 11 is a diagram showing an example of writing in the initial settings of the data area, and Figure 12 is a diagram after the program has been written to some extent. A diagram showing an example of writing in the same data area at each stage,
Figure 13 is a diagram showing an example of the structure of data output from the microcomputer section in Figure 1 to the data bus during the performance RUN state, and Figure 14 is an example of the CRS/DIM envelope signal forming circuit in Figure 1. 15 is a block diagram showing an example of the sound source channel in FIG.
6 to 27 are flowcharts schematically showing the control program executed by the microcomputer shown in FIG. 1, FIG. 16 is a flowchart schematically showing an example of the main program, and FIG. 18 is a flowchart showing a detailed example of the program key processing block shown in FIG.
6 is a flowchart showing a detailed example of the command key processing block, FIG. 19 is a flowchart showing an example of the writing program WTP branching from FIG. 16, and FIG. Flowchart illustrating an example of the pattern address search subroutine APTRN shown in FIG.
FIG. 1 is a flowchart showing an example of the size writing program SIZEWT that branches from FIG. 19, FIG. 22 is a flowchart showing an example of the pattern writing program PTRNWT that branches from FIG. A flowchart showing an example of the sequence writing program SEQWT.
A flowchart showing an example of the stop program R/STP. FIG. 25 is a tempo setting subroutine used in FIGS. 16, 24, and 27.
Flowchart showing an example of ASTEMPO, 2nd
Figure 6 is the subroutine shown in Figure 24.
FIG. 27 is a flowchart showing an example of the timer interrupt subroutine TINT used in FIG. 24. FIG. 28 is a conceptual example of a circuit configuration for generating a step clock. Block diagram shown, No. 29
30 to 34 are functional diagrams showing the present invention. 10...Automatic performance device, 11...Microcomputer, 12...Mail panel, 16...Central processing unit (CPU), 17...Storage unit,
21-1 to 21-X...Sound source channel, 22
...CRS/DIM envelope signal formation circuit.

Claims (1)

[Scope of Claims] 1. A step setting means for setting and storing each step at which a musical tone is to be produced out of a specific number of steps corresponding to each production pattern of a performance pattern, and configuring one beat (or a specific note). beat size setting means for setting a beat size representing the number of steps; tempo setting means for setting a performance tempo; calculation means for calculating a step progression speed based on the set performance tempo and the beat size; reading means for sequentially reading out the setting state of each step of the performance pattern set by the step setting means according to the step progression speed; An automatic performance device comprising means for generating musical tones. 2. The step setting means includes a step storage section that stores steps to be sounded for each of a plurality of performance patterns each having an arbitrary number of steps; It is comprised of a beat size storage section that sets and stores beat sizes individually corresponding to the patterns, and the calculation means stores the beat sizes set corresponding to the pattern selected from among the plurality of performance patterns. 2. The automatic performance apparatus according to claim 1, wherein the reading means reads out the step to be sounded corresponding to the selected pattern from a step storage section while being used for calculation. 3. The step setting means includes step selection means for selecting a desired step to be produced from among a specific number of steps corresponding to each sound generation timing, and storing the steps selected by the step selection means. a rewritable step storage section; the beat size setting means includes a beat size selection means for arbitrarily selecting a beat size;
2. The automatic performance apparatus according to claim 1, further comprising a rewritable beat size storage section that stores the beat size selected by the beat size selection means. 4. The beat size selection means includes a beat size write instruction key, and disables writing in the step storage section when the instruction key is operated, and writes the number of steps selected by the step selection means into the beat size storage section. 4. The automatic performance device according to claim 3, wherein the automatic performance device is configured to store information in a memory. 5. The tempo setting means includes a tempo selection switch that selects the number of beats (or a specific number of notes) within a predetermined time, and a plurality of calculation keys that increase or decrease the number selected by the switch at a predetermined ratio. Any one of claims 1 to 4, wherein the calculation means is a means for calculating a step progression speed based on the beat size and the selected state of the tempo selection switch and the calculation key. Automatic performance device of crab memory. 6. Step setting means for setting and storing each step at which a musical tone is to be produced among a specific number of steps corresponding to each sounding order of the performance pattern; and a pattern size for setting a pattern size representing the number of steps constituting the performance pattern. a setting means; a beat size setting means for setting a beat size representing the number of steps constituting one beat (or a specific note); a tempo setting means for setting a playing tempo; and a setting means for setting the set playing tempo and the beat size. a calculation means for determining a step progression speed based on the step progression speed; a reading means for sequentially reading out the setting state of each step of the performance pattern set by the step setting means in accordance with the determined step progression speed; a musical tone generating means for generating a musical tone corresponding to each step setting state; and one for advancing the reading step by the reading means.
An automatic performance device comprising pattern readout control means for setting a cycle according to the pattern size. 7. The pattern readout control means controls the readout means so that when the readout steps by the readout means have progressed to the number of steps represented by the pattern size, the step progress is returned to the initial step. 6th
The automatic performance device described in Section 1. 8. The step setting means includes a step storage section that stores steps to be produced in advance; the pattern size setting section includes a pattern size storage section that stores pattern sizes in advance; and the beat size setting section 8. The automatic performance device according to claim 6, further comprising a beat size storage section in which beat size is stored in advance. 9. The step setting means includes a step selection means for selecting a desired step to be generated from among a specific number of steps corresponding to each sound generation timing, and storing the step selected by the step selection means. The pattern size setting means includes a rewritable step storage section, and the pattern size setting means includes a pattern size selection means for arbitrarily selecting a pattern size, and a rewritable step storage section for storing the pattern size selected by the pattern size selection means. a pattern size storage unit, and the beat size setting means includes a beat size selection means for arbitrarily selecting a beat size;
Claim 6 or 7, further comprising a rewritable beat size storage section that stores the beat size selected by the beat size selection means.
The automatic performance device described in Section 1. 10. A step memory section that stores each step that should produce a musical tone among a specific number of steps that correspond to each sound generation timing of a performance pattern, and a beat size that represents the number of steps that make up one beat (or a specific note). a beat size storage section; a tempo setting means for setting a performance tempo; a calculation means for calculating a step progression speed based on the performance tempo and the beat size; a tone setting means for setting sound information regarding the sound to be generated in correspondence with the step to be generated, and outputting the sound information in accordance with the readout output of the step storage section; and an output. and musical tone generation means for generating musical tones based on the generated tone information. 11. The tone setting means sets, as information regarding the sound to be generated, information representing the type of percussion instrument, information representing the strength and weakness of the sound, and information representing the duration of the sound, and the musical sound generating means sets information regarding the sound to be generated based on the above information. Claim 1, which drives a percussion instrument sound source.
The automatic performance device described in item 0. 12. Claim 10, wherein the tone setting means sets information representing pitch as information regarding the sound to be generated, and the musical tone generating means is means for generating scale tones based on the information. The automatic performance device described in Section 1. 13. The musical tone generating means includes a plurality of channels of speaker sounding means, and the tone setting means sets at least information indicating a sounding channel by the speaker sounding means as information regarding the sound to be generated. The automatic performance device according to item 10, item 11, or item 12. 14 The tone setting means includes a plurality of sound information selection means corresponding to a plurality of types of information regarding sounds to be generated, and stores information selected by the sound information selection means corresponding to each step to be emitted. An automatic performance device according to any one of claims 10 to 13, comprising a rewritable tone storage section. 15 a sequence storage section that stores information for sequentially instructing performance patterns as the automatic performance progresses; and a sequence storage section that stores pattern sizes representing the number of steps constituting one performance pattern for each of the plurality of performance patterns; a pattern size storage section from which a pattern size corresponding to the performance pattern indicated by the information read out is read; and a beat size representing the number of steps constituting one beat (or a specific note) for the plurality of performance patterns. a beat size storage section storing information corresponding to each of the plurality of performance patterns, a pronunciation information storage section storing at least steps to be produced corresponding to each of the plurality of performance patterns, and a tempo setting means for setting a performance tempo. , calculation means for determining a step progression speed based on the performance tempo set by the tempo setting means and the beat size read from the beat size storage unit; and calculation means for calculating the step progression speed according to the determined step progression speed. Steps stored in the pronunciation information storage section corresponding to the performance pattern specified by the information read out from the storage section are sequentially read out, and one cycle of read step progression corresponds to the pattern size read out from the pattern size storage section. reading means set based on the sound generation information storage section; musical tone generation means for generating musical tones corresponding to each step memory read out from the pronunciation information storage section; An automatic performance device comprising: sequence advancing means for advancing reading of the sequence storage section each time a cycle is completed; and writing means for writing desired data into each of the storage sections. 16. The sequence increment means includes a sequence counter that specifies a read address of the sequence storage section, and the pattern size storage section and the beat size storage section are read out from the sequence storage section according to the contents of the sequence counter. The storage contents are read using the performance pattern instruction information read out from the sequence storage section, and the pronunciation information storage section specifies a pattern to be read based on the performance pattern instruction information read out from the sequence storage section, and the processing means specifies the pattern to be read out using the performance pattern instruction information read from the sequence storage section. The step memory corresponding to the specified pattern is read out according to the step progression speed determined by the step, and the musical tone generation means generates a musical tone at the timing of the step to be generated based on this readout. The automatic performance device according to item 15. 17. The reading means is controlled to return the step progress to the initial step when the reading step from the pronunciation information storage section progresses to the number of steps represented by the pattern size read from the pattern size storage section. 17. The automatic performance device according to claim 16, wherein the sequence counter is also incremented by one step at this time. 18 The pronunciation information storage section includes a step storage section that stores steps to be produced in accordance with each of a plurality of performance patterns, and a step storage section that stores sound information regarding sounds to be produced in correspondence with the steps to be produced. Claim 15 or 16, further comprising: a tone storage section in which a musical tone is generated based on the tone information read out from the tone storage section corresponding to a step to be generated by the reading means. The automatic performance device according to item 1 or 17. 19. The writing means includes a pattern selection means for selecting a performance pattern, a step selection means for selecting a desired step to be sounded from among a specific number of steps corresponding to each sound generation timing,
beat size selection means for arbitrarily selecting a beat size; pattern size selection means for arbitrarily selecting a pattern size; tone selection means for selecting information regarding the sound to be generated; a sequence writing circuit for storing data instructing a played pattern in the sequence storage section; and a performance pattern selected by the pattern selection means in the step storage section, pattern size storage section, beat size storage section and tone storage section. data selected by the step selection means, pattern size selection means, and beat size selection means are respectively stored in storage areas corresponding to the step selection means, and selection information by the tone selection means is stored corresponding to the selection steps by the step selection means. 19. An automatic performance device according to claim 18, comprising a pattern writing circuit for performing a pattern writing circuit. 20 A step memory section that stores each step that should produce a musical tone among a specific number of steps that correspond to each sound generation timing of a performance pattern, and a beat size that represents the number of steps that make up one beat (or a specific note). a beat size storage section; a tempo setting means for setting a performance tempo; a calculation means for calculating a step progression speed based on the performance tempo and the beat size; reading means for reading out a musical tone; musical tone generating means for generating a musical tone in response to the readout output of the step storage section; a gradual volume change setting means for setting a gradual change in volume; and control means for gradually controlling the volume of the sound generated by the musical sound generation means in response to the sound generation means. 21 The volume gradual change setting means includes a gradual increase selection key, a gradual decrease selection key, and a change speed selection switch, and the control means is configured to select either a gradual increase type or a gradual decrease type in response to selection operations of the selection key and the selection switch. 21. The automatic performance device according to claim 20, comprising a circuit for generating an envelope signal, and a circuit for commonly controlling the volume of the generated sound in accordance with the envelope signal.