JPS6340395A - Manufacture of through-hole printed interconnection board - Google Patents
Manufacture of through-hole printed interconnection boardInfo
- Publication number
- JPS6340395A JPS6340395A JP18261986A JP18261986A JPS6340395A JP S6340395 A JPS6340395 A JP S6340395A JP 18261986 A JP18261986 A JP 18261986A JP 18261986 A JP18261986 A JP 18261986A JP S6340395 A JPS6340395 A JP S6340395A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- hole
- resist
- copper
- hole printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000007747 plating Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000007796 conventional method Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010949 copper Substances 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 238000005476 soldering Methods 0.000 description 10
- 239000011889 copper foil Substances 0.000 description 6
- 229910007116 SnPb Inorganic materials 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000002845 discoloration Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000037303 wrinkles Effects 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 241000208140 Acer Species 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 241000269821 Scombridae Species 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 235000020640 mackerel Nutrition 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000009420 retrofitting Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（並菓上の利用分野）
この発明は、スルーホール印刷配線板の製造方法の改良
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Application) This invention relates to an improvement in a method for manufacturing a through-hole printed wiring board.
（従来の技術）
従来、スルーホール印刷配線板には、異金属めっきとし
て導体パターン全面に′１４を解Ａｕめつき電解Ｓｕ
Ｐｂめつき処理したもの、また電解Ｃｕスルーホールの
もの、ソルダーレベラー処理したものが、公知の方法に
よって製造されているが、それには下記の欠点がある。(Prior art) Conventionally, through-hole printed wiring boards have been plated with different metals such as '14' and Au plating on the entire surface of the conductor pattern.
Pb plating treated ones, electrolytic Cu through-hole ones, and solder leveler treated ones are manufactured by known methods, but these have the following drawbacks.
すなわち、′に解Ａｕめつき処理を通用する方法では、
コストが高くなる欠点があり、またＡｕを下地金属銅に
直付けにすると、Ａｕの拡散現象が生じるため、銅とＡ
ｕの金楓層の中間に緩衝用の金属Ｎｉ＃の介在が必要と
なる。In other words, in the method that passes the solution Au plating process for ',
The disadvantage is that the cost is high, and if Au is attached directly to the copper base metal, a diffusion phenomenon of Au will occur, so the copper and A
It is necessary to interpose buffering metal Ni# between the gold maple layers of u.
電解Ｓｎ Ｐｂめつき処理を適用する方法では、エツチ
ングオーバーによるオーバーハングが欠落して近接導体
と短絡し易くなり、通常のソルダーレジストでは半田付
は時に半田めっきが醇けて使用できず、５ｎＰｂめつさ
上にコーティングする場合、５ｎＰｂ用のソルダーレジ
ストヲ施さなければならず、コス）？Ａとなる。また、
５ｎｐｂ用のソルダーレジストをコーティングしても、
半田付は後にソルダーレジストがシワ状になり、外観が
著しく損われる。さらにまた半田付は後はソルダーレジ
ストの密層が悪くなり、とくに後付は部品個所はテープ
マスクをして半田付けを行い、半田付は後のテープ剥離
で剥れる危険性をもっている。In the method of applying electrolytic SnPb plating treatment, the overhang due to etching is lost and short circuits with adjacent conductors are likely to occur.When soldering with normal solder resist, the solder plating is sometimes saturated and cannot be used, and the 5nPb plate is When coating on the crest, a solder resist for 5nPb must be applied (cost)? It becomes A. Also,
Even if it is coated with 5npb solder resist,
After soldering, the solder resist becomes wrinkled and the appearance is significantly impaired. Furthermore, after soldering, the dense layer of solder resist deteriorates, and especially in retrofitting, parts are soldered with a tape mask, and there is a risk that the soldering will peel off when the tape is peeled off later.
電解Ｃｕスルーホール処理を適用する方法では、Ｃｕス
ルーホールはスラックスが酸化防止用採掘被膜として使
用されているが、ロジンペースのもの、または主成分と
してのアルキイミダゾールが銅と化学結合するもの等が
あり、７ランクス処理してもＣｕスルーホールは長期間
の保存ができず、銅表面が酸化し易く、半田付けを阻害
する欠点がある。In the method of applying electrolytic Cu through-hole processing, Slack is used as a mining coating to prevent oxidation, but there are also rosin-based ones, or ones in which alkyimidazole as the main component chemically bonds with copper. Even with 7-Ranks treatment, Cu through-holes cannot be stored for a long period of time, and the copper surface is easily oxidized, which has the drawback of inhibiting soldering.
ソルダーレベラー処理を適用する方法では、’４Ｆ４Ｃ
ｕスルーホール基板のうちのランド部のみをＳｎ Ｐｂ
処理をするが、半田槽の中へ基板を直接入れるための基
板に対してのショックが大きいことと、パターン部分は
Ｃｕのみのため、ソルダーレジストが付着しない箇所が
発生すると、そこから醸化されてしまう欠点がある。In the method of applying solder leveler processing, '4F4C
u Only the land part of the through-hole board is Sn Pb.
However, since the board is placed directly into the solder tank, the shock to the board is large, and the pattern area is made of only Cu, so if there are places where the solder resist does not adhere, it will cause problems. There are drawbacks to this.
（発明が解決しようとする問題点）
この発明は、上記の問題に鑑みてなされたものであって
、とくに半田付は後ソルダーレジストがＳｎ Ｐｂスル
ーホールのようテ、塗膜面がしわにならないで、半田付
は後も外観が非常に綺麗に保たれ、かつ酸化変色がない
スルーホール印刷配線板の製造方法を提供することを主
たる目的としているものである−
（問題を解決するための手段）
この発明によるスルーホール印刷配線板の製造方法は、
常伝によってスルーホーＡ／を形成した銅張積ノ鰺板に
化学Ｃｕめつき処理およびネガティブめっきレジスト処
理を順次に施し、矢にスルーホールを含むパターン全面
に電解の光沢Ｓｎめっき全施し、不要になった前記めっ
きレジスト全除去し、次にエツチング処理によってパタ
ーン以外の導体を除去し、フュージング後にソルダーレ
ジストによるマスキング処理全施すことを特徴としてい
るものである。(Problems to be Solved by the Invention) This invention was made in view of the above-mentioned problems, and in particular, when soldering, the solder resist after soldering is like a SnPb through-hole, and the coating surface does not wrinkle. The main objective is to provide a method for manufacturing through-hole printed wiring boards that maintains a very clean appearance even after soldering and is free from oxidative discoloration. ) The method for manufacturing a through-hole printed wiring board according to the present invention includes:
Chemical Cu plating treatment and negative plating resist treatment are sequentially applied to the copper-clad laminated mackerel board on which through-holes A/ have been formed according to tradition, and electrolytic bright Sn plating is applied to the entire pattern including the through-holes on the arrows, making it unnecessary. The present invention is characterized by completely removing the plating resist, then etching to remove the conductor other than the pattern, and after fusing, completely masking with solder resist.
（実施例）
以下、この発明を、その実施の一例を示した図面にもと
づいて具体的に説明する。(Example) Hereinafter, the present invention will be specifically described based on drawings showing an example of its implementation.
第１図ないし第９図は、スルーホール印刷配線板の製造
工程順序を示す銅張積層攻の断面図、第６Ａ図ないし第
９Ａ図は第６図ないし第９図にそれぞれ対応する銅張積
層板の平面図である。Figures 1 to 9 are cross-sectional views of copper-clad laminates showing the manufacturing process order of through-hole printed wiring boards, and Figures 6A to 9A are copper-clad laminates corresponding to Figures 6 to 9, respectively. It is a top view of a board.
第１図はスルーホール印刷配線板用の銅張積層板を示し
たもので、（１）は絶縁板、（２１Ｆｉ銅箔体であって
、ワークサイズに裁断されている。FIG. 1 shows a copper-clad laminate for a through-hole printed wiring board, where (1) is an insulating plate and a (21Fi) copper foil body, which is cut to the work size.
第２図は、前記銅張積層板にスルーホール用の下穴（ｌ
ａ）ｅドリル加工であけた状態１示し、第３図は銅箔体
及び穴内の全面に化学Ｃｕめつき（３）を施した状、報
を示し、第４図はネガティブめっきレジスト（４）を印
刷で施した状態を示し、第５図は電解Ｃｕめつき（５）
全施した状ｊｐｌＡｋ示したものである。Figure 2 shows pilot holes (l) for through holes in the copper clad laminate.
a) Figure 1 shows the hole made by e-drilling, Figure 3 shows the copper foil body and the entire inside of the hole with chemical Cu plating (3), and Figure 4 shows the negative plating resist (4). Figure 5 shows electrolytic Cu plating (5).
This shows the fully applied state.
上記の工程は従来のパターン法によるもので、これにパ
ネル法による工程が組合わされる。以下にこの発明方法
による処理工程が示されている。The above steps are based on the conventional pattern method, which is combined with a panel method. The processing steps according to the method of the invention are shown below.
第６図および第６Ａ図は、スルーホールのホール内を含
むパターン全面に電解の光沢Ｓｎめつき（６）を施した
状態を示したものである。FIGS. 6 and 6A show a state in which the entire surface of the pattern including the inside of the through-hole is coated with electrolytic bright Sn plating (6).
第７図および？５７Ａ図は、第４図で施しためつきレジ
スト（４）のうち、不要になっためつきレジスト部分を
除去した状態を示したものである。Figure 7 and ? FIG. 57A shows a state in which the unnecessary smudge resist portion of the smudge resist (4) applied in FIG. 4 has been removed.
第８図および第８Ａ図は、第６図で施したＳｎめっきを
腐蝕させないで、銅箔体（２）のみ腐蝕させるエッチャ
ント、例えばアルカリエッチャント、過硫酸アンモなど
のエッチャントでエツチング処理上節し、そのあと活性
処理を行い、さらにフュージング処理を施したものであ
る。8 and 8A show that an etching process is performed using an etchant that corrodes only the copper foil body (2) without corroding the Sn plating applied in FIG. 6, such as an alkaline etchant or ammonium persulfate; After that, an activation treatment was performed, and a fusing treatment was further performed.
第９図およびｇＱＡ図は、最後にソルダーレジストによ
るマスキング（７）を施した状態金示したものである。FIG. 9 and the gQA diagram show the state in which masking (7) with a solder resist is finally applied.
上記の製造方法において、電解の光沢Ｓｎのめつき処理
を施した理由は、電解Ｃｕめつきの保護層として耐蝕性
を有するＳｎ ｆ形成することにより、強靭な被膜とな
り、しかも結晶４造の細かい平滑なめつき析出面が得ら
れるからである。In the above manufacturing method, the reason for performing the electrolytic glossy Sn plating process is that by forming a corrosion-resistant Sn f as a protective layer for the electrolytic Cu plating, it becomes a strong coating, and it also has a fine smooth surface with four crystals. This is because a tanned precipitation surface can be obtained.
しかして上記製造方法によれば、下記の効果が得られる
。According to the above manufacturing method, the following effects can be obtained.
１）前記処理方法で得られたスルーホール印刷配線板に
よれば、半田付は後、ソルダーレジストがＳｎ Ｐｂス
ルーホールのように塗膜面がしわにならないで、半田付
は後も外観が非常に綺麗である。1) According to the through-hole printed wiring board obtained by the above treatment method, the solder resist does not wrinkle after soldering unlike SnPb through-holes, and the appearance remains very good even after soldering. It is very beautiful.
２）Ｓｎ層が酸化防止、耐蝕性の保護層となっているた
め、銅箔と異って大気の接触による酸化、熱処理工程に
よる酸化変色が無く、ソルダーマスクなしでパターン導
体Ｓｎの状態で露出させても銅箔のような著しい酸化変
色はない。2) Since the Sn layer serves as an anti-oxidation and corrosion-resistant protective layer, unlike copper foil, there is no oxidation due to contact with the atmosphere or oxidation discoloration due to heat treatment, and the Sn layer can be exposed as a patterned conductor without a solder mask. There is no significant oxidation discoloration like with copper foil.
３）電気光沢Ｓｎめっき液の組成はＳｎ Ｐｂめっき液
の組成に比較して単純なため、管理がしやすい。3) The composition of the electro-bright Sn plating solution is simpler than that of the SnPb plating solution, so it is easier to manage.
４）ＳｎＰｂめつきの冶仕は、めっき叡を組成している
ホウフッ化水素ばベースのものが多いため、公害処理が
非常に困難であるが、光沢Ｓｎめっき液は硫酸ペースで
もできるので公害処理が簡単である。4) Since the SnPb plating process is often based on borohydrogen fluoride, which is the composition of the plating agent, it is very difficult to treat pollution. However, since the bright Sn plating solution can be used with sulfuric acid paste, it is easy to treat pollution. It's easy.
（発明の効果）
以上に延べたように、この発明のスルーホール印刷配線
板の製造方法によれば、従来方法に比べて品質ならびに
性能に格段と優れた印刷配線板を簡単容易に製造するこ
とができる。(Effects of the Invention) As described above, according to the method for manufacturing a through-hole printed wiring board of the present invention, a printed wiring board with significantly superior quality and performance compared to conventional methods can be easily manufactured. Can be done.
第１図ないし第９図は、この発明の一実施例を示したも
ので、スルーホール印刷配線板の製造工程順序を示す銅
張積層板の断面図、第６Ａ図ないし第９Ａ図は前記第６
図ないし第９図に対応する平面図である。
（１）・・・絶縁板、（２）・・・銅箔体、（１ａ）・
・・下穴、（３）・・・化学Ｃｕめつき、（４）・・・
ネガティブめっきレジスト、（５） ・を解Ｃｕめつき
、（６）−’に解光沢Ｓｎめつさ、（７）・・−マスキ
ング。1 to 9 show one embodiment of the present invention, and FIGS. 6A to 9A are cross-sectional views of a copper-clad laminate showing the manufacturing process order of a through-hole printed wiring board, and FIGS. 6
FIG. 9 is a plan view corresponding to FIGS. (1)...Insulating plate, (2)...Copper foil body, (1a)...
...Preparation hole, (3)...Chemical Cu plating, (4)...
Negative plating resist, (5) ・Resolved Cu plating, (6) ・Resolved gloss Sn resist, (7)...- Masking.
Claims (1)
学Ｃｕめつき処理およびネガティブめつきレジスト処理
を順次に施し、次にスルーホールを含むパターン全面に
電解光沢Ｓｎめつきを施し、不要になつた前記めつきレ
ジストを除去し、次にエッチング処理によつてパターン
以外の導体を除去し、フユージング後ソルダーレジスト
によるマスキング処理を施すことを特徴とするスルーホ
ール印刷配線板の製造方法。The copper-clad laminate is sequentially subjected to through-hole formation, chemical Cu plating treatment, and negative plating resist treatment using conventional methods, and then electrolytic bright Sn plating is applied to the entire pattern including the through holes, eliminating unnecessary A method for manufacturing a through-hole printed wiring board, which comprises removing the worn plating resist, removing conductors other than the pattern by etching, and performing masking with a solder resist after fusing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18261986A JPS6340395A (en) | 1986-08-05 | 1986-08-05 | Manufacture of through-hole printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18261986A JPS6340395A (en) | 1986-08-05 | 1986-08-05 | Manufacture of through-hole printed interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340395A true JPS6340395A (en) | 1988-02-20 |
Family
ID=16121455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18261986A Pending JPS6340395A (en) | 1986-08-05 | 1986-08-05 | Manufacture of through-hole printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340395A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5789296A (en) * | 1980-11-26 | 1982-06-03 | Sony Corp | Method of producing printed circuit board |
-
1986
- 1986-08-05 JP JP18261986A patent/JPS6340395A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5789296A (en) * | 1980-11-26 | 1982-06-03 | Sony Corp | Method of producing printed circuit board |
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