JPS63316987A - Video judgment device - Google Patents

Abstract

PURPOSE:To freely vary the direction and the speed of scroll of a still picture only by operating a single scroll dial, by designating the direction of the scroll corresponding to the rotational diraction of a scroll dial, and designating scroll speed corresponding to as angle of rotation. CONSTITUTION:The frequency of a scroll speed variable clock pulse S5 supplied to the clock pulse input terminal CLK of a counter 100 is varied corresponding to the angle of rotation of the scroll dial. When the scroll dial is rotated in a clockwise direction, the counter 100 starts a count up operation, and when it is rotated in a counter-clockwise direction, the counter 100 starts a count down operation, and the still picture on a display screen is scrolled horizontally by eight bits at every increase/decrease of the value of the counter 100. Thus, it is possible to vary freely both the scroll direction and the scroll speed of the still picture on the display screen only by operating the single scroll dial.

Description

Detailed Description of the Invention "Field of Industrial Application" This invention is applicable to video judgment used for determining the finishing order in horse races, bicycle races, boat races, auto races, etc., and for determining the shape of objects moving at high speed and reading characters. Regarding equipment.

“Prior Art” For example, slit-type cameras are widely used to determine the finishing order in horse races, bicycle races, and the like. The schematic configuration of this slit type camera is as shown in FIG.

In this figure, l is a lens, 2 is a slit plate for forming the slit 2a, and 3 is a film, which are housed in a camera case C. And goal line 4
The film 3 is arranged so that the image of the object above is formed on the film 3 through the lens l and the slit 2a, and the film 3 is attached to a moving object (in this case, a racehorse) 5 passing over the goal line 4.
By moving and rewinding at a speed corresponding to the direction of movement of the moving object 5 and in the opposite direction to the moving direction of the moving object 5, only the moving object 5 that has passed over the goal line 4 is continuously imprinted on the film 3 over time. . In this case, goal line 4
The image of the stationary object above (e.g. background) is always in slit 2a
Since it passes through the film 3 and reaches the film 3, it is imprinted in a band shape along the moving direction of the film 3, and is not imprinted as an actual shape. Then, the judge visually checks the developed film 3 and determines the order of arrival of the plurality of moving objects 5 that have passed over the goal line 4.

By the way, in horse racing, bicycle racing, etc., it is desired to determine the finish order quickly, but the above-mentioned method requires a certain amount of time for film development and the like. Therefore, the present applicant previously proposed Japanese Patent Application Laid-Open No. 133355/1983 as an image judgment device that can perform judgment work quickly and easily.

This image judgment device images a moving object 5 passing over a goal line 4 in the vertical direction using a line sensor camera having a plurality of photosensitive elements arranged one-dimensionally, and receives a video signal output from the line sensor camera. The pixel data is sequentially converted into digital pixel data, this pixel data is continuously written for multiple screens into the image memory, and then the pixel data corresponding to the required screen is read out from this image memory and converted into an analog video signal. By supplying a video signal to the television monitor, a still image of a desired screen is displayed on the television monitor. In addition, this video judgment device is equipped with a scroll display function that continuously moves the still image displayed on the monitor TV in the horizontal direction across multiple screens. Pressing the screen selection switch enables scrolling from the selected screen, then specifying the scroll direction (right or left) with the scroll direction designation switch, setting the movement speed with the scroll speed setting volume, Furthermore, by pressing the scroll switch, the still image will scroll in the specified direction and at the set speed. The judge then judges the finishing order while looking at the scroll screen.

"Problems to be Solved by the Invention" By the way, in the conventional video judgment device described above, a switch for specifying the scroll direction and a volume for specifying the scroll speed were provided separately. , the operation when scrolling still images on a monitor television was extremely complicated. Therefore, it has been a challenge to improve operability, especially during scroll display.

This invention was made in view of the above-mentioned circumstances, and an object of the present invention is to provide an image judgment device that can perform judgment work quickly and easily, and in addition, improves operability during scrolling. It is said that

"Means for Solving the Problems" This invention provides images of l lines along a predetermined reference line of a moving object passing on a predetermined reference line, arranged one-dimensionally for each type 1 storage time. a line sensor camera that simultaneously captures data using a plurality of photosensitive elements and sequentially outputs each pixel signal output from each of the photosensitive elements as a video output signal; and a line sensor camera that sequentially converts the video output signal of the line sensor camera into pixel data. By sequentially storing the pixel data supplied from the first converting means and the first converting means, pixel data for a plurality of temporally continuous screens are stored. a readout unit that sequentially reads out one screen worth of pixel data from an arbitrary readout area; a second conversion unit that converts the pixel data read out by the readout unit into a video signal; a display means for displaying a still image based on a video signal, the image determination device comprising: a scroll dial that can be rotated; and scrolling of the still image displayed on the display means according to the rotational direction of the scroll dial. Generates a first operation signal for specifying a direction, and also generates a second operation signal for specifying a scroll speed of a still image displayed on the display means according to a rotation angle of the operation dial. and readout area specification for sequentially resetting the readout area based on the first and second operation signals, and thereby specifying the newly set readout area to the readout means one by one. It is characterized by having the means.

"Operation" At the same time as the moving object passes the reference line, pixel data corresponding to the object image of the moving object is sequentially written into the storage means, and then among the pixel data for multiple screens once stored in this storage means. One screen worth of pixel data is sequentially read out from the readout area designated by the readout area designation means, and a still image is displayed by the display means. here,
When the scroll dial is rotated, the operation signal generating means generates first and second operation signals corresponding to the rotation direction and rotation angle of the scroll dial, respectively, and supplies them to the reading area specifying means, and the reading area specifying means The means sequentially resets the readout area based on the first and second operation signals, and specifies the newly set readout area one by one to the readout means. As a result, the still image displayed by the display means scrolls in a moving direction (for example, right or left direction) that corresponds to the rotation direction of the scroll dial and at a moving speed that corresponds to the rotation angle of the scroll dial. do.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) Overall composition.

FIG. 1 is a block diagram showing the overall configuration of an image judgment device according to an embodiment of the present invention. The image judgment device shown in this figure is roughly divided into a line sensor camera 6, an image storage device 7, and an operator. a control box 8 for referees, a control box 8a for referees, a monitor television 9a,
It consists of a VTR (video tape recorder) 9b and a TR monitor television 9C. The line sensor camera 6 is placed on a line of sight M parallel to the goal line 4, and the image storage device 7, operator control box 8, VTr (9b) and monitor television 9c are operated by an operator inside the building. It is installed in a place where the
An umpire control box 8a and a monitor television 9a are installed at a location where the umpire makes decisions.

The line sensor camera 6 has a lens IO and COD (Cha
It is composed of a line sensor 11 and an output amplifier 12. The line sensor 11 is a one-dimensional array of 51
It is composed of a photoelectric conversion section 13 having a photodiode (photosensitive element) for two pixels, and an output shift register section 14, and is arranged so as to image the goal line 4 in the vertical direction. Then, the object image of the moving object 5 passing over the goal line 4 forms an image on the photoelectric conversion unit 13 via the lens lO, is converted into an electric signal (charge) in the photoelectric conversion unit 13, and l charge is accumulated. Each pixel is simultaneously (in parallel) transferred to the output shift register unit 14 in synchronization with a scanning timing signal S T S (phototransfer pulse) supplied from the outside every time, and a scanning timing signal 5TSe is The signals are sequentially (serially) output from the output shift register unit 14 to the output amplifier 12 in synchronization with the transfer pulse (transfer pulse), amplified by the output amplification 'at2, and output as a vertical scanning video signal vS. Furthermore, the monitor televisions 9a and 9c are configured with CRTs (cathode ray tubes).

Next, in the image storage device 7, 21 is an analog vertical scanning video signal S supplied from the line sensor camera 6.
S, 6 b corresponding to the shading (brightness) of each pixel
It is an A/D (analog/digital) converter that converts it into digital pixel data PD, and when the level of the vertical scanning video signal VSS is the lowest within a predetermined range, it outputs "oooooo" as pixel data PD, When the level of the vertical scanning video signal VSS is the highest within a predetermined range, "111111" is output as pixel data PD.

Pixel data P output from this A/D converter 21
D is supplied to the data input terminal DI of the video memory 22.

The video memory 22 sequentially stores the pixel data PD output from the A/D converter 2I under the control of the control circuit 23, and stores the pixel data PD outputted from the A/D converter 2I sequentially under the control of the control circuit 23.
It has a storage capacity capable of storing at least 8 frames (screens) of bit pixel data PD. The detailed configuration of this video memory 22 will be described later.

The control circuit 23 controls the write operation and read operation of the video memory 22, and controls the A/D converter 21 and the D/A under the instructions of the control boxes 8 and 8a.
It controls the conversion timing of the converter 24, etc. When writing and reading pixel data PD, it supplies write and read address data AD to the video memory 22, as well as RASC row address strobe) signal, CAS ( column address strobe)
and a WE (write enable) signal. 2
4 is a D/A (digital/analog) converter that converts the horizontal readout pixel data I-I P D outputted from the data output terminal 1) O of the video memory 22 into a video signal S; A video synchronization synthesis circuit that combines the synchronization signal 5YNC and the scale signal SS and outputs a composite video signal CVS; 26 is a composite synchronization signal 5YNC and a horizontal synchronization signal HD corresponding to the composite synchronization signal 5YNC;
and a synchronization signal generation circuit that generates a vertical synchronization signal VD;
27 is a scale setting signal S supplied from the control circuit 23
A scale signal generation circuit 28 that generates a scale signal SS based on SS is configured with a timer 28a, and a time data generation circuit that generates elapsed time data TD based on a timer control signal TC9 supplied from the control circuit 23. It is a circuit.

(2) Configuration of operator control box 8.

The control box 8 instructs the control circuit 23 to perform various operations in a recording mode and a playback mode (consisting of a VTR mode and a scroll mode), which will be described later. This control box 8
, 30 is a recording start/interrupt switch, and when this recording start/interrupt switch 30 is pressed, an internally built-in LED (light emitting diode) 30a lights up to enter the recording mode, and at the same time an LED 31 for recording mode display is activated. lights up, and the control circuit 23 starts writing the pixel data PD. When the recording start/interrupt switch 30 is pressed again during this recording mode, the LED 30a turns off and the writing operation by the control circuit 23 is temporarily suspended. Furthermore, when the recording start/interrupt switch 30 is pressed again, the writing operation by the control circuit 23 is resumed.
When the writing operation for eight frames is completed, the recording mode is canceled and both the LED 30a and the recording mode display LED 31 are turned off. Reference numeral 33 denotes an LED that indicates that a recording start signal changeover switch (not shown) has been switched to the external side. enters recording mode. 32-1 to 32-
8 and 32a to 32d are LEDs that display, by frame number, to which address of the video memory 22 the control circuit 23 is currently writing or reading pixel data PD. That is, when writing or reading pixel data PD corresponding to the first frame, LED3:1. lights up, and similarly, corresponding to the 2nd to 8th frames, LED 32a and LED
32-, 32-, turn on sequentially. Also, LED32
b, 32c, and 32d are provided in case the storage capacity of the video memory 22 is expanded, and the LED 32b lights up corresponding to the 9th to 16th frames, and Corresponding to the th frame, LED3
2c is lit, and the LED 32d is lit corresponding to the 24th to 32nd frames.

34 is a VTR mode switch, and when this VTR mode switch 34 is pressed, the internal LED
34a lights up and one of the playback modes is v'.
r It becomes rt mode. In this VTR mode, the control circuit 23 sequentially reads out pixel data PD corresponding to the first frame from the video memory 22. As a result, the first frame is displayed on the monitor televisions 9a and 9c. In addition, 35 is a VTR recording start switch,
36 is a VTrL scroll speed setting knob,
In the V'r R mode described above, when the VTR recording start switch 35 is pressed, the internal LE
D35a lights up and the still image displayed on monitor TVs 9a and 9c scrolls horizontally to the 8th frame at the moving speed set by the VTR scroll speed setting knob 36. The LED 35a turns off. In this VTR mode, if the record button of the VTR 9b is set, the scrolling of the still image will be recorded by the VTR 9b. Further, 37 is a reset switch that cancels the above-described scrolling operation and returns to the first frame.

41 is a time start switch, and this switch 4
When 1 is pressed, the internal ED 41a lights up, and at the same time, the timer 28a in the time data generation circuit 28 starts measuring time, and the time data generation circuit 28 starts clocking every 1/10 seconds. Alternatively, the elapsed time data TD is supplied to the A/D converter 21 and the elapsed time display 42 in the control box 8 in units of l/loo seconds, respectively.

43 is a time on/off switch, and when this switch 43 is pressed, an internal LED 43a lights up, and if it is in recording mode, the elapsed time output from the time data generation circuit 28 is displayed. Data TD is superimposed on pixel data PD in A/D converter 21 and written into video memory 22 . 44 is a time reset switch, and when this switch 44 is pressed, the timer 28a is reset. Reference numeral 45 denotes an indicator lamp that indicates that the time start signal changeover switch (not shown) has been switched to the external side, and when lit, an external time start signal ETS is supplied from the outside in place of the fourth time start switch described above. Accordingly, the timer 28a starts timing operation. The time counting operation of the timer 28a stops when the recording mode ends.

49 is a video out positive/negative changeover switch, and when this switch 49 is pressed, the built-in LE
D49a lights up and the inverted signal IS is sent via the control circuit 23.
is supplied to the video synchronous synthesis circuit 25, where the composite video signal CvS is inverted and a negative screen is displayed on the display screen of the monitor television 9. Also, when the switch 49 is pressed again, the LED 49a
goes out and the normal positive planting screen is displayed. 5O is a video out on/off switch, and when this switch 50 is pressed, an internal LED 50a lights up, and an erase signal ES is supplied to the video synchronous synthesis circuit 25 via the control circuit 23, and the video synchronous synthesis circuit 25 is started. A black signal that does not display anything is output from the circuit 25 as the composite video signal CVS.

52 is a right/left changeover switch, which is set to the right side when the moving object 5 moves in front of the line sensor camera 6 from right to left; otherwise, it is set to the left side. As a result, the pixel data P is stored in the video memory 22.
The designation order of addresses when writing D is changed, and in the reproduction mode, a moving object image is displayed on the display frames of monitor televisions 9a and 9c in the same direction as the actual moving direction of moving object 5.

53 is one of the line sensors 11 in the line sensor camera 6
, the scanning speed for each line (one charge accumulation time of the photoelectric conversion unit 13, that is, the scanning timing signal STS
It is a line scan time changeover switch that switches the time from phototransfer pulse to the next scan timing signal STS, and has a line scan time changeover switch of 2 m5ec (0,
5KIIz), I m5ec (lKHz), 0.5m5
ec(2K II z), 0.25m5ec(4KH
It is possible to switch to any one of z). A video signal level meter 51 displays the peak value of the vertical scanning video signal VVS output from the line sensor camera 6, and is used when setting the aperture value of the lens 10 of the line sensor camera 6.

(3) Configuration of the referee control box 8a.

The control box 8a instructs the control circuit 23 to perform various operations in a scroll mode, which will be described later. In this control box 8a, 53 is a standard/variable changeover switch, and when this switch 53 is pressed, an internal LED 53
a lights up, and the still image displayed on the monitor television 9a can be enlarged or reduced in the horizontal direction. In this case, the enlargement rate or reduction rate is set by the enlargement/reduction setting device 54.
It is possible to set it continuously. 5
5 is a scroll mode switch, and this switch 5
When 5 is pressed, the internal LED 55a lights up and the scroll mode is entered. Reference numeral 56 designates a scroll dial for operating a scroll direction/speed setting device 76, which will be described later.In the scroll mode, the scroll dial 56 is used to specify the frame direction and scroll speed of a still image displayed on the monitor television 9a. It is. 57 is a scroll speed setting switch that sets the scroll speed in three stages: "fast", "standard", and "slow".

Further, 58 is a video scale on/off switch, and when this switch 58 is pressed, an internal LED 58a lights up, and the scale signal SS generated by the scale signal generation circuit 27 is transmitted to the video synchronization synthesis circuit 25. is superimposed on the video signal vS, and a video scale line is displayed in the vertical direction, that is, parallel to the scanning direction of the line sensor 11, on the display screen of the monitor television 9a.

In this case, the horizontal position of the scale line is set by the video scale position setting knob 59, and the number of scale lines is set to one or multiple by the scale line single line/double line changeover switch 60. is set. Furthermore, 62-, ~62-.
and 62a to 62d are LEDs that function similarly to the LEDs 32-1 to 321 and 32a to 32d of the control box 8 described above.
Whether writing or reading is being performed is displayed for each frame number. An LED 63 indicates that the recording mode is in progress, and an LED 64 indicates that the VTR mode is in progress.

(4) Configuration of video memory 22 and method of writing/reading pixel data PD.

As shown in FIG. 2(a), the video memory 22 is composed of eight (layers) memory blocks M1 to M8, each of which has 6g! 256Kx
It is composed of l-bit DRAM (dynamic RAM). The six DRAMs of each memory block Ml-M8 have one set of column addresses (0 to 511).
) and the row address (0 to 511), so that 6-bit pixel data PD for one pixel is written in parallel and read out in parallel.

Next, the case of writing pixel data PD into the video memory 22 will be described. Here, in order to distinguish the pixel data PD for each pixel, P n, m (n = 0 to 511
．． m = 0 to 4095).

First, the vertical scanning video signal VSS for l scanning periods sequentially output from the line sensor camera 6, that is, the vertical scanning video signal VSS for 512 pixels corresponding to one column in the vertical direction in the i frame, is sent to the A/D converter 21. Each pixel is sequentially converted into 6-bit pixel data, and sequentially supplied to the data input terminal DI of the video memory 22. Then, pixel data P for 512 pixels in the first column. ,. ~P
511.0 is sequentially written to the locations specified by column address 0 and row address 0 to 511 of memory block M1, and pixel data P0,1 to P3.1 for 512 pixels in the next second column are written. are sequentially written to the locations specified by the column address 0 and the row addresses 0 to 511 of the memory block M2. Similarly, pixel data for 512 pixels in the third column P O+t to P s+++t
is the pixel data P for 512 pixels in the fourth column in the memory block M3. 9. ~P Sll+3 is memory block M
4, pixel data P0.7 to PSII+7 for 512 pixels in the eighth column are sequentially written into the memory block M8. Further, pixel data Pa for 512 pixels in the ninth column. ~Ps□, e is memory block M1
The column address of 110 and the column address of θ to 511 are sequentially written. Similarly, as shown in FIG. 2(b), pixel data of 512 pixels for one scanning period of the line sensor camera 6 is sequentially written in the column direction (vertical direction). Then, pixel data Po of 512×512 pixels forming the first frame.

~P Sll+Sll is 8 memory blocks M1~
The pixel data constituting the second, third, . . . 8th frames are sequentially written to each storage area of M8, A+, and are written to each memory block M1 to M8 in the same way.
8 storage areas A t , A s . . . As. In this case, column addresses and row addresses are assigned to each of the storage areas A1 to A8, as shown in Table 1 below.

Table 1 Storage area Column address Row address A,
0~63 0~511A, 64~1
27 0~511A3 128~191 0~5
ttA, 192-255 0-511As
256~319 0~511As 320
~383 0~511A? 384-447 0
~511A8 448~511 0~511 Next,
Regarding the case of reading pixel data PD from the video memory 22, let us consider the case in which a still image of 512 dots in the horizontal direction x 489 dots in the vertical direction is displayed on the display screen of the monitor television 9a in standard time, as shown in FIG. Let's explain using an example.

In this case, pixel data PD for 512 pixels is sequentially read out in the row direction (horizontal direction) during each image display period of one horizontal scanning period of the monitor television 9a, ie, every effective horizontal scanning period. Also, since the display is performed using the interlaced method, odd row addresses (1, 3, 5, etc.)
..., 511) pixel data PD read out by
The first field (odd field) is displayed, and even row addresses (0, 2, 4, ......, 5
The second field (even field) is displayed by the pixel data PD read out by step 10), and one frame is displayed by the first field and the second field.

To explain this in more detail, first, pixel data P1 corresponding to the first eight dots of the first row of the first field.
．． . ~Pl+,? Read out. At this time, video memory 2
By specifying a row address "l" and a column address "0" for P1.2, pixel data P1. . ~P3.
7 is read from each memory block M1 to M8. Subsequently, by incrementing the column address by 1 while keeping the row address "l", continuous pixel data P1 . Duck (--8 to 51N) is read out 8 pixels at a time.

The pixel data P+, I (11=0 to 511) for 512 pixels thus read out is displayed on the display screen of the monitor television 9a as the first line of the first field. Similarly, the pixel data Ps, II (I11=0 to 5) corresponding to the second row of the first field are
11), pixel data P 5+1(-
= θ ~ 511), ... Pixel data corresponding to the 256th line P s++, ff1 (ll = 0 ~ 511)
is read out, and the reading of the first field is completed. Then, the first field of the second field (even field)
Pixel data Po, n+(mouth=θ~511) corresponding to the row
) is read out, followed by pixel data p,,m (m=O~511) corresponding to the second row of the second field.
, pixel data P corresponding to the third row 4. l1l(11
1=0~5If),...Pixel data PHa,m corresponding to the 256th line (m=O~511)
is read out, and the reading of the second field is completed. With these first and second fields,
A still image corresponding to 1 frame of 512 dots in the horizontal direction and 489 dots in the vertical direction is displayed on the display screen of the monitor television 9a. Note that the reason why the number of dots in the vertical direction is not 512 is due to the vertical blanking period.

(5) Referee control box 8a and control circuit 2
Detailed configuration of the main parts of 3.

FIG. 4 shows the standard/variable changeover switch 53 and enlargement/reduction setting device 5 provided in the referee control box 8a.
4. Scroll direction/speed setter 76, scroll speed setting switch 57, and successive address generation circuit 70 forming a part of control circuit 23 in image storage device 7
FIG. 2 is a block diagram showing the configuration of FIG.

In this figure, various operation signals output from the judge control box 8a are transmitted through a line driver circuit 72 provided in the control box 8a and a line receiver circuit 73 provided in the image storage device 7. The signal is then supplied to each circuit described later.

Here, the scroll direction/speed setter 76 is set as shown in FIG.
As shown in (a) and (b), a variable resistor 75, a scroll dial 56 and a disk 77 attached to the shaft 75a of this variable resistor 75, and this disk 77.
It consists of a pair of microswitches 78 and 79 that turn on/off depending on the rotation angle of the scroll dial 56, and when the mark 56a carved on the scroll dial 56 is located at the upper end, the variable resistor 75 is at the midpoint. The microswitches 78 and 79 are respectively arranged so that they are both in the OFF state. When the dial 56 is rotated clockwise, the lever of the microswitch 78 is biased by the semi-disc-shaped member 80 attached to the disc 77, and the microswitch 78 is turned on. In this case, the other microswitch 79 remains off.

Conversely, when the dial 56 is rotated counterclockwise, the lever 7 of the microswitch 79 is rotated by the member 80.
9a is energized, the microswitch 79 is turned on, and the microswitch 78 is turned off.

Next, in FIG. 4, the normally closed contacts NC of the microswitches 78 and 79 of the scroll direction/speed setter 76 are both grounded, and the normally open contacts No. of the microswitches 78 and 79 are both grounded. +
Connected to Vcc. And micro switch 7
When 8.79 is in the off state, each of their common contacts C conducts with the normally closed contact NC, and the ground level (“L”
"level)" signal, and conversely, when it is in the on state, each common contact C is electrically connected to the normally oven contact NO, and the +V
Outputs a cc (“H” level) signal. The output signal of the microswitch 79 is then sent as a scroll movement direction control signal S3 to an up/down control input terminal U/f of a first column address setting counter 100, which will be described later, via a line driver and receiver circuit 72.73.
The power signals of the microswitches 78 and 79 are each supplied to one input terminal of the Noah gate 84,
The output of this NOR gate 84 is the scroll start signal S
4 (row active) is supplied to the enable terminal ε of the counter 100 via the line driver and receiver circuits 72 and 73.

On the other hand, both ends of the resistor of the variable resistor 75 have a resistance of 81.82
The center tap of the resistor is grounded. When the scroll dial 56 is located at the center point, a ground level voltage is output from the variable resistor 75, and when the dial 56 is rotated clockwise or counterclockwise, the variable resistor 75 outputs a voltage at the ground level. ,
A voltage is output according to the rotation angle of the dial 56 with the midpoint as a reference. The output voltage of this variable resistor 75 is supplied to a control input terminal C of a VCO (voltage controlled oscillator) 92. This VCO 92 is an oscillator whose output frequency changes according to the voltage supplied to the control input terminal C, and the output of this VCO 92 is divided by three predetermined frequency division ratios in a frequency divider 93, and the frequency is fa,
Three types of clock pulses, fb and rc, are supplied to the selector 94 at the next stage. In this case, the frequency relationship is always ra > fb >"C. The selector 94 is
The frequency fa.

One of the three types of clock pulses, fb and fc, set by the scroll speed setting switch 57 is selectively output. That is, when the scroll speed setting switch 57 is set to "fast", the clock pulse of frequency "a" is selected, and the "standard" clock pulse is selected.
In the case of "slow", the frequency rb is selected, and in the case of "slow", the frequency fc is selected.
The clock pulse output from the line driver and receiver circuit 72. is used as a scroll speed variable clock pulse S5. '73 to the clock pulse input terminal CLK of the counter 100.

Next, the counter 100 for setting the first column address is 9.
It is composed of a bit presettable up/down counter, and its preset input terminal P is supplied with 9-bit initial address data from a selector 120, which will be described later.
The operation of counting the scroll speed variable clock pulses S5 is controlled by the scroll start signal S4. Further, this counter 100 is connected to the video memory 2
2, it functions as a counter that sets the first column address. Here, the first column address means, when reading out pixel data PD for one frame,
This is the start address of the column address, and is the pixel data PD displayed in the leftmost column of the l frame (for example,
In FIG. 3, pixel data Pa. ,P+,. , P3
．． . ,...) is an address for specifying. Further, this counter 100 is counted when the pixel data PD for eight screens is written into the video memory 22 and the recording mode is canceled, or when the
It is set by the initial screen setting signal supplied at the time the TR mode switch 34 is pressed.

The count value (9 bits) of the counter 100 for setting the first column address is transferred from its output terminal Q to the latch circuit 1.
01. This latch circuit 101 receives a frame pulse FP supplied from a memory drive pulse generation circuit 130, which will be described later. The count value of the counter 100 is latched by a pulse signal supplied immediately before the start of the frame period, and this count value is supplied to the preset input terminal P of the column address counter 102.

The column address counter 102 is composed of a 9-bit presettable up/down counter.
It normally functions as an up counter, and when an address inversion signal (row active), which will be described later, is supplied to the up/down control input terminal U/f), it functions as a down counter. Then, when the horizontal synchronizing pulse HDP is supplied from the memory drive pulse generation circuit 130 to the load terminal LD of the column address counter 102 immediately before the start of one horizontal period, the counter 1 latched in the latch circuit 101
Take in the count value of 00. Thereafter, each time the clock pulse CP is supplied from the memory drive pulse generation circuit 130 to the clock pulse input terminal CLK, the preset count value is incremented (+1). The count value of column address counter 102 is supplied from its output terminal Q to write/read address selector 140 as a subsequent column address.

The above configuration and row address generation circuit 103 constitute successive address generation circuit 70. This row address generation circuit 103 generates a read row address based on the frame pulse FP and horizontal synchronization pulse HDP supplied from the memory drive pulse generation circuit 130.

In addition to the successive column addresses, the write/read address selector 140 also includes the row address generation circuit 103.
A successive row address is supplied from write address generating circuit 141, and a write column address and a write row address are further supplied from write address generation circuit 141. The write/read address selector 140 selects a combination of a write column address and a write row address, or a combination of a subsequent column address and a write column address based on a write/read switching signal supplied according to the operation mode of the control circuit 23. One of the sets of read row addresses is supplied to the row/column address selector 142.

Furthermore, the row/column address selector 142 selects either the column address or the row address from the address input terminal AD0 of the video memory 22 based on the row/column switching signal R/C supplied from the memory drive pulse generation circuit 130. ~A D *.

In the configuration up to this point, when the scroll dial 56 is rotated clockwise, the micro switch 78
]" level signal is output, and the microswitch 79 outputs an "L" level signal, and as a result,
A scroll direction control signal S3 of "H" level is supplied to the up/down control input terminal U/I of the first column address setting counter 100, and a scroll start signal S4 of "L level" is supplied from the NOR gate 83 to the counter 1.
00 enable terminal r. This allows the counter! 00 starts an up-count operation and increments the count value every time a clock pulse is supplied to the clock pulse input terminal CLK. In this case, since the initial address data is preset in advance, the value added by 1 to the initial address data becomes the count value, and this count value is used to specify the pixel data to be displayed in the leftmost column of the l frame. Output as the first column address. As a result, the display screen scrolls to the right by 8 bits every time the count value of the counter 100 increases by +1.

On the other hand, the clock pulse input terminal CLK of the counter 100
Scroll speed variable clock pulse S supplied to
5 frequency is set using the scroll dial 56 as described above.
The scroll speed setting switch 57 changes the speed according to the rotation angle of the scroll speed setting switch 57.
c). Since the counting speed of the counter 100 changes depending on the frequency of the scroll speed variable clock pulse S5, the speed at which the first column address is added by 1 also changes accordingly.
The scroll speed of the display screen is switched in three stages by a scroll speed setting switch 57, and further changes continuously according to the rotation angle of the scroll dial 56.

Conversely, when the scroll dial 56 is rotated counterclockwise, the microswitch 78 outputs an "L" level signal and the microswitch 79 outputs an "H" level signal.
The counter 100 starts counting down, and the still image on the display screen is scrolled to the left by 8 bits every time the count value of the counter 100 decreases by 1. and,
When the scroll dial 56 is returned to the midpoint, the output of the Noah gate 83 becomes "+(" level, and the counter 10
0 stops the counter operation, and as a result, the still image on the display screen remains stationary without scrolling.

In this way, by simply operating the single scroll dial 56, the scrolling direction and scrolling speed of the still image on the display screen can be freely changed. The still image on the display screen is moved in exactly the same way as when determining the order of arrival while visually observing the film 3 (see Figure 8), that is, in the same way as moving the film 3 in the horizontal direction. You can avoid scrolling.

Next, the enlargement/reduction setting device 54 of the referee control box 8a is constituted by a variable resistor, and outputs a voltage according to the setting level of this variable resistor, and this voltage is used as an enlargement/reduction control signal S2. Level shift amplifier 10 via line driver and receiver circuits 72 and 73
5. Then, the enlargement/reduction control signal S2 is sent to the next stage A/D converter 1 by the level shift amplifier 105.
06 rated input voltage, and then converted into 8-bit digital data by the A/D converter 106. Here, if the enlargement/reduction setting device 54 is set to the minimum value, the output data of the A/D converter 106 will be “000Q 0000” in binary representation, and the enlargement/reduction setting device 54 will be set to the maximum value. When set, the output data of the A/D converter 106 is expressed in binary as “it 11
1111”.

The output data of the A/D converter 106 is transferred to the latch circuit 107 at the timing when the frame pulse FP is supplied.
is latched by the data selector 108 and supplied to one input terminal of the data selector 108. At the other input end of this data selector 108, there is a mark horizontal dot number setting switch 109 configured by a dip switch attached to the board.
, output data "10000000" for the lower 8 bits of a binary number of 640, which is the number of read pixels in one horizontal scanning period in standard time, is supplied. The select terminal S of the data selector 108 is supplied with a switching signal S1 from the standard/variable changeover switch 53 via the line driver and receiver circuits 72 and 73. When the selector switch 53 is set to the standard side, the output data of the standard horizontal dot number setting switch 109 is “10 Go 00
Go'' is selected and the standard/variable selector switch 53 is set to the variable side, the A/D converter 106
Output data “oo oo oo oo” ~ “1111
1111” to programmable divider 11.
0 setting terminal P and input terminal A of the adder circuit 111.

The programmable divider 11O includes a phase comparison circuit 112, an active low-pass filter tta, and a V
Together with the CO 114, it constitutes a +CPLL (7-Aze Locked Loop) pulse generator 115. That is, the programmable divider 110
The oscillation frequency fout of is divided by the frequency division number N supplied to the setting terminal P, and a signal of frequency Fs is supplied to the phase comparator 112.

Phase comparator 112 includes programmable divider 110
The phase of the output signal is compared with the horizontal synchronization signal HD supplied from the synchronization signal generation circuit 26 (see FIG. 1), and a signal corresponding to the phase difference is output. The detection output of this phase difference is converted to DC by an active low-pass filter tta, and this DC voltage is used to generate the oscillation frequency fou of the VCO 114.
t is controlled.

The PLL pulse generator l15 having such a configuration is
Since it operates so that the phase difference between the output signal of the programmable divider 110 and the horizontal synchronization signal HD is always a constant value, the frequency of the horizontal synchronization signal HD can be expressed as "r1", and the frequency of the output signal of the programmable divider 110 can be expressed as "rs". Then, the following formula holds.

rs=rr
......(1) Also, programmable divider 1
If the setting value of 1O (frequency division r&) is N, rs = rout/N --
(2) Therefore, the oscillation frequency rout of the VCO 114
is obtained from the following equation.

rouL=NXfr・”
-(3) Here, NTS C (National
Te1evision SystemConu++1t
The horizontal synchronization frequency in the tee) signal is 15.734kHz
z, so fout= N x 15.734 kHz −・
...(4).

Then, the output signal of the VCO 114 is transmitted to the memory drive circuit 1.
30, and the memory drive circuit 130 supplies the VCO 11 with
A clock pulse CP having a frequency of 1/8 of the oscillation frequency rout of 4 is generated, and a frame pulse FP is generated using this clock pulse CP as a reference.

Horizontal synchronization pulse HDP, row address strobe RAS
, column address strobe CAS, write enable signal WE, and row/column switching signal R/C.

The column address counter 102 receives a clock pulse C.
P is counted, and the count value is supplied to the video memory 22 as a successive column address, and then as shown in FIG.
As shown in (b), pixel data for 8 dots is read out for each column address. Then, the VCO1
As is clear from the above equation (4), the oscillation frequency rout of No. 14 is N times the horizontal synchronization frequency, and therefore,
Within l horizontal scanning period, column address counter 1
The count number of 02 is N/8, and the number of successive pixels is N.

Here, the voltage of the enlargement/reduction control signal S2, the output data of the A/D converter 106, the output data of the standard horizontal dot number setting switch 109, the setting value N of the programmable divider 110, and the The relationship between the number of successive pixels and the number of horizontal display dots within one horizontal scanning period is as shown in FIG. 6(a). That is,
Increase the set value N by ±20% based on 640 to 512 to 7.
68, the number of horizontal display dots (the number of horizontal dots displayed on one screen) within one horizontal display period can be increased or decreased by ±20% with respect to 512 dots. Therefore, for example, when the standard/variable changeover switch 53 is set to the variable side and the enlargement/reduction setting device 54 is set to the minimum value, as shown in FIGS. Pixel data of 408 dots (512 dots in one horizontal scanning period) related to image display is read out every effective horizontal scanning period and sent to the D/A converter 2.
As a result, a still image with 408 horizontal display dots is displayed on the display screen of the monitor televisions 9a and 9c, and the still image is displayed in the most expanded state in the horizontal direction. Ru. Conversely, if the enlargement/reduction setting device 54 is set to the maximum value, the video memory 2
2, pixel data of 616 dots (768 dots in one horizontal scanning period) is read out every effective horizontal scanning period and converted into a video signal VS.
The number of horizontal display dots on the display screens of a, 9 and c is 616.
A still image is displayed, and the still image is displayed in the most horizontally reduced state. Furthermore, when the standard/variable changeover switch 53 is set to the standard side, 512 dots of pixel data (640 dots in one horizontal scanning period) are read out from the video memory 22 every valid horizontal scanning period, and the video signal ■ S, and as a result, the monitor televisions 9a, 9
The number of horizontal display dots displayed on the display screen c is 512, and the still image is displayed at the standard magnification.

Next, the address inversion signal (low active) supplied to the up/down control input terminal U/[1) of the column address counter 102 and the select terminal S of the selector 120 is used to switch the right/left switch of the operator control box 8. It is supplied when the switch 52 is set to the left side. Then, the selector 120 normally inputs the 9-bit initial address data set in the initial address setting switch 117 to the first column address counter 1.
02 is supplied to the preset input terminal P, and when an address inversion signal is supplied to the select terminal S, the addition result of the adder circuit Ill is sent to the first column address counter 1.
00 to the preset input terminal P. The initial address setting switch 117 is used to set the first frame to be displayed, and in this embodiment, 0, which is the first column address of the first frame, is set. Furthermore, the adder circuit lit adds the data supplied to its input terminal A and the data supplied to its input terminal B, and outputs the addition result from its output terminal Y.
At its input end, there is a switch 11 for setting the initial address when reversing the write address, which is composed of a dip switch.
6 is supplied to the input terminal B, and the output data of the standard horizontal dot number setting switch 109 selected by the data selector 108 or the A/D converter 10 is supplied to the input terminal B.
6 output data are provided. Further, the write address inversion initial address setting switch 116 is set with appropriate setting data according to the enlargement/reduction ratio when reading out the video memory 22, and in this embodiment, the initial address setting switch 116 is set as shown in FIG.
(b) As shown in (maximum column address 511) - (
A column address 434 calculated by dividing the number of horizontal display dots (616) by 8 at maximum reduction is set.

(6) Explanation of operation during recording.

When determining the finishing order of a horse race using the video evaluation device configured as described above, first, the line scan time changeover switch 5 is
3 to set the scan speed of the line sensor 11 (one charge accumulation time of the photoelectric conversion unit 13) according to the approximate movement speed of the racehorse (moving object 5). this is,
If the scanning speed of the line sensor 11 is too fast compared to the moving speed of the racehorse, an object image extending in the horizontal direction (in the direction of movement of the racehorse) than the actual object image of the racehorse will be written in the video memory 22. , conversely, if the scanning bead is too slow, a horizontally contracted object image will be stored in the video memory 2.
This is because it is written to 2. Next, take a picture of the white object with the line sensor camera 6, adjust the aperture value of the line sensor camera 6 so that the pointer of the level meter 51 does not exceed a predetermined value, and set the line sensor camera 6 on the line of sight of the goal line 4. Place it on M. Further, the right/left selector switch 52 is switched depending on the direction of movement of the racehorse, and the time on/off switch 43 is turned on when it is desired to capture the elapsed time since the horse race started along with the object image. Also, confirm that the LEDs 33 and 45 are turned off and that the still signal changeover switch and the time start signal changeover switch are not switched to the external side.

Next, when the racehorse starts, the time start switch 41 is pressed. As a result, the elapsed time since the start is sequentially displayed on the elapsed time display 42. Thereafter, just before the leading racehorse passes the finish line 4, the recording start/interrupt switch 30 is pressed. Then, the recording mode is entered, and the control circuit 23 sequentially supplies the address data AD to the video memory 22, and at the same time, the vertical scanning video signal VVS supplied from the line sensor camera 6.
h< It is converted into pixel data PD by the A/D converter 21, and this pixel data PD is sequentially supplied to the video memory 22 via the switching circuit 20. Then, as shown in FIG. 7, the pixel data PD output from the A/D converter 21 is stored in the 11th frame F of the video memory 22.
The information is sequentially written in the direction of arrow V (vertical direction) from the first storage area A corresponding to number 1. And video memory 2
When the pixel data PD is written up to the eighth storage area A corresponding to the eighth frame F8 of No. 2, the recording mode is automatically canceled.

Here, in the recording mode mentioned above, time on/off
When the off switch 43 is turned on, as shown in FIG. l/10 seconds from display reference line TSL (
However, if the scan speed is 0.25m5ec, the time display line TL indicates this every time 1/100 seconds elapses.
is written into the video memory 22 together with the object image.

(7) Explanation of operation during playback.

Next, when the race ends and the recording mode described above is canceled, the first frame F1 is displayed on the display screen of the monitor television 9a, and the judge then switches the scroll mode switch of the control box 8a. 5
Press 5 to enter scroll mode.

From then on, by operating the scroll dial 56,
The desired screen is searched and the order of arrival is determined.

In this case, turning the scroll dial 56 clockwise scrolls the still image on the display screen to the right, and conversely, turning the scroll dial 56 counterclockwise scrolls the still image to the left.
Further, the larger the rotation angle of the scroll dial 56, the faster the scrolling speed becomes. In this case, the scroll speed can be largely changed in three steps using the scroll speed setting switch 57. In addition, the still image displayed on the display screen of the monitor television 9a is
If the object image of the actual racehorse is expanded or contracted in the horizontal direction, set the standard/variable selector switch 53 to the variable side and operate the enlargement/reduction setting @54 to make the still image horizontal. It can be enlarged or reduced in the direction and modified in the same way as the actual object image.

At this point, when the VTR mode switch 34 is pressed, the VTR mode described above is entered, and from then on, the scroll dial 5
6 is considered invalid. Also, press the video out scale on/off switch 58 to turn it on, superimpose and display the vertical video scale line on the display screen of the monitor television 9 on which the racehorse is displayed, and turn the video scale position setting knob. 59 to move the scale line left and right. As a result, even when multiple racehorses are displayed overlappingly on the display screen of the monitor television 9, for example, by aligning the scale line with the front end of the racehorses, the finishing order can be determined quickly and accurately. can be determined.

Note that in the embodiment described above, the video memory 22
Although the memory capacity of the 2000 is set to be 8 frames, by expanding the memory by adding more memory, the memory capacity can be increased to 16 frames, 24 frames, or 32 frames. .

"Effects of the Invention" As explained above, according to the present invention, there is provided a scroll dial that can be rotated, and a method for specifying the scroll direction of a still image displayed on a display means in accordance with the rotation direction of the scroll dial. an operation signal generating means for generating a first operation signal for specifying a scrolling speed of a still image displayed on the display means according to a rotation angle of the operation dial; Based on the first and second operation signals, the readout area for reading out one screen worth of pixel data from the storage means is sequentially reset, and the newly set readout area is used as the readout area for reading out the pixel data. Since the means is equipped with a readout area designation means for specifying one by one, it is possible to freely change both the scrolling direction and the scrolling speed of the still image by simply operating a single scroll dial. The still image can be moved left and right in exactly the same way as the conventional photo judgment, in which the order of finishing is judged by visually checking the film. 'll members will not feel any discomfort that it is a digital image (
, it is possible to achieve the effect that the determination work can be performed extremely smoothly and quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, and FIG. 2 is a diagram for explaining the configuration of a video memory 22 of the same embodiment and the addresses of pixel data written to this video memory 22. FIG. 3 is a diagram showing the relationship between the pixel data written in the video memory 22 and the display screen of the same embodiment, FIG. 4 is a block diagram showing the configuration of the main part of the same embodiment, and FIG. 5 (A) , (B) and (C) are a front view, a top view, and a rear view showing the configuration of the scroll direction/speed setting device according to the same embodiment, and FIGS. 6A and 6B are
is a diagram for explaining the enlargement/reduction function according to the same embodiment,
FIG. 7 shows monitor televisions 9a and 9 in the same embodiment.
FIG. 8 is a schematic configuration diagram showing the configuration of a conventional slit-type camera. 4...Goal line (reference line), 5...
・Moving object, 6...Line sensor camera, 7...
... Image storage device, 8a ... Referee control box, 9a ... Monitor television (display means), 11 ... CCD line scan image sensor, 21 ...・A/D converter (first conversion means), 22...video memory (storage means),
23... Control circuit, 24... D/A converter (second conversion means), 25... Video synchronization synthesis circuit, 56... Scroll dial, 70
... Read address generation circuit (reading means), 76
...Scroll direction/speed setter (operation signal generation means), 75...Variable resistor, 77...
・Disc, 78.79...Micro switch, 80
...Parts, 84...Noah Gate, 92
... VCo, 93 ... Frequency divider, 94 ...
...Selector, 57...Scroll speed setting switch, S3...Scroll movement direction control signal (first operation signal), S5...Scroll speed variable clock pulse (first operation signal) 2 operation signal), 10
0... Counter for setting the first column address (reading area specifying means). Applicant Yamaguchi Co., Ltd. Cinema Ikegami Tsushinki Co., Ltd. (A) No. Figure 5

Claims (1)

[Scope of Claims] An image of a moving object passing on a predetermined reference line for one line along the reference line is simultaneously captured every charge accumulation time by a plurality of one-dimensionally arranged photosensitive elements, and
a line sensor camera that sequentially outputs each pixel signal output from each of the photosensitive elements as a video output signal; a first conversion means that sequentially converts the video output signal of the line sensor camera into pixel data; By sequentially storing the pixel data supplied from the converting means, the pixel data for a plurality of temporally continuous screens are stored, and the pixel data for one screen is stored in the storage means and from a designated arbitrary readout area of the storage means. a reading means for sequentially reading pixel data; a second converting means for converting the pixel data read by the reading means into a video signal; and a still image based on the video signal supplied from the second converting means. A video judgment device having a display means for displaying a still image; an operation signal generating means for generating an operation signal and a second operation signal for specifying a scrolling speed of a still image displayed on the display means according to a rotation angle of the operation dial; The readout area designating means sequentially resets the readout area based on the first and second operation signals, and thereby specifies the newly set readout area one by one to the readout means. Video judgment device.