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JPS6331156A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6331156A
JPS6331156A JP61175057A JP17505786A JPS6331156A JP S6331156 A JPS6331156 A JP S6331156A JP 61175057 A JP61175057 A JP 61175057A JP 17505786 A JP17505786 A JP 17505786A JP S6331156 A JPS6331156 A JP S6331156A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
silicon film
gate
film
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61175057A
Other languages
Japanese (ja)
Inventor
Naoya Matsumoto
直哉 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61175057A priority Critical patent/JPS6331156A/en
Publication of JPS6331156A publication Critical patent/JPS6331156A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent emitter resistance from increasing and hfe from decreasing by a method wherein a bipolar transistor emitter electrode polycrystalline silicon film may be rendered thinner than a MOSFET gate polycrystalline silicon film. CONSTITUTION:A bipolar transistor emitter electrode polycrystalline silicon film is rendered thinner than a field effect transistor gate polycrystalline silicon film. On a silicon substrate 1, a MOSFET constituted of a source 4, drain 5, gate oxide film 6'', and gate 6, and the impurity-diffused region of a bipolar transistor base 7 are covered by a PSG film 3. Next, a contact window is pro vided in an oxide film 2 on the base 7 and PSG film 3. A polycrystalline silicon film is attached to the entire surface of a semiconductor chip, impurity ions are implanted into the polycrystalline silicon film, etching is accomplished by photolithography for patterning the polycrystalline silicon film into an emitter electrode 9, and then thermal diffusion is accomplished for the formation of an impurity-diffused layer for an emitter 8 under the emitter electrode 9.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に同一半導体基板上にバ
イポーラトランジスタと電界効果トランジスタとを混在
して形成した半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which bipolar transistors and field effect transistors are mixedly formed on the same semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来、絶縁ゲート型電界効果トランジスタ(以降MO3
FETと称す)は、ゲートをアルミニウム層から多結晶
シリコ膜に変えることによって、ゲートに自己整合的に
ソース及びドレインの不純物拡散層を形成でき、その結
果高密度な半導体装置が可能になると共に内部素子の特
性の製造上のばらつきを抑えることが出来るようになっ
た。
Conventionally, insulated gate field effect transistor (hereinafter referred to as MO3
By changing the gate from an aluminum layer to a polycrystalline silicon film, FETs (FETs) can form source and drain impurity diffusion layers in self-alignment with the gate, which allows for high-density semiconductor devices and internal It has become possible to suppress manufacturing variations in device characteristics.

一方、バイポーラトランジスタは、エミッタの不純物拡
散層の表面に直接アルミニウム層を堆積したエミッタ電
極の構造から、最近では、エミッタを形成する領域の表
面にイオン注入等により不純物を導入した多結晶シリコ
ン膜を形成し、これをエミッタの不純物拡散源として多
結晶シリコン膜の下に熱拡散によってエミッタの不純物
拡散層を形成し、更に多結晶シリコン膜の上に所定のパ
ターンでアルミニウム層を堆積してアルミニウム層のエ
ミッタ電極を形成している。このような構造では、 (i)アルミニウムの電極とエミッタの不純物拡散層と
の間で、多結晶シリコン膜の電極を介在させているので
、アルミニウムと不純物拡散層のシリコンとの相互拡散
によるアロイスパイクを防止して信頼性が向上する。
On the other hand, bipolar transistors have changed from an emitter electrode structure in which an aluminum layer is deposited directly on the surface of the impurity diffusion layer of the emitter to a polycrystalline silicon film in which impurities are introduced into the surface of the region where the emitter is formed by ion implantation, etc. This is used as an emitter impurity diffusion source to form an emitter impurity diffusion layer by thermal diffusion under the polycrystalline silicon film, and then an aluminum layer is deposited in a predetermined pattern on the polycrystalline silicon film to form an aluminum layer. It forms the emitter electrode of. In such a structure, (i) Since a polycrystalline silicon film electrode is interposed between the aluminum electrode and the emitter impurity diffusion layer, alloy spikes occur due to mutual diffusion between aluminum and the silicon of the impurity diffusion layer. This improves reliability by preventing

(ii)エミッタの不純物拡散層を極めて薄く形成でき
るという利点がある。
(ii) There is an advantage that the impurity diffusion layer of the emitter can be formed extremely thin.

そこで、バイポーラトランジスタとMOSFETとが同
一の半導体基板に形成された半導体装置では、バイポー
ラトランジスタのエミッタ電極とMOSFETのゲート
に多結晶シリコ膜を使うことによって、内部素子の高密
度化と半導体装置の高信頼度化が達成できる。
Therefore, in a semiconductor device in which a bipolar transistor and a MOSFET are formed on the same semiconductor substrate, by using a polycrystalline silicon film for the emitter electrode of the bipolar transistor and the gate of the MOSFET, it is possible to increase the density of internal elements and increase the density of the semiconductor device. Reliability can be achieved.

又、このような半導体装置は、従来、製造プロセスを簡
略化するために、同一の多結晶シリコン膜によってバイ
ポーラトランジスタのエミッタ電極及びMOSFETの
ゲートを形成するので、両者が同じ膜厚となっていた。
Furthermore, in order to simplify the manufacturing process, conventionally, in such semiconductor devices, the emitter electrode of the bipolar transistor and the gate of the MOSFET were formed using the same polycrystalline silicon film, so that both had the same film thickness. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上述した従来の半導体装置では、MOSFET
のソースとドレインとをゲートをマスクとしてイオン注
入によって自己整合的に形成するので、ゲートの多結晶
シリコン膜がマスクとしての役割りを果すためには最低
4000人の膜厚が必要となり、従ってバイポーラトラ
ンジスタのエミッタ電極の多結晶シリコン膜の膜厚も最
低4000人となってしまう。その結果、バイポーラト
ランジスタのエミッタ抵抗が大きくなると共にhreが
上がりにくいという欠点がある。
However, in the conventional semiconductor device described above, MOSFET
Since the source and drain of the gate are formed in a self-aligned manner by ion implantation using the gate as a mask, the polycrystalline silicon film of the gate needs to have a thickness of at least 4000 nm to function as a mask, and therefore, the bipolar The thickness of the polycrystalline silicon film of the emitter electrode of the transistor is also at least 4000 nm. As a result, there is a drawback that the emitter resistance of the bipolar transistor increases and hre is difficult to increase.

本発明の目的は、バイポーラトランジスタのエミッタ抵
抗の増大とhreの低下とを伴うことにし、バイポーラ
トランジスタとMOSFETとを同一半導体基板上に混
在して形成した高密度・高信頼度の半導体装置を提供す
ることにある。
An object of the present invention is to provide a high-density, high-reliability semiconductor device in which bipolar transistors and MOSFETs are mixedly formed on the same semiconductor substrate, with an increase in emitter resistance and a decrease in hre of bipolar transistors. It's about doing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、バイポーラトランジスタと電界
効果トランジスタとが同一半導体基板上に混在して形成
された半導体装置において、前記バイポーラトランジス
タのエミッタ電極の多結晶シリコン膜の膜厚が前記電界
効果トランジスタのゲートの多結晶シリコンよりも薄く
なっている。
In the semiconductor device of the present invention, in a semiconductor device in which a bipolar transistor and a field effect transistor are formed on the same semiconductor substrate, the thickness of the polycrystalline silicon film of the emitter electrode of the bipolar transistor is the same as that of the field effect transistor. It is thinner than the polycrystalline silicon of the gate.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)、(b)は本発明の第1の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。この実施例の製造方法では、先ず、第1図(
a>に示すように、素子分離用の酸化膜2によって絶縁
分離されたシリコン基板1の表面にそれぞれソース4.
ドレイン5゜ゲート酸化膜6”′及びゲート6によって
構成されるMOSFET及び酸化膜によって覆われたバ
イポーラトランジスタのベース7の不純物拡散の上にリ
ン珪酸ガラス(以降PSGと称す)膜3を3000人形
成する。ここでMOSFETのソース4及びドレイン5
は、4000人の多結晶シリコン膜のゲート6をマスク
としてイオン注入によって形成されている。
FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention. In the manufacturing method of this example, first, the manufacturing method shown in FIG.
As shown in Fig. a>, sources 4.
A phosphosilicate glass (hereinafter referred to as PSG) film 3 is formed by 3000 people on the impurity diffusion of the base 7 of the MOSFET constituted by the drain 5° gate oxide film 6'' and the gate 6 and the bipolar transistor covered with the oxide film. Here, source 4 and drain 5 of MOSFET
is formed by ion implantation using the gate 6 of a 4,000-layer polycrystalline silicon film as a mask.

次に、第1図(b)に示すように、ベース7上の酸化膜
2とPSG膜3とにコンタクト用の窓を開孔し、半導体
チップ全面に多結晶シリコン膜を2500人の膜厚で被
着し、更にイオン注入によって不純物を多結晶シリコン
膜に導入した後ホトリソグラフィ技術によって所定のパ
ターンにエツチングして多結晶シリコン膜のエミッタ電
極9を形成し続いて熱拡散によってエミッタ電極9の下
にエミッタ8の不純物拡散層を形成すると、本発明の第
1の実施例ができる。
Next, as shown in FIG. 1(b), a contact window is opened in the oxide film 2 and PSG film 3 on the base 7, and a polycrystalline silicon film is deposited to a thickness of 2500 nm over the entire surface of the semiconductor chip. After introducing impurities into the polycrystalline silicon film by ion implantation, it is etched into a predetermined pattern using photolithography technology to form the emitter electrode 9 of the polycrystalline silicon film, and then the emitter electrode 9 is formed by thermal diffusion. A first embodiment of the present invention is obtained by forming an impurity diffusion layer of the emitter 8 below.

第2図(a)、(b)は本発明の第2の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。
FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

この実施例は、先ず、第2図(a)に示すように、シリ
コン基板1上のゲート絶縁膜6パを覆うように多結晶シ
リコン6a′を所定のパターンで2000人の膜厚で形
成し、不純物拡散層のベース7上の酸化膜2にコンタク
ト用の窓を開孔して半導体チップ全面に多結晶シリコン
膜6b’を2500人の膜厚で被着し、その上からイオ
ン注入によって不純物を導入し更に熱拡散によってエミ
ッタ8の不純物拡散層を形成する。
In this embodiment, first, as shown in FIG. 2(a), polycrystalline silicon 6a' is formed in a predetermined pattern to a thickness of 2000 nm so as to cover a gate insulating film 6 on a silicon substrate 1. , a contact window is opened in the oxide film 2 on the base 7 of the impurity diffusion layer, a polycrystalline silicon film 6b' is deposited on the entire surface of the semiconductor chip to a thickness of 2500 nm, and impurities are implanted on top of the polycrystalline silicon film 6b' by ion implantation. is introduced, and further an impurity diffusion layer of the emitter 8 is formed by thermal diffusion.

次に、第2図(b)に示すように、ホトリソグラフィ技
術により、多結晶シリコン膜6b′及び6a′を順次エ
ツチングして、膜厚4500人のゲート6′及び膜厚2
500人のエミッタ電極9′を形成することによって、
本発明の第2の実施例ができる。
Next, as shown in FIG. 2(b), the polycrystalline silicon films 6b' and 6a' are sequentially etched by photolithography to form a gate 6' with a thickness of 4500 and a gate 6' with a thickness of 2.
By forming 500 emitter electrodes 9',
A second embodiment of the invention is now available.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、バイポーラトランジスタ
のエミッタ電極の多結晶シリコン膜の膜厚をMOSFE
Tのゲートの多結晶シリコン膜よりも薄く形成すること
により、エミッタ抵抗の増大とhfeの低下とを防止し
て特性が良好で高密度・高信頼度の半導体装置が提供で
きるという効果がある。
As explained above, the present invention improves the thickness of the polycrystalline silicon film of the emitter electrode of a bipolar transistor by
By forming it thinner than the polycrystalline silicon film of the gate of T, there is an effect that an increase in emitter resistance and a decrease in hfe can be prevented, and a semiconductor device with good characteristics, high density, and high reliability can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1及び第2図(a)、(b)はそれぞれ本発明の第1
及び第2の実施例の製造方法を説明するための工程順に
示した半導体チップの断面図である。 1・・・シリコン基板、2・・・酸化膜、3・・・PS
G膜、4・・・ソース、5・・・ドレイン、6.6′・
・・ゲート、6パ・・・ゲート酸化膜、6a’ 、6b
′・・・多結晶シリコン膜、7・・・ベース、8・・・
エミッタ、9,9′・・・エミッタ電極。 (αジ 熟 I 凹 Cす (b)
FIGS. 1 and 2 (a) and (b) are the first embodiment of the present invention, respectively.
FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment. 1... Silicon substrate, 2... Oxide film, 3... PS
G film, 4...source, 5...drain, 6.6'・
...Gate, 6P...Gate oxide film, 6a', 6b
'... Polycrystalline silicon film, 7... Base, 8...
Emitter, 9, 9'...emitter electrode. (αjiriku I concave Csu (b)

Claims (1)

【特許請求の範囲】[Claims]  バイポーラトランジスタと電界効果トランジスタとが
同一半導体基板上に混在して形成された半導体装置にお
いて、前記バイポーラトランジスタのエミッタ電極の多
結晶シリコン膜の膜厚が前記電界効果トランジスタのゲ
ートの多結晶シリコンよりも薄いことを特徴とする半導
体装置。
In a semiconductor device in which a bipolar transistor and a field effect transistor are formed together on the same semiconductor substrate, the polycrystalline silicon film of the emitter electrode of the bipolar transistor is thicker than the polycrystalline silicon film of the gate of the field effect transistor. A semiconductor device characterized by its thinness.
JP61175057A 1986-07-24 1986-07-24 semiconductor equipment Pending JPS6331156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61175057A JPS6331156A (en) 1986-07-24 1986-07-24 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61175057A JPS6331156A (en) 1986-07-24 1986-07-24 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6331156A true JPS6331156A (en) 1988-02-09

Family

ID=15989477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61175057A Pending JPS6331156A (en) 1986-07-24 1986-07-24 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6331156A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0399231A2 (en) * 1989-04-26 1990-11-28 Matsushita Electric Industrial Co., Ltd. A semiconductor device and method of manufacturing the same
US6441441B1 (en) * 1996-06-07 2002-08-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61110457A (en) * 1984-11-05 1986-05-28 Nec Corp semiconductor equipment
JPS6292358A (en) * 1985-10-17 1987-04-27 Nec Corp semiconductor equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61110457A (en) * 1984-11-05 1986-05-28 Nec Corp semiconductor equipment
JPS6292358A (en) * 1985-10-17 1987-04-27 Nec Corp semiconductor equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0399231A2 (en) * 1989-04-26 1990-11-28 Matsushita Electric Industrial Co., Ltd. A semiconductor device and method of manufacturing the same
US6441441B1 (en) * 1996-06-07 2002-08-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same

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