JPS63311549A - Address discriminating circuit - Google Patents

Abstract

PURPOSE:To make an upper-limit address calculating means unnecessary so as to simplify the constitution of the hardware of an address discriminating circuit, by making the address discrimination effective, when no discordant bit is issued from a lower-limit address comparing means and when all discordant bits are masked by a capacity masking means. CONSTITUTION:At a lower-limit address comparing means 40 composed of exclusive 'OR' gates, a system path memory address 10 is compared with the content of a lower-limit address holding means 20 and, when the address 10 does no coincide with the content of the mean 20 in the unit of bit a corresponding discordant bit is made effective. A capacity masking means 60 composed of AND gates, takes the AND of a discordant bit 35 and the inversion of the content of a capacity holding means 30 in the unit of bit. A discriminating circuit 50 makes the address discrimination effective, when the results of the capacity masking means 60 show that all bits are ineffective. Therefore, no upper-limit address calculating means is required and, as a result, the constitution of the hardware of this address discriminating circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device in which a plurality of storage means are connected to a system bus. The present invention relates to an address discrimination circuit for determining an address.

[Conventional technology]

Conventionally, this type of address discrimination circuit has a lower limit address holding means 20 of m bits to which each storage means should respond, n pins,
and the capacity holding means 3o of the kit.

a lower limit address comparing means 40 that compares the address of the system bus with the contents of the lower limit address holding means; an upper limit address calculating means 7o that calculates the sum of the contents of the lower limit address holding means and the contents of the capacity holding means as the upper limit address; It consisted of an upper limit address comparing means 80 for comparing the calculation result and the address of the system bus.

A lower limit address comparing means 401 constituted by a comparator compares the system bus memory address 10 and the contents of the lower limit address holding means 20, and when the system bus memory address ≧ the contents of the lower limit address holding means 20, a lower limit address valid signal is output. 90 is valid.

The upper limit address calculation means 70 constituted by an adder calculates the contents of the lower limit address holding means 20 and the capacity holding means 50.
The upper limit address is generated by adding the contents of . Further, when the addition result multiplies overflow, the upper limit address digit overflow signal 110 is enabled.

The upper limit address comparison means 80, which is constituted by a comparator, compares the result of the upper limit address calculation means 70 with the system bus memory address 10, and when the system bus memory address is the upper limit address, the upper limit address valid signal 100 is determined.
shall be valid.

In the determination circuit 501, address determination is valid when the lower limit address valid signal 90 is valid, the upper limit address valid signal 100 is valid, and the upper limit address overflow signal 110 is invalid.

[Problem that the invention seeks to solve]

The above-mentioned conventional address discrimination circuit includes a 1 m-bit lower limit address comparison means 401, an upper limit address calculation means 70, and an n-bit upper limit address comparison means 80, each of which has an m-bit comparator.

Adder to perform lower limit address + capacity.

An n-bit comparator is required. Therefore, there is a drawback that the square configuration becomes complicated.

[Means for solving problems]

The address discrimination circuit according to the present invention includes m-bit lower limit address holding means for holding the lower limit of the address allocated to each storage means, and n-bit capacity holding means for holding the capacity of the address allocated to each storage means. , a lower limit address comparison means constituted by m exclusive OR gates for comparing the address of the system bus and the contents of the lower limit address holding means; and capacitance masking means constituted by n AND gates for masking the contents of the means, and when there are no mismatching bits in the lower limit address comparison means, all mismatching bits are masked by the capacitance masking means. It is characterized in that address discrimination is enabled when the

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an address discrimination circuit according to an embodiment of the present invention. In the figure, 10 is a system bus memory address, 20 is a lower limit address holding means,
30 is a capacity retention means.

40 is a lower limit address comparing means, and 35 is a mismatch bit which is the comparison result of the lower limit address comparing means 40. Also, 5
0 is a determination circuit, and 60 is a capacitance masking means.

゛ In the lower limit address comparison means 40 constituted by an exclusive OR gate, the system bus memory address 10
and the contents of the lower limit address holding means 20 are compared, and the system bus memory address is compared bit by bit with the contents of the lower limit address holding means 20.

The corresponding mismatch bit is enabled.

The capacitance masking means 60 composed of logical product K takes the logical product of the mismatch bit 65 and the inversion of the capacitance holding means 30 in bit units.

The determination circuit 50 validates the address determination when the result of the capacitance masking means 60 is that all bits are invalid.

FIG. 6 and FIG. 4 show an example of a system bus having a memory address of 20 pits to which a plurality of storage means (maximum capacity 512 KW) which are added by 64 KW per year are connected. The lower limit address holding means 20 has 4 bits, and the capacity holding means 30 has 6 bits.
It becomes a pit.

The lower limit address is 0 to 960 as shown in Figure 3.
Up to Kw (54Kw can be set in annual units.The capacity is 64Kw and 128Kw as shown in Figure 4.

It can be set as 256Kw or 512Kw. However, as a limitation, the lower limit address can only be set to a value that is divisible by the capacity. For example, when the capacity is 128KwQ, the lower limit address is set to 0,128,256°384Kw.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for an upper limit address calculation means and uses a 1 m bit lower limit address comparison means and an n bit upper limit address comparison means to calculate m exclusive logical sums from 1 m bits and n bits comparators. It has the effect that it can be reduced to a gate and n AND gates.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an address discrimination circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional address discrimination circuit. FIG. 3 is a diagram showing the relationship between the lower limit address bit setting and the lower limit address, and FIG. 4 is a diagram showing the relationship between the capacity bit setting and the capacity. 10... System bus memory address, 20... Lower limit address holding means, 30... Capacity holding means. 35... Discrepancy signal), 40... Lower limit address comparing means, 50... Judgment circuit, 60... Capacity masking means. Figure 1

Claims (1)

[Claims] 1. A plurality of storage means each having a fixed expansion capacity unit are connected to the system bus, and in an address discrimination circuit for determining within its own storage means the address to which each storage means should respond, the address assigned to each storage means is m-bit lower limit address holding means for holding the lower limit of the address, n-bit capacity holding means for holding the capacity of the address assigned to each storage means, the address of the system bus, and the contents of the lower limit address holding means. a lower limit address comparison means constituted by m exclusive OR gates for comparing, and n AND gates for masking mismatched bits with the contents of the capacity holding means in the comparison result. and a capacitance masking means, wherein the address discrimination is enabled when there are no mismatching bits in the lower limit address comparison means and when all mismatching bits are masked by the capacitance masking means. Discrimination circuit.