JPS5953588B2 - Memory interleave control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory interleaf control scheme, particularly in a memory device having a plurality of memory constituent units.
A memory interleaf control method that allows users to freely respond to changes in the configuration of a memory device without determining which memory configuration units should be accessed directly from access address information. It is related to.

Conventionally, a plurality of memory constituent units each having a width of, for example, 32 bytes have been prepared, and interleaving has been applied as necessary to improve processing speed.

FIGS. 1A and 1B show explanatory diagrams explaining this state. Reference numerals 1-0 to 1-3 in the figure represent memory structural units (hereinafter referred to as banks), 2 represents a memory chip, and 3 represents access address information. In the case shown in FIG. 1A, 8 bits x 32 bytes = 256 memory chips 2 of IK x 1 bit are arranged to form one memory structural unit, and are designated as banks 1-0 to 1-3.

If the interleaf is applied across the four banks 1-0 to 1-3 shown in the figure (the number of interleaves is "4"), the access address address is "0" at the beginning of bank 1-0, The beginning of bank 1-1 is given address "32," the beginning of bank 1-2 is given address "64," and the beginning of bank 1-3 is given address "96." From this, for example, all addresses existing in bank 1-0 have interleaf bits indicated by the 6th b and 7th a from the lowest of the access address information 3 shown in FIG. 1B. When the two bits indicate "00", it is assumed that bank 1-0 is accessed. Note that when dividing into a set of banks 1-0 and 1-1 and a set of banks 1-2 and 1-3, and interleaving with an interleaf number of "2" between these sets, the first The bank can be determined by looking only at bit b shown in Figure B.

Conventionally, the configuration was such that banks were specified by looking at the interleaf bits as described above, and the number of interleafs was ``2''.
In the case where the design takes into consideration the number of interleaves "2", it is necessary to add at least two banks to meet the above-mentioned interleaf number "2" when adding a new one.

In the case shown in Figure 1, the memory chip 2 is 1K x 1 bit, and even if two banks are added, it will only be added by 64K bytes, so it will not be much of a burden on the user. No.

However, as shown in Figure 2, there has been a recent trend toward the adoption of 64 x 1-bit memory chips 4, and one bank is divided into 2
M bytes are reached, and two banks 5-j, 5- (
If it is mandatory to provide an additional capacity of j+1), this will result in an additional capacity of 4 Mbytes, which will place a large burden on the user in terms of expenses. The present invention aims to address the above-mentioned problems, and eliminates the method of directly specifying an access bank from access address information, and takes into consideration that it can be freely matched to the configuration of an actual memory device. The purpose of this is to make it possible to freely expand even just one bank of 2M bytes. Therefore, the memory interleaf control method of the present invention is applicable to each of the above-mentioned memory interleaf control systems in a data processing system having a memory device that is provided with a plurality of memory structural units and configured such that an interleaf method can be adopted between the memory structural units. Corresponding to the memory configuration unit, there is a mounted/unmounted identification flag that indicates whether the memory configuration unit is implemented or not, and each memory configuration unit is accepted when the interleaf method is not adopted for the memo configuration unit. An address representing at least one of the addresses held by
The memory configuration unit corresponding bit in the access address information issued by the access requesting device and the address number information are configured to be set at least.
an address/number comparison unit that compares the number information with the number information, and determines the number of interleafs given to each memory unit based on the interleaf bits in the access address information and the implementation/uninstallation identification flag. The interleaf number determining unit is provided to determine the memory configuration unit to be accessed by supplying the determination result by the interleaf number determining unit and the interleaf bits to the memory activation circuit. It is a feature. This will be explained below with reference to the drawings. Figure 3 and Figure 4 A, B
is an explanatory diagram for explaining the present invention, and FIG. 5 shows an embodiment of the present invention.

In FIG. 3, the symbol MEM is a memory device, 51, 5-
(1+1) and 5-J5-(j+1) each represent a 2 Mbyte bank. In the case of the present invention, in order to indicate how much capacity each bank has, for example, the address that would be assigned if no interleaving was applied is assumed, and the address is The starting address of each bank when the grant is made is “0”, “2M”, “
4M" and "6M" are set as address numbers AN in advance in each bank. In the case shown, for example, AN,=0, AN1+1=2, AN3-4, AN1+
Given as 1=6. Furthermore, a mounted/unmounted identification flag M is provided to indicate whether each bank is currently mounted or not mounted. Each flag VMl,V
Ml+1, VM3, VM, +1 are given logic "1" if each is implemented, and logic "0" if not implemented.
is given. Furthermore, a valid indication flag i+1, . . . +1 indicating whether the address number AN is valid or invalid is provided as necessary. In the case of the present invention, for example, if banks 5-1, 5(1+1), and 5-j are installed, the number of ways (interleaf number) by banks 5-1 and 5-(1+1) is "2". The interleaf with the number of ways "1" and the interleaf with the number of ways "1" only by the bank 5-j can coexist in the system.

Also, banks 5-1, 5-(1+1), 5-j and 5(j+
1) is implemented, banks 5-1 and 5-(1+1
) and the interleaf with way number “2” and bank 5.
−j and an interleaf with a way number of “2” by 5−(j+1) are made to coexist. FIG. 4A shows access addresses when banks 5-j and 5-(j+1) are interleaved with a way number of "2".

In this case, as shown in the figure, banks 5-j and 5-(j+1)
Addresses on bank 5j are the only addresses where bit b shown in FIG. 1B is logic 0, and addresses on bank 5-(j+1) Only those for which b is logical "1" exist. For this purpose, the mounted/unmounted flags VM and VMlJ+1 shown in FIG. 3 are checked, and if both are mounted, an interleaf of way number "2" is applied as shown in FIG. The access bank is determined based on the access bank. Note that the numbers “0”, “31”, and “32” shown in Figure 4
, "63", "64", etc. represent addresses that point in units of bytes when one word is composed of 32 bytes. Therefore, bit b shown in FIG. 1B above corresponds to the least significant bit of address 5 indicating a word. In this case, the bank corresponding bit in the access address information (described later in Figure 5)
Therefore, if bank 1 5-j appears to be designated and the bit b is logic "0", bank 5j is determined as the access bank, and bank Ii appears to be designated 5j. If bit b is logic "1", bank 5-(j+1) is determined as the access address, and it appears that bank 5-(j+1) is specified and bit b is logic "1". 0'', bank 5-j is determined as the access bank, and I
If it appears that v bank 5-(j+1) is specified and the above bit b is logic "1", bank 5-(j+1) is specified.
j+1) is determined as the access bank.

Note that the bank corresponding bits correspond to bits #22 and #23 when the rightmost bit in the access address information 3 shown in FIG. 5 is set to bit #0. Therefore, it can be considered that the logic 1111111v above corresponds to the following determination. That is, a) When bit #22, #23 = 0, 0 and b = 0, b) Bit #
22, #23 0, 0 (-'c when b = 1) d) when bits #22, #23 = 0, 1 and b = 0
When bits #22 and #23 = 0 and 1 and b = 1, they are accessed.

FIG. 4B shows access addresses when only bank 5-j is interleaved with a way number of "1".

In this case, in order to correspond to the case shown in FIG. An address where the bit b has logic "1" is assigned to the half.

In the case of Figure 4B, the mounted/unmounted flag M1 shown in Figure 3
and VM,+1 are checked, and the flag VM, is logic "1" and V
If MJ+1 is logic "0", it is automatically regarded as a bank with the number of ways "1". Then, from the bank corresponding bit in the access address information, bank 5-
If bank 5-j is seen, bank 5-j is automatically determined as the access bank. However, in the case shown in FIG. 4B, the b bit (FIG. 1B) is added to the beginning of the address in the bank as shown in FIG. 5 to separate the lower half and the upper half in the diagram. FIG. 5 shows an embodiment of the present invention, in which reference numeral 3 denotes an access address information 6 address number comparison section corresponding to FIG. 9 is a memory activation circuit, 9 is an address conversion circuit, 10 is address information within a bank, AN' is a bank corresponding bit part in access address information, and b is an interleaf bit.

In the illustrated case, when the access address information 3 is given, the bank corresponding bit part AN' in the information 3 is supplied to the address number comparison section 6.

The address numbers ANi, ANi+1, AN, and ANJ+1 shown in FIG. It is determined which bank corresponds to the access when it is assumed that no interleaving is applied from the viewpoint of the corresponding bit AN. That is,
Banta is tentatively determined by either of the following.

The result is then notified to the way number determining section 7. The way number determining unit 7 is given in advance the mounted/unmounted flags Ml, VMl+1, VM,, VM, +1 of each bank, and if the way number determining unit 7 is currently set to bank 5-j or 5- by the bit part AN', (j+1) is tentatively determined, then the flag VM
, and VMj+1, and in the case of , banks 5-j and 5
−(j+1) are both implemented, and the number of ways is “2”.
It is determined that the interleaf part is applied. In this case, it is determined that the number of ways is "1". Note that if both VM and VMJ+1 are at logic "O", this access request is invalid. When the number of ways is "2", the memory activation circuit 8 receives the tentatively determined bank information and way number information, and also receives the illustrated interleaf bit b, as described with reference to FIG. 4 above. Based on the logic determined, the access bank is determined and the bank is accessed.

In this case, the illustrated address converter 9 generates and outputs a logic "O" or "1" depending on whether the upper half or the lower half is illustrated in FIG. 4A. Then, access is performed using the determined internal address information 10. Further, when the way number determining section 7 determines that the number of ways is "1", the memory activation circuit 8 directly accesses the bank of VM or VMJ+1 which has logic "1".
Access it by viewing it as Banta.

Then, the address converter 9 passes the illustrated bit b as it is, sets it at the top of the intra-bank address information 10, and access is performed. The above describes the case of 2-way/1-way, but for example, in the case of 4-bank 4-way interleaf, it is possible to add 1 bank or 2 banks, and these can be easily dealt with by analogy. .

That is, in this case, the bank corresponding bits AN' shown in FIG. 5 are 3 bits, and the interleaf bits b shown in FIG.
This is the form in which bits are used. When adding one bank, the number of interleafs, for example, 4-way or 1-way, is determined from the bank corresponding bits and interleaf bits, the bank is determined accordingly, and the upper 2 bits of the address within the bank are created. . In 1-way mode, the interleaf bits (2 bits) become the upper 2 bits of the address within the bank.

Also, when two banks are added, a mode analogous to this will be applied. As described above, according to the present invention, it is possible to freely deal with changes in the configuration of a memory device, and expansion can be done as desired in accordance with the user's wishes.

[Brief explanation of drawings]

FIGS. 1 and 2 are explanatory diagrams for explaining the prerequisite problems of the present invention, FIGS. 3 and 4 are explanatory diagrams for explaining the present invention, and FIG. 5 shows an embodiment of the present invention.

Claims (1)

[Claims] 1. In a data processing system that has a memory device that is equipped with a plurality of memory configuration units and is configured such that an interleaving method can be adopted between the memory configuration units, the memory configuration unit is implemented in accordance with each of the above memory configuration units. At least an installed/uninstalled identification flag indicating whether the memory configuration unit is unimplemented and address/number information representing at least one of the addresses handled by each memory configuration unit in a state where the interleaving method is not adopted for the memory configuration unit. an address number comparison unit configured to set the memory configuration unit corresponding bits in the access address information issued by the access requesting device and the address number information; and the access address information. An interleaving number determining unit is provided to determine the number of interleavings given to each memory unit based on the interleaving bits in the memory unit and the implementation/non-implementation identification flag, and the interleaving number determining unit determines the number of interleavings given to each memory unit based on the interleaving bit in the memory unit and the implementation/unimplemented identification flag. A memory interleaving control method characterized in that a memory constituent unit to be accessed is determined by supplying the determination result and the interleave bit.