JPS63303424A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To perform an arithmetic operation at the timing of two clocks against original oscillation, by making an access to two storage devices at the same timing and sending data to a computing element. CONSTITUTION:When address signals A and B are outputted against two operands from a ROM 1, the address signals A and B are simultaneously latched respectively by latches 25 and 26 at the timing of a clock CK1. After they are latched by the latches 25 and 26, the address signals A and B are simultaneously latched respectively by RAMs 41 and 42. When the address signals A and B are inputted to the RAMs 41 and 42, calculation data A and B are outputted to the computing element 5 through latches 27 and 28 from the RAMs 41 and 42 at the timing of a clock CK2 and arithmetic operation is executed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an arithmetic circuit.

[Conventional technology]

In general, an arithmetic circuit is an important circuit that is the core of the arithmetic processing mechanism of a central processing unit or a microcomputer, and is particularly required to be high-speed.

Next, an example of a conventional arithmetic circuit is shown in FIG.

In FIG. 3, 1 is a ROM, 21, 22, 23 and 24 are latches, 3 is a switching circuit, 4 is a RAM, and 5 is an arithmetic unit.

FIG. 4 is a timing chart of control signals and data in each component.

First, address signals A and B for two operands output from the ROM 1 are latched into the latch 21 and the latch 22 at the timing of the clock CK1. The latched address signals A and B are controlled by the switching circuit 3, and one of them (here, address signal A) is sequentially input to the RAM 4.

Calculated data A is output based on the input address signal A. The output arithmetic data A is latched by the latch 23 at the timing of the clock CK2, and then also input to the arithmetic unit 5. The input calculation data A waits for the calculation data B to be input next.

When the calculation data A is input to the calculation unit 5, an address signal is input to the address of the RAM 4. The RAM 4 outputs operation data B in response to the input address signal B. The output calculation data B is input to the calculation unit 5 after being latched by the latch 24 at the timing of the clock CK3.

The input calculation data B is operated on the previously input calculation data A to obtain a calculation result. The obtained calculation results are input to the RAM 4 as well as to the outside.

[Problem that the invention seeks to solve]

In the conventional arithmetic circuit described above, there was only one transfer path for the arithmetic data, so it was necessary to input the next arithmetic data after inputting one arithmetic data to the arithmetic unit. . Therefore, there was a drawback that it took three clocks for the original oscillation to obtain the calculation result. In addition, a switching circuit is required, and the control signal is also complicated, such as having to create a clock by dividing the original oscillation by three.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an arithmetic circuit that improves arithmetic speed and simplifies control signals.

[Means for solving problems]

The arithmetic circuit of the present invention has two similar storage devices and an arithmetic unit that operates on data read out from the storage devices at the same timing, and each storage device is accessed at the same timing to process data. It is characterized in that it is sent to a computing unit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 1 is ROM25.2
6.27 and 28 are latches, 41 and 42 are RAM
, 5 is an arithmetic unit, and FIG. 2 is a timing chart of control signals and data for each component.

In FIG. 1, a data transfer path consisting of latches 25, 27 and RAM 41, latches 26, 28 and
Since a data path consisting of M42 is provided, address signals and data can be handled simultaneously.

Next, the operation will be explained. Now, it is assumed that the ROM1 outputs an address signal A and an address signal for two operands.

The address signal A is latched into the latch 25 and the address signal B is latched into the latch 26 simultaneously at the timing of the tarock CKI. After these address signals are latched,
They are also simultaneously input to RAM4 and RAM42, respectively.

When address signal A is input to the RAM 41, calculation data A is output based on the address signal. Similarly RAM
When address signal B is input to 42, calculation data B is output according to the address.

The output calculation data A and calculation data B are clock CK.
They are simultaneously latched by the latch 27 and the latch 28 at timing 2. After being latched, the two calculation data are simultaneously input to the calculation unit 5. Arithmetic operations are performed by the arithmetic unit 5, and the obtained results are supplied to the outside or R
It is also input to AM42 and stored.

〔Effect of the invention〕

As is clear from the above explanation, according to the arithmetic circuit of the present invention, two memory devices can handle two arithmetic data simultaneously, so that it takes two clocks for the original oscillation to obtain the arithmetic result. This means that the processing speed is increased by one clock compared to the conventional arithmetic circuit. Since only two types of control signals are required, there is no need to divide the original oscillation by three, simplifying the circuit. Furthermore, the fact that calculation data can be handled simultaneously eliminates the need for a switching circuit, leading to a reduction in chip size.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows a timing chart of this embodiment, FIG. 3 shows a conventional example, and FIG. 4 shows a timing chart of this conventional example.

Claims (1)

[Claims] It has two similar storage devices and an arithmetic unit that operates on data read out from the storage devices at the same timing, and each of the storage devices is accessed at the same timing and sends the data to the arithmetic unit. An arithmetic circuit characterized by: