JPS6260755B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory addressing circuit.

In digital processing, data stored in memory is often retrieved and processed every few pieces in succession. For example, fast Fourier transform is a typical example of digital signal processing. in this case,
In the next processing step, it is necessary to read out the contents of every several memory addresses one after another and perform calculations on the data string written to the memory in the preceding processing step. Memory addressing means generally consists of a simple register or a counter as shown in FIG. In Figure 1, 1 is a memory, 2 is an addressing counter for memory 1,
3 is a control circuit that controls the counter. The counter is generally a +1 up counter or a -1 up counter.
A down counter is used.

If a simple register is used as the addressing means, it is possible to access the memory in any order, but it is necessary to transfer the address value to the register each time the memory is accessed. In digital processing, consecutive addresses in memory are often accessed one after another, and a method devised to save the time of transferring address values each time the address is specified using a counter as shown in Figure 1. This is a method used as a means. Instead of transferring the address value, it is only necessary to increment (or decrement) a counter, which shortens the memory access cycle compared to using a simple register as the addressing means, and helps speed up processing. be. However, when accessing the contents of every few (n) addresses in the memory one after another, as required in fast Fourier transform, the configuration shown in FIG. 1 is inappropriate. This is because the count width is fixed to 1 or -1, and every nth value necessary for the counter 2 must be transferred every time the memory is accessed. If the execution time of a memory access instruction is equal to the execution time of an instruction to transfer data to an address register, the memory access cycle will be twice as long as when accessing consecutive addresses. The above-mentioned problems are major obstacles to digital processing, which handles large amounts of data and requires high-speed processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory address control circuit that eliminates the above-mentioned problems.

According to the present invention, an address register, an adder that takes the address register as an augend and selects a plurality of fixed values and outputs them as addition values to the address register, and selection and addition of the addition values of the adder. An address control circuit is obtained, which includes an arithmetic operation and a control circuit that controls the operation.

Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of essential parts showing one embodiment of the present invention. In Figure 2, 1' is memory,
4 is an address register, 3' is a control circuit, 5, 6
7 is a fixed value specifying means, 7 is an adder, and a control circuit 3' controls the selection of inputs 5 and 6 of the adder and the addition operation. As an example, assume that the addition values specified by 5 and 6 are 1 and n (n is an integer), respectively. If a fixed value of 5 is selected and added by the control circuit 3', the contents of consecutive addresses in the memory 1' can be accessed one after another. Also, the control circuit 3'
Therefore, by selecting a fixed value of 6 and adding it, the contents of n addresses in the memory 1' can be successively accessed. As described above, according to this embodiment, the contents of consecutive addresses in the memory can be accessed one after another, and the contents of n addresses can also be accessed one after another. Furthermore, the contents of consecutive addresses and the contents of n addresses can be accessed in any combination, which has a large effect on the increase in hardware. In this embodiment, two selectable fixed addition values are provided, but it is clear that this can be expanded to three or more.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part of a conventional address control circuit, and FIG. 2 is a block diagram of the main part showing an embodiment of the present invention. 1, 1'...Memory, 2...Address specification counter, 3, 3'...Control circuit, 4...Address register, 5, 6...Fixed value specification means, 7...Adder.

Claims (1)

[Claims] 1. A single adder, a first fixed value specifying means to which a fixed value n is set, a second fixed value specifying means to which a fixed value m is set, and one input terminal of the adder. means for inputting one of said fixed values n and m to said adder; and a single means connected to the output of said adder for supplying the addition result as an address to the memory and feeding back to the other input of said adder. and an address register, and each time an addition is executed, the first
and the second fixed value specifying means,
An address control circuit that sequentially creates addresses incremented by a fixed value n or m.