JPS63298515A - Controller for semiconductor memory cartridge - Google Patents

Abstract

PURPOSE:To prevent the generation of a noise voltage at the time of removing a semiconductor memory cartridge by turning on an input and output signal line only at the time of the access of the semiconductor memory of the semiconductor memory cartridge. CONSTITUTION:An input and output buffer 7 is defined to be a three state buffer circuit and a means for deciding whether the semiconductor memory cartridge 2 has a period for writing data or reading is provided. Then, during a period except this executing period, the gate of the three state buffer circuit is turned off to bring connector parts 9a, 9b parts into a high impedance state to electrically interrupt the input and output signal line of a controller 1 and the semiconductor memory cartridge 2 mounted thereon. Namely, at the time of removing the semiconductor memory cartridge 2, the connector parts 9a, 9b are effectively brought into the high impedance state, so that at the time of removing, the noise voltage is not generated to prevent the damage of the circuit or the damage of the data in the semiconductor memory cartridge 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for a semiconductor memory cartridge used as an auxiliary storage device of a computer, and particularly relates to a control device for controlling a semiconductor memory cartridge used as an auxiliary storage device of a computer, and in particular, to a control device for controlling a semiconductor memory cartridge used as an auxiliary storage device of a computer. The present invention relates to a control device for a semiconductor memory cartridge that has an improved means for preventing this.

[Conventional technology]

A semiconductor memory cartridge consisting of one or more semiconductor memories such as RAM or ROM housed in a case is used as an auxiliary storage device for computers (including personal computers, word processors, device-embedded control computers, etc.) has been done. When a RAM is used as the semiconductor memory, a memory backup battery is also housed. This semiconductor memory cartridge has a connector, etc. that allows data to be written there.
It is removable from the control device for reading,
The written data can be saved when removed from the control device.

By the way, in a conventional control device, after writing or reading data in a semiconductor memory cartridge, the control line between the MPU (microprocessor) of the control device and the semiconductor memory of the semiconductor memory cartridge is connected to the MPU (microprocessor).
A voltage of the same level as when a control signal for a data read command is sent from U is applied to prevent erroneous writing in the semiconductor memory cartridge. At this time, since no address signal is supplied from the MPU of the control device to the semiconductor memory of the semiconductor memory cartridge via the address bus, no data is read from the semiconductor memory cartridge. The control signal for this data read command has a level of H'' or It L IT.
Therefore, current flows through the control line. In addition, voltage is applied to the signal line of each bit in the data bus and address bus between the MPU of the control device and the semiconductor memory of the semiconductor memory cartridge, even when data is not read or written in the semiconductor memory cartridge. This applied voltage represents +tH" or "L", but of course it does not represent the address in the semiconductor memory of the semiconductor memory cartridge in the address bus. Therefore, the control signal for the data read command is sent to the control line. Even if the same level of voltage is applied as when the data bus and address bus are supplied, data will not be read from the semiconductor memory cartridge.However, if voltage is applied to each bit signal line of the data bus and address bus, Then, when this applied voltage represents IT HIT, current flows from the control device side to the semiconductor memory cartridge side through the data bus and address bus, and when the applied voltage represents Ff L H, a current flows from the semiconductor memory cartridge side. Current flows from the side to the control device side through the data bus and address bus.

In this way, even when data is not being written or read in the semiconductor memory cartridge, the data bus, address bus, control system, etc. Current flows through the Il wire (hereinafter collectively referred to as the signal line), but if the semiconductor memory cartridge is removed from the control device in this state, a noise voltage will be generated in the connector that connects the control device and the semiconductor memory cartridge. Occur. This also applies when the semiconductor memory cartridge is installed in the control device, and since voltage is applied to each signal line on the control device side, a noise voltage is generated in the connector section.

Therefore, due to this noise voltage, a signal with the same level as the control signal of the data write command is generated on the control line, and
An address signal representing a certain address within the semiconductor memory of the semiconductor memory cartridge may be generated on the address bus.

In such a state, writing will be performed at this address in the semiconductor memory, and the data written there will be destroyed.

In addition, in semiconductor memory cartridges and control devices, when the level is fl HIT, it is usually 5V, and when it is "L", it is around Ov, but the noise voltage generated at the connector may be much higher than 5V. In some cases, it is sufficiently lower than OV. When such a noise voltage occurs,
The human output buffer of the semiconductor memory cartridge used in the range of OV to 5 V and the human output buffer of the control device will be destroyed.

On the other hand, there is a conventional example in which a three-state buffer circuit is used as a human output buffer for a control device, and the connector section is brought into a high impedance state by turning off the gate of the three-state buffer circuit. This gate is in the off state when the semiconductor memory cartridge is removed from the control device, and immediately after the semiconductor memory cartridge connector is inserted into the control device connector and the semiconductor memory cartridge is completely installed. When the semiconductor memory cartridge is removed from the control device, it is turned off immediately before the electrical connection between the semiconductor memory cartridge and the control device is disconnected. Thereby, it is possible to prevent the generation of noise voltage when the semiconductor memory cartridge is attached or detached.

[Problem that the invention seeks to solve]

By the way, when attempting to prevent the generation of noise voltage when a semiconductor memory cartridge is attached or detached using a three-state buffer circuit as described above, the position of the semiconductor memory cartridge with respect to the control device when the semiconductor memory cartridge is attached or detached is detected. A means is required. In the conventional example described above, a mechanical, optical or electrical position detection mechanism is provided for this purpose, and a circuit for controlling on/off the gate of the three-state buffer circuit is also provided. Therefore, the scale of the entire system increases, and since the position detection of the semiconductor memory cartridge is very delicate, the configuration and arrangement of the position N detection mechanism require high precision, which increases the manufacturing cost. This will increase product costs. Of course, it is conceivable to manually turn on and off the gate of the three-state buffer circuit, but this increases the number of operations performed by the user, which is undesirable and may lead to erroneous operations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control device for a semiconductor memory cartridge that solves these problems, has a simplified configuration, and can prevent the generation of noise voltage when attaching and detaching a semiconductor memory cartridge. .

Means for Solving Problem c] In order to achieve the above object, the present invention uses a three-state buffer circuit as a human output buffer, and also provides a three-state buffer circuit for a semiconductor memory cartridge to write and read data. The gate of the 3-state buffer circuit is turned off during periods other than this execution period, and the connector section is placed in a high impedance state, and input/output signals between the control device and the semiconductor memory cartridge installed therein are provided. Make sure the wire is electrically isolated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a control device for a semiconductor memory cartridge according to the present invention, in which 1 indicates a control device;
2 is a semiconductor memory cartridge, 3 is an MPU, 4 is an address decoding circuit, 5 is a RAM, 6 is a ROM, 7 is a human output buffer, 8 is a semiconductor memory, 9a and 9b are connectors, 10.10 is a data bus, 11. 11' is an address bus, 12 and 12' are control lines, and 13 is a backup battery.

In the figure, when the semiconductor cartridge 2 is installed in the control device 1, the connectors 9a and 9b are connected, and the control device 1
bidirectional data bus 10, address bus 11, control v
A12 is each connector 9a.

It is electrically connected to the bidirectional data bus 10', address bus 11', and control line 12' of the semiconductor memory cartridge 2 via the line 9b. Data bus 10, address bus 1
1. The control lines 12 connect the MPU 3 and the connector 9a, and a human output buffer 7 consisting of a 3-state buffer circuit is provided between these lines.

When writing data to the semiconductor memory 8 of the semiconductor memory cartridge 2, the MPU 3 writes a write command control signal to the control line 12 and an address signal specifying the address in the semiconductor memory 8 to which data should be written to the address bus 11. The output data are respectively output to the data bus 10. These are the human output buffer 7, the connector 9a,
It is sent to the semiconductor memory 8 via 9b. The semiconductor memory 8 is put into a write mode by the control signal, and data is written to the address specified by the address signal. When reading data from the semiconductor memory 8, the MP
U3 outputs a read command control signal to the control line 12 and an address signal specifying the address from which data is to be read in the semiconductor memory 8 to the address bus 11, respectively. As a result, the data read from the specified address in the semiconductor memory 8 is output to the data bus 10', and is sent to the MPU 3 via the connectors 9b, 9a and the human output buffer 7.
be taken in.

Note that the semiconductor memory 8 is backed up by a backup battery 13, and the data written in the semiconductor memory 8 is retained even after the semiconductor memory cartridge 2 is removed from the control device 1.

A program is stored in the ROM 6, and the MPU 3 reads this program from the ROM 6 and executes this program. The RAM 5 stores data used when the MPU 3 executes this program. ROM
When reading a program from 6 or writing or reading data from RAM 5, the MPU 3 sends control signals for write and read commands to the control line 12 and sends address signals to the address bus 11, as in the case of the semiconductor memory 8. When writing data to RAM 5, the data is output to data bus 10, and when reading from RAM 5 or ROM, data and programs are output to data bus 1.
Take in via 0.

In this way, the MPU 3 can access the RAM 5, ROM 6, and semiconductor memory 8, and the data bus 10. Since the address bus 11 and the control line 12 can be used in common, addresses in different ranges of the address space accessible by the MPU 3 can be stored in the RAM 5.
The ROM 6 and the semiconductor memory 8 are made to occupy the space.

Therefore, by the address signal output from MPU3, the MP
U3 is RAM5. It can be determined whether the ROM 6 or the semiconductor memory 8 is to be accessed. The address decode circuit 4 is for making this determination.

Therefore, if the MPU 3 outputs an address signal specifying the address of the RAM 5 to the address bus 11, the address decode circuit 4 takes in this address signal and makes the RAM selection signal S active. This R.A.
The M selection signal S+ is supplied to the select input C8 of the RAM 5 to enable writing or reading from the RAM 5. At this time, the semiconductor memory cartridge selection signal S, which is supplied to the gate input of the S-type output buffer 7, is not active. ROM6
The same goes for RO from the MPU 3 to the control line 12.
When the address signal specifying the address of M6 is output, the ROM selection signal S2 supplied from the address decoding circuit 4 to the select input τ of the ROM 6 becomes active, making it possible to successively output programs from the ROM 6.

At this time, the RAM selection signal S1 and the semiconductor memory cartridge selection signal S are not active.

When the MPU 3 does not select the semiconductor memory cartridge 8 and the semiconductor memory cartridge selection signal S is not active (tt Htr level), the input/output buffer 7
Data bus 10 and address bus 11 on the collector 9a side of
, the control line 12 becomes in a high impedance state. That is, the human output buffer 7 connects the data bus 10, address bus 11, and control line 12 to the MPU a side and the connector 9.
It is electrically separated into the a side. Further, when the MPU 3 selects the semiconductor memory cartridge 8 and outputs an address signal specifying a certain address of the semiconductor memory 8 to the address bus 11, and the semiconductor memory cartridge selection signal S3 becomes active (#f L IT level), the The gate input of the output buffer 7 becomes active, enabling the human output buffer, and the data bus 10, address bus 11, and control line 12 on both sides of the input/output buffer 7 are electrically connected. This makes it possible to write and read data in the semiconductor memory cartridge 2. .

Therefore, when the semiconductor memory cartridge 2 is not in the data writing or reading state, the crowd cover 7,
Since each signal line between the semiconductor memories 8 is in a high impedance state and no current flows, even if the semiconductor memory cartridge 2 is removed from the control device 1 using the connectors 9a and 9b,
Connector 9a.

No noise voltage is generated at 9b. therefore,
Data destruction in the semiconductor memory 8 and circuit destruction in the control device 1 and the semiconductor memory cartridge 2 will not occur. This also applies to the case where the semiconductor cartridge 2 and the control device 1 are attached. Therefore, there is no need to provide a position detecting means for the control device 1 when the semiconductor cartridge memory 2 is attached or detached. This embodiment requires an address decoding circuit 4 for determining whether the semiconductor memory cartridge 2 is in a data writing/reading state. , compared to the case where an off-control circuit is added, the scale is smaller, and there are no manufacturing problems like in the conventional example. No manual operation required.

〔Effect of the invention〕

As explained above, according to the present invention, the connector section is reliably in a high impedance state when the semiconductor memory cartridge is attached or detached, so there is no noise voltage generated during the attachment or detachment, and there is no risk of circuit damage or damage to the semiconductor memory. Reliability is greatly improved because data is not destroyed in the cartridge, and additional mechanisms such as those for detecting the position of the semiconductor memory cartridge can be eliminated, reducing the scale of the entire system. There are no manufacturing problems such as configuration and placement accuracy that would otherwise occur, and the problems of the prior art can be solved, making it possible to provide a semiconductor memory cartridge control device with excellent functionality at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a control device for a semiconductor memory cartridge according to the present invention. 1... Control device, 2... Semiconductor memory cartridge, 3... MPU, 4...
Address decoding circuit, 7...Person output buffer, 9a, 9b...Connector, 10.10'...
...data bus, 11.11'...address bus, 12.12'...lJ' as wholesale line.

Claims (3)

[Claims] (1) The semiconductor memory cartridge is removable,
In a control device that writes and reads data in the mounted semiconductor memory cartridge, a first means for determining whether or not to access the semiconductor memory of the semiconductor memory cartridge, and a determination result of the first means are provided. A second means for turning on and off an input/output signal line to the semiconductor memory cartridge is provided, and the input/output signal line is turned on only when the semiconductor memory of the semiconductor memory cartridge is accessed. A semiconductor memory cartridge control device characterized by: (2) A control device for a semiconductor memory cartridge according to claim (1), wherein the first means is an address decoding circuit. (3) In claim (1) or (2), the second means is a three-state input/output buffer, and is in a high impedance state except when accessing the semiconductor memory of the semiconductor memory cartridge. A control device for a semiconductor memory cartridge, characterized in that: