JPH0516615B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic program computer with a memory pack equipped with a plurality of memory pack attachment/detachment mechanisms.

[Prior art and its problems] Conventionally, a plurality of memory packs, for example, RAM cards (RAM packs), are provided with an attachment/detachment mechanism that can be attached or detached at will, and a plurality of
Program data,
There are electronic program calculators with memory packs that can continuously write variable data, etc.

In conventional computers of this kind, when setting program data, the entire memory area of multiple installed RAM cards is treated as one address space, and consecutive physical addresses are assigned. Once the program, variable data, etc. have been set, that is, written, the RAM card can only be used in the combination set at the time of the above settings. For example, mutually
Two 4KB RAM cards A1 and A2 are used as a set, a program is written to one RAM card A1, data is written to the other RAM card A2, and then the above RAM card A1 is replaced.
Insert the 2KB configuration RAM card B1 into the above RAM card A2.
If used in combination with , the storage area of the variable data area of RAM card A2 is stored as an absolute address when setting RAM card A1, so
Address correspondence with RAM card B1 is impaired, so when RAM card B1 is used in combination with RAM card A2, completely different variable data will be output one after another.
It is impossible to expect normal processing operation.

In this way, conventionally, for example, each pair of
One of the two 4KB RAM cards can be replaced with a smaller capacity RAM card (e.g. 2KB,
1KB, etc.), we were unable to meet the request.

[Objective of the Invention] The present invention has been made in view of the above points, and provides a range of usable memory pack combinations by making it possible to arbitrarily rearrange memory packs with different memory capacities without requiring any operational burden on the operator. We have developed an electronic program calculator with a memory pack that can greatly expand the memory pack and also allow you to select a memory pack with any storage capacity depending on the storage area to be used, which eliminates wasted memory capacity and allows for an economical way to use the memory pack. The purpose is to provide.

[Summary of the Invention] The present invention, in an electronic program computer equipped with a plurality of memory pack attachment/detachment mechanisms, recognizes the address space of the memory pack attached to the memory pack attachment/detachment mechanism at power-on, and uses the recognized address space. The system compares the address space with the address space when the memory pack was installed and used last time, and changes the absolute address based on the difference in the address space.This allows arbitrary memory packs with different memory capacities to be changed. This memory pack can be recombined, greatly expanding the range of usable memory pack combinations, and allows you to select a memory pack with any storage capacity depending on the storage area to be used, eliminating wasted memory capacity and making it an economical memory pack. It becomes possible to use

[Example] An example of the present invention will be described below with reference to the drawings. Here, we will take as an example a program computer with a memory pack structure in which two RAM cards can be installed at the same time. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 10 controls the entire computer.
CPU, under microprogram control,
Attached to the RAM pack attachment/detachment mechanism described later
It executes processing according to the RAM card setting program, and here, it has a specific firmware mechanism that performs a RAM card check and associated rewriting, which will be described later, at power-on (initialization control).

Reference numeral 11 is an address bus used for address transfer to a RAM card, which will be described later, and 12 is a data bus used for transfer of read/write data.

13 is a latch circuit with a data selection output function
(A), and the data on the data lines 21 and ₂₂ (DA/
DB) and selectively outputs data (DA) or data (DB) in accordance with the control signal (a) from the CPU 10 as well. Here, the control signal (a) is “1”
When , the data (DA) input through the data line 21 is selectively output, and when it is "0",
The data (DB) input via the data line 22 is selectively output.

A latch circuit (B) 14 latches data on the data line 22 in response to a control signal (ck ₂ ) from the CPU 10.

Reference numeral 15 denotes an arithmetic circuit that receives data from the latch circuits (A) 13 and (B) 14 as data to be operated on, and executes an arithmetic operation in accordance with a control signal (s) from the CPU 10. Here, when the control signal (s) is "1", it is the subtraction mode, and when it is "0", it is the addition mode.

A data buffer 16 stores the output data of the arithmetic circuit 15, and outputs data by receiving a control signal (b) of "1" level from the CPU 10. A bidirectional data buffer 17 stores data on the data bus 12 or data line 22, and the output direction of the data is switched and controlled by a control signal (c) from the CPU 10. Here, data is output onto the data bus 12 when the control signal (c) is "1", and data is output onto the data line 22 when the control signal (c) is "0".

18 is a RAM that forms the attachment/detachment mechanism of the memory pack.
This is a connector section for attaching and detaching cards.Here, two sets of card connection connectors CA and CB are provided to connect two RAM cards, and each connector
Both CA and CB have connection terminals TD and TA for data and address, and a connection terminal TC for supplying chip enable signals (CE) and read/write signals (R/W).

19 and 20 are RAM cards connected to the connectors CA and CB of the connector section 18, respectively. ) RAM cards can be used in common.

FIGS. 2 and 3 are for explaining the operation of the above embodiment, respectively. FIG.
Memory map when RAM cards 19A and 20A are installed. Figure b shows 2KB of memory in connector CA.
RAM card 19B is installed and connected to connector CB.
Each memory map is shown when a 4KB RAM card 20A is installed, and here one of the two RAM cards 19 and 20 installed in each connector CA and CB of the connector section 18 (for example, 19) is used as a program card, and the other card (for example, 20) is used as a variable data card. Figure 3 shows when the power is turned on.
3 is a diagram showing an operational flow of memory check processing executed under the control of the CPU 10. FIG.

The operation of one embodiment will now be described with reference to FIGS. 1 to 3. Here, among the program card and data card set using two RAM cards 19A and 20A each having a 4KB configuration, the program card, that is, the RAM card 19A.
Let us take as an example the case of changing to a 2KB RAM card 19B. Figures 2a and b show specific examples. Figure 2a shows two RAMs each having a 4KB configuration.
This shows the address allocation and storage status of the program card and data card, which are configured by 19A and 20A, on the card. Abs-Add is the absolute address assigned consecutively to each card,
The shaded area of the RAM card 19A (program card) is an area where a program has been written, and the shaded area of the RAM card 20A (data card) is an area where data has been written. Also, in the data management area
END・Adr is the last address of all memory areas (here, address 7999), AB is the variable name, “5500”
is its corresponding absolute address (i.e. variable name AB=
“1234”) is shown. An example of the rewriting operation when the RAM card 19A serving as a program card out of such a set of program cards and data cards is replaced with a 2KB RAM card 19B as shown in FIG. 2b will be described below. do.

First, when the power is turned on, the connector section 18 is connected under the fixed microprogram control of the CPU 10.
The capacity of the RAM card installed is checked. In other words, here are the available RAM cards.
Since there are three types: 4KB, 2KB, and 1KB,
It checks the memory capacity by reading/writing data each time while adding addresses in 1KB increments. This capacity check can be done in various ways, but in this case, address 0→address 999→address 1000→
Assume that the capacity check is performed every 1K in the order of address 1999 → address 2000 → address 2999, etc. Then, the final address data indicating the memory capacity determined by this check is latched in the latch circuit (A) 13 (step S1 in FIG. 3). Here, in the connector CA,
A 2KB RAM card was installed as a program card in place of RAM card 19A, and was paired with RAM card 19A on connector CB.
Since the RAM card 20A is installed as a data card, the total memory capacity is 6 KB, and therefore, the data "5999" indicating the final address is latched in the latch circuit (A) 13.

Next, data indicating the memory final address (END-Adr) according to the previous combination stored at a specific address of the RAM card 20 is successively outputted, and this is latched into the latch circuit (B) 14 (see Fig. 3). Step S2). Here, the previous memory capacity is 8 KB, so data "7999" indicating the final address is latched in the latch circuit (B) 14.

Next, the data stored in the latch circuit (A) 13 (the final address data corresponding to the current memory capacity) and the data stored in the latch circuit (B) 14 (the final address data corresponding to the previous memory capacity) are address data), the difference between the current memory capacity and the previous memory capacity is determined. That is, CPU1
0 sets the control signal (a) to “0” and the latch circuit (A)1
The data “5999” stored in 3 is transferred to the latch circuit (B).
14 is input to the arithmetic circuit 15 together with the data "7999", and the control signal (s) is set to "1".
Find the difference between the previous memory capacity and the current memory capacity. Here, the difference in memory capacity is “−
2000" is obtained. The differential data obtained by this calculation is latched in the latch circuit (A) 13 in accordance with the control signal (ck ₁ ) from the CPU 10 (step S3 in FIG. 3).

Next, CPU10 was attached to connector CB
It controls reading of the absolute address storage area of the RAM card 20A, and latches the read absolute address in the latch circuit (B) 14. That is, after sending the read address onto the address bus 11, the CPU 10 sets the control signal (b) and the control signal (c) to "0", generates the control signal ( _ck2 ), and reads out the address from the RAM card 20A. The absolute address data is transferred to the latch circuit via the data bus 12 and the bidirectional data buffer 17.
(B) Latch at 14 (Step S4 in Figure 3).

Next, the CPU 10 sets the control signal (a) to "0" and the control signal (s) to "0" to set the arithmetic circuit 15 to the addition mode, and the arithmetic and adder circuit 15 causes the latch circuit (B) to
Latch circuit (A) 13 stores the absolute address stored in 4.
The address is corrected using the difference in memory capacity stored in , and this corrected absolute address is stored in the data buffer 16 (step S5 in FIG. 3).

Further, the CPU 10 outputs the corrected absolute address stored in the data buffer 16 onto the data bus 12 by setting the control signal (b) to "1" and the control signal (c) to "0", and also indicates the write mode. A read/write signal (R/W) and a write address similar to that at the time of reading are sent, and the corrected absolute address is written back to the read address of the RAM card 20A (step S6 in FIG. 3). For example, as shown in Figure 2 a and b, variable name; AB="1234"
The absolute address of is rewritten from address 5500 to address 3500.

In this way, once the rewriting of one absolute address is completed, it is determined whether or not there are still absolute addresses to be rewritten (step S7 in Figure 3), and until there are no more absolute addresses to be rewritten. That is, the above processing operation is repeatedly executed until the rewriting of the absolute address in the RAM card 20 is completed.

As described above, when the power is turned on, the RAM cards 19 and 20 attached to the connector section 18
The memory capacity of the RAM card is determined, and as the memory capacity changes, absolute address rewriting processing is executed, making it possible to arbitrarily rearrange RAM cards with different memory capacities. Since it is possible to select and use any card from among various RAM cards according to the amount of setting information, it is possible to use a RAM card without wasting memory capacity. Furthermore, since the absolute address is rewritten when the power is turned on, address specification can be performed using the absolute address as is during execution of arithmetic operations, and therefore the arithmetic processing speed is not affected at all.

[Effects of the Invention] As detailed above, according to the present invention, in an electronic program computer equipped with a plurality of memory pack attachment/detachment mechanisms, when the power is turned on, the address space of the memory pack attached to the memory pack attachment/detachment mechanism is recognized. However, by comparing the recognized address space with the address space when the memory pack was installed and used last time, and executing the absolute address change process based on the difference in the address space,
It is now possible to arbitrarily rearrange memory packs with different memory capacities, greatly expanding the range of usable memory pack combinations, and also allowing memory packs with arbitrary storage capacities to be selected according to the storage area to be used, reducing wasted memory capacity. It is possible to provide an electronic program calculator with a memory pack, which allows the use of an economical memory pack without the need for a memory pack.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the main parts in an embodiment of the present invention, and Figures 2a and 2b are memory maps of combinations of RAM cards to explain the operation in the above embodiment. Figure shown, 3rd
The figure is a diagram showing a processing flow of main parts in the above embodiment. 10...CPU, 11...Address bus, 12
...Data bus, 13...Latch circuit (A), 14...
... Latch circuit (B), 15 ... Arithmetic circuit, 16 ... Data buffer, 17 ... Bidirectional data buffer,
18... Connector part, 19, 20... RAM card, CA, CB... Connector.

Claims (1)

[Claims] 1. In an electronic program computer equipped with a plurality of memory pack attachment/detachment mechanisms, at power-on, a means for recognizing the address space of a memory pack attached to said attachment/detachment mechanism, and a means for recognizing the address space recognized by this means in the previous memory pack. A memory pack characterized in that it is equipped with means for comparing the address space with the address space when it is installed and in use, and means for executing absolute address change processing based on the difference in the address space obtained by this means. Comes with an electronic program calculator.