JPS63296157A - Information processor - Google Patents

Abstract

PURPOSE:To perform data transfer with transfer width larger than the actual transfer width of a transfer controller, by providing an address conversion means which shifts a memory address outputted by the transfer controller by a prescribed number of bits and outputs it to an address bus. CONSTITUTION:A memory managing unit (MMU)3 performs a processing to convert addressing via a logical address bus 2 by a microprocessor (MPU)1 to a physical address on a physical address bus 5. By the processing, not only a memory M1 for main storage, but memories M2-M7 for peripheral units can be controlled dynamically. And address incrementing width can be changed by shifting the output address of a controller (DMAC)37 for transfer control. In such a way, it is possible to perform transfer with two or more byte width by shifting and converting the address incrementing width of the DMAC37 even when the transfer width of the DMAC37 is as small as around 1 byte, and to perform the transfer between memories with high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to an information processing apparatus that performs transfer processing between memories.

[Prior Art] Information processing systems comprising microprocessors, memories, and the like are widely used for processing single images of characters and various other types of digitized information.

The data bus width of a microprocessor (hereinafter referred to as MPU), that is, the data width that the processor can process at one time is 4 bits, 8 bits, 16 bits, 32 bits, etc.
As the amount of data that can be processed at once increases, the processing speed has also been significantly improved. Also,
As the data bus width expanded, the address bus width also expanded, which increased the accessible memory capacity.

However, peripheral circuits (devices) used together with MPU
Advances in ICs such as input/output processors for control, controllers for DMA (direct memory access) transfer control, and DMAC have not necessarily kept pace with MPUs, and 16- or 32-bit processors are becoming mainstream. Some devices with smaller data and address bus widths are still in use today.

Therefore, when using an MPU with a large bus width and a peripheral input/output processor in the same system, it is recommended to set up a buffer memory on the peripheral processor side, or adjust the bus width used on the MPU side to match that of the peripheral side. A method is being taken.

If a buffer memory is not used, a PIO (program pull input/output port) or the like will return a signal to the MPU indicating that the data width that can be processed is 8 bits, which is smaller than the MPU side, and the MPU will respond accordingly. It is conceivable to use a control method that adopts an adapted data width on the side.

[Problems to be Solved by the Invention] However, although this method does not pose any problems when inputting commands to peripheral processors or processing status reads, transferring a large amount of data increases the exclusive time of the system bus, causing system overhead. The problem arises that the

In view of this point, it is conceivable to transfer data using a buffer memory and expand the bus width only during transfer. However, this method requires troublesome address decoding processing, and the data width of the buffer memory is fixed to 16 bits, 32 bits, etc., which hinders system expandability.

Now let's think about DMAC. If you use a DMAC with a smaller bus width than the MPU, it may be faster for the MPU to transfer data directly, so there is no point in using the DMAC, so either do not use the DMAC, or
If DMA transfer is absolutely necessary, D with high processing power
It was necessary to develop a new MAC.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides information including a central processing unit, a memory, and a transfer control device that performs transfer between memories without going through the central processing unit. In the processing device, a configuration is adopted in which an address conversion means is provided for shifting the memory address outputted by the transfer control device by a predetermined number of bits and outputting it to the address bus when controlling memory transfer.

[Operation] According to the above configuration, by shifting the output address of the transfer control means, the address increment width can be changed and data transfer can be performed with a transfer width larger than the actual transfer width of the transfer control device. Furthermore, the memory area that can be dressed by the transfer control means can be increased by 7 times.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the configuration of an information processing apparatus employing the present invention. Here, configurations common to various computer systems or information processing devices using computers, such as word processors and image processing devices, are shown.

In the figure, what is indicated by the symbol Ml is a main memory composed of a RAM element or the like. Code M2~M
The memory indicated by 7 is used as a buffer memory for each peripheral device connected, and is configured using the same RAM.

Here, memory M2 is a buffer memory for the hard disk device 7 and floppy disk device 8, memory M3 is a buffer memory (VRAM) for the CRT display 10, and memory M4 is a keyboard 12 and pointing device 13 such as a mouse or digitizer.
Memory M5 is a buffer memory for an image printer 15 such as a dot printer and an image scanner 16 for reading images, and memory M6 is a buffer memory for an optical disc 18 such as a CD-ROM, CDI or video disc. Buffer memory, and memory M7 is used as a buffer memory for inputting and outputting information with the local area network 20 to which this system is connected.

The memories M1-M7 mentioned above are connected to the MMU 3 by a data bus and a physical address bus 5 (not shown).

In this physical address bus 5, memory cells of each memory are always handled in one-to-one correspondence with a fixed address.

The MMU (memory managing unit) 3 is composed of a family chip of the MPU 1, which is the main control unit of the device 4, a custom chip or discrete circuit designed according to the MPUI used, or the memory element used. MMU3 and MPUI are connected by logical address bus 2.

The MMU 3 performs a process of converting the addressing via the logical address bus 2 by the MPU 1 into a physical address on the physical address bus 5. Through this process, not only the memory M1 for the main memory but also the memories M2 for each peripheral device are converted.
M7 can be managed dynamically to improve memory efficiency.

The output address of MMU3 is the address multiplexer 35
is output to the physical address bus 5 via the physical address bus 5.

In this embodiment, in order to perform DMA transfer, a ready-made DMAC 37 having a bus width smaller than that of the MPU 1 is provided.

It is assumed that the DMAC 37 can perform at least transfer in byte units between the memories M1 and M7. DMAC37 is DM
When performing A transfer, it is connected to MMU3 instead of MPUI.

To switch the bus right between MPUI and DMAC37 controlling the address bus.

A bus arbiter 38 is provided. This bus arbiter 38
is a 1-bit signal PD input from the MMU33, which will be described later.
Controlled by M2. The bus arbiter 38 performs bus switching as well as MPUI.

Signals BMP and BDM indicate the presence or absence of bus ownership for the DMA C37.

Here, the structure of the MMU 3 is shown in FIG. 2. In FIG. 2, reference numeral 51 indicates logical address data output from the MPU 1 via the logical address bus 2. The logical address output by the CPU has a predetermined bit length and is divided into three predetermined blocks: upper, middle, and lower. Here, the code 51A is upper segment data, 51
B is page data and 51C is address data.

Segment data 51A and page data 51B are input to segment map 52 and page map 53, respectively, which are composed of memories storing table data for address conversion, and are input to main memory memory M according to the usage status of the memory.
1 and buffer mesh M2 to M7,
Management information and physical address information to be output to the physical address bus 5 are output to address registers 54 to 56.

The converted output data of the segment map 52 and the page data 51B are input to the page map 53, and the output is a part of the physical address output to the register 56.
The physical address output to the register 56, which becomes the DMA type code (PDM) for DMA control output to the register 54 and the management flag (Prot) output to the register 55, is the address data 51C of the input logical address. and the converted address data output from the page map 53.

Here, the management flag of the register 55 is management information of the program running in the system, and is data for identifying whether the data is a system program or a user program, and whether or not the program can access the physical memory space. It consists of an entry bit that informs whether a physical space has been accessed by a user program, and an access bit that identifies whether a physical space has been accessed by a user program. The physical address output to the register 56 is the page map 5.
3 and the input address data 51C.

FIG. 3 shows in detail the management information and physical address information for memory addressing that are output to the registers 54 to 56 in FIG.

In the figure, the symbol Prot is the aforementioned management flag, which is composed of 5 bits, where bit 5 is the entry bit, bits 4 and 3 are the processing bits, and bit 2 is the entry bit.
and bit l is an access bit.

Also, the DMA type code indicated by the symbol PDM is PO
It is composed of 3 bits: M2, PDMI, and FDMO. The most significant bit PDM2 indicates whether or not to perform DMA transfer, and is set to 1 in the case of DMA transfer.
Set to O if U performs direct transfer. This information is input directly to bus arbiter 38 to indicate bus rights.

The two bits PDMI, 0 are used to determine the data width when performing DMA transfer, that is, the address increment width. This data is input to address multiplexer 35.

The address multiplexer 35 is configured as shown in FIG. The decoder 201 is PDMI, FDMO17)OO~11 (decimal 0~
Depending on the four states up to 3), one of the four outputs O to 3 is set to high level. This output is ant game)2
02゜203... opens and closes.

Beep) Ao input via MMU3.

The output address of MPUI or D'MAC37 consisting of AI... is determined by these AND gates 202, 203...
・Shifted by. That is, Antogame) 202
．． The outputs of 203, . The output address (A”o) where the outputs of the OR gates 206, 211, 216, etc. are converted.

A'l...), enter Kabit) Ao is or gate 2
From 06.211,216, AI is ORGATE 211.
It is wired so that it can be output from 216 and 221. When the output terminal l of the decoder 201 is at a high level, Ao is outputted as A'1 and AI is outputted as A'2. That is, the input address is shifted upward by one bit. Similarly, a 2-bit or 3-bit shift can be performed by setting the output terminal 2.3 of the decoder 201 to a high level using PDMO or PDMI.

203-205, 209, 210 so that the remaining bits are filled with O's.

One input of 215 is connected to a low level.

Here, address conversion using the above configuration during DMA transfer will be explained with reference to FIG. The output address column in FIG. 5 shows in binary numbers the addresses (offsets) that are incremented when transferring between memories with transfer widths of 1 byte, 2 bytes, 4 bytes, and 8 bytes. In the case of a 1-byte transfer, the memory cell is accessed 1 byte at a time, so in the case of a (word) transfer, the memory address jumps by one, and the address increment is 0°10.100...
・It becomes.

If DMAC performs a 1-byte transfer,
The address increment is 6.1°lO...

However, if word transfer is possible between memories using a 16-bit data bus, if the address input from the DMAC is converted as 0.10, 100°110, etc., and memory access is performed, Word (16 bit) transfer is possible even when the DMAC is operating to perform byte transfer. Similarly, set the input address to 0, 1
By converting as 000, 1100, etc., it is possible to transfer 4 bytes (long word: 32 bits).

The above conversion is possible by shifting the input address data by 1 or 2 bits.

Therefore, by changing the PDMI and FDMO patterns as shown, it is possible to shift 1 and 3 bits of θ pits, respectively, and thereby, addressing corresponding to 1 to 8 byte width transfers is possible.

By having the address multiplexer 35 perform the above address conversion processing, even when the DMA C37 is incrementing the address with a 1-byte transfer width, the physical address is 2 bytes (word: 16 bits) or 4 bytes (long word). : 32 bits), 8 bytes (double longword: 64 bits)
Highly efficient inter-memory transfer is possible even when using a chip.

FIG. 6 shows the processing procedure in the above overall configuration. DMA transfer control in the overall configuration will be described below with reference to FIG.

When the system is powered on, first in step St, the MPUI initializes each section and loads programs necessary for initial operation from the hard disk 7, floppy disk 8, or ROM (not shown) into the memory M1.

In step S2, mapping of the MMU 3 is performed according to the loaded program. Based on unique information about each peripheral device connected to the bus, the DM
The presence or absence of A transfer, DMA transfer length, data width, etc. are set for each peripheral device. As a result, from now on, by only inputting the logical address, the management flag Fre shown in FIG.
t, a DMA type code PDM, and a physical address are generated, and transfer conditions suitable for each device can be set.

In step S3, it is determined whether DMA transfer is to be performed. When performing DMA transfer, the PD
M2 is set to high level, and the bus arbiter 3B separates MPUI from the bus using control signals BDM and BMP, and disconnects the DMA.
Connect C37 to bus.

In step S5, two bits of PDMI and FDMO are controlled according to the transfer width of the peripheral device to the buffer memory. This allows the subsequent transfer width, i.e. (and)
It is determined how address increments are performed on the physical address bus. From now on, PDMI, F
The shift width of address multiplexer 35 is controlled according to DMO. In step S6, the processor on the peripheral device side examines the PDMI and FDMO bit patterns and recognizes what transfer width has been selected.

When a request for DMA transfer is input from the peripheral device in step S7, bus ownership is transferred from MPU 1 to DMAC 37 in step S8, and DMA transfer is started.

DMAC37 operates to perform byte transfer,
Actual address increment is PDML, FDMO
The transfer is controlled as shown in FIG. 5 according to the value of , and a 2-byte, 8-byte width transfer is executed.

When the completion of transfer is confirmed in step S9, step 51
When the value is 0, the bus right is returned to MPUI, and the transfer process ends.

As described above, according to this embodiment, even if the transfer width of the DMAC37 is as small as about 1 byte, by shifting and converting the address increment width of the DMA C37, it is possible to transfer a width of 2 bytes or more. , it is possible to achieve the excellent effect of enabling highly efficient memory-to-memory transfer.Also, by shifting the address data to the upper
A zero-order example will be presented that provides the advantage of greatly expanding the area that the MAC can access nakedly.

For example, if the data bus width of the system shown in FIG.
C is the upper limit of a 24-bit address in the conventional system, that is, 16
It is impossible to perform addressing over an area larger than MB.

Therefore, MPU l connects PDM2 to PDM via MMU3.
By setting 3 bits of O to rlolJ, the output address of the DMAC 37 can be shifted by 1 bit using the address multiplexer 35 to perform a 32-bit width transfer. This allows the transfer speed to be doubled and the addressable area to be doubled.

In the above configuration, the DMA transfer width set by the DMA type code PDM can be changed by software, so the setting can be changed depending on the peripheral device.
A flexible system can be configured.

[Effects of the Invention] As is clear from the above, according to the present invention, in an information processing device including a central processing unit, a memory, and a transfer control device that performs transfer between memories without going through the central processing unit, The memory address output by the transfer control device when controlling memory transfer is shifted by a predetermined number of pits and is outputted to the address bus. According to the present invention, the efficiency of memory transfer can be increased because data transfer can be performed with a large transfer width and the memory area that can be addressed by the transfer control means can be increased. Also, efficient transfer control can be performed even when using transfer control means with a small bus width.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing device adopting the present invention, FIG. 2 is a block diagram showing the configuration of the MMU in FIG. 1, and FIG. 3 is an explanatory diagram showing output data of the MMU. , Fig. 4 is a circuit diagram showing the configuration of the 7-dress multiplexer shown in Fig. 1, and Fig. 5 is a circuit diagram showing the state of address conversion.
6 is a flowchart showing the operation of the overall configuration of FIG. 1. 1...MPU 2...Logical address bus 3...MMU 35...Address multiplexer 37...DMAC38...Bus arbiter MINM7
...Memory Figure 3 Figure 4 Ryo V Shimata Irekuri no Shito's 1 Clam e Tsukiguchi Figure 5 Meiou! 411@70-+7- M6 figure to deaf self

Claims (1)

[Scope of Claims] 1) In an information processing device including a central processing unit and a transfer control device that performs transfer between memories without going through the memory and the central processing unit, when the transfer control device controls memory transfer, An information processing device comprising an address converter that shifts an output memory address by a predetermined number of bits and outputs the shifted memory address to an address bus. 2) The information processing device according to claim 1, wherein the bit shift width of the address conversion means can be set by a central processing unit.