JPH02195431A - Address operation control device - Google Patents

Abstract

PURPOSE:To prevent the execution time of a bit operating instruction from being increased by controlling the substitution of a prescribed bit for the lower bit side of an access address so that the operand of a specified size does not exceed the word boundary of a memory in accordance with the access address and the specified data size information of the operand. CONSTITUTION:A base address BA for specifying data obtained by setting up the set of plural bits as a minimum unit is inputted from an input circuit 2 to one input terminal of an adder 1 in an address operation control device and an OFFSET for applying the bit operating position of data based upon the base address BA is applied to the other input terminal through an input circuit 3 and a shift circuit 4. The adder 1 forms the access address AA of data including a bit to be operated by using the OFFSET and the lower bits and upper bits are respectively inputted to a selector 5 and an output circuit 6. The prescribed bit is substituted for the lower bit side of the access address AA by a selector 5 so that the operand does not exceed the word boundary of the memory and controlled by a substitution control unit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for generating an access address for an operand containing bits to be manipulated by a bit manipulation instruction, and relates to a technology for generating an access address for an operand that includes a bit to be manipulated by a bit manipulation instruction, and for example, The present invention relates to a technique that is effective when applied to a processor where a plurality of operand sizes are subject to bit manipulation instructions.

[Prior art]

In a microprocessor that uses the pick-endian system, the operands required for instruction execution are based on the least significant bit, regardless of its size, in other words,
It is handled so that the least significant bits are aligned. on the other hand,
When a bit manipulation instruction is executed, an offset indicating the bit manipulation position of the target operand is given based on the most significant bit of the operand.

In such a processor, the access address of an operand containing a bit to be manipulated by a bit manipulation instruction is calculated using a base address and an offset indicating the bit manipulation position based on the base address. That is, if the address output from the processor is a byte address, shift the offset by 3 bits to the right, convert it to a byte address, and add the converted byte address and base address to determine the access address of the operand. calculate.

Incidentally, conventionally, the operand size handled by bit manipulation instructions was usually fixed to a byte (8 bits), but for example, the operand size of most instructions for a 32-bit processor is halfword (16 bits) or word (32 bits).
Since data sizes such as bits are also allowed, the inventor is considering increasing the degree of freedom by allowing arbitrary data sizes such as bytes, halfwords, and words for the operands of bit manipulation instructions. did.

For example, when a byte address that specifies data in 8-bit units has a 32-bit configuration, and data input/output to and from memory is performed in 32-bit units, the memory access address is essentially the 32-bit byte address. The upper 30 bits are assumed to be the upper 30 bits. Therefore, when the access address of the above operand is specified by a byte address, when accessing a halfword or word-configured operand based on this access address,
Depending on the value of the lower two bits of the access address of the operand given as a byte address, it may be necessary to access the memory multiple times beyond the word boundary of the memory. More specifically, in FIG. 6, which shows an example of address mapping in memory space, the byte data access address containing operation target pin 1- is at address 11 (01,03°...1,0,111°). ), and the data size of the operand is specified as word, the required operand is located at 12fi beyond the memory word boundary from address 11 (031,030...13).
1□○ 工 0, ), 13th address (03,03o-1,1□0
．． 1. ).

14 address (Oi□03o・=13121□Oo), so to access the operand, 11
An address (0, 10, . . . 13
0, ), and the lower 2 bits of the address specifying address 12 and 4 are ignored, effectively 12
An address that specifies a street address (0□, 0.....1
31□), it is necessary to perform it twice. still,
The suffix attached to each bit means the bit number of the address from the lower order side.

In this way, when accessing memory to obtain an operand for a bit manipulation instruction, depending on the relationship between the specified operand size and the access address of the operated operand, when reading an operand of the specified size, It has been found that there are cases in which memory must be accessed multiple times across memory word boundaries.

An example of an address arithmetic device described is Japanese Patent Application No. 197146/1983.

[Problem to be solved by the invention]

However, if multiple memory accesses are required across memory word boundaries, the execution time of the bit manipulation instruction increases accordingly. For example, when drawing graphics to a frame buffer, when bit manipulation instructions are used to perform color operations on specific bits of each pixel data to remask, the increased execution time of the bit manipulation instructions will reduce the processing efficiency of graphics drawing. .

By the way, the operands required in the execution of a bit manipulation instruction only need to include the bit to be manipulated.

Therefore, the present inventor investigated a technique for converting the access address so that the operand of a specified size does not exceed the word boundary of the memory, according to the access address and operand size of the operand calculated based on the base address and offset. . In this case, we first considered a process that relies exclusively on software, such as repeating an operation many times that sequentially updates the access address of the operand according to the operand size and the access address of the calculated operand. In this method, since addition and shift operations for address operations are performed multiple times, the number of execution steps of the program increases. Therefore, the present inventor devised a hardware method to prevent an operand of a specified size from exceeding the memory word boundary, according to the operand access address and operand size calculated based on the base address and offset. This study examines ways to do so.

An object of the present invention is to provide an address arithmetic control device that can obtain the access address of an operand in a short time without placing a burden on software even if the operand size handled by a bit manipulation instruction is arbitrarily specified. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, for the access address of the operand obtained by the arithmetic means that calculates the address of the operand that includes the bit to be manipulated by the bit manipulation instruction, the data size information specified for the operand and the access address are , a selector is provided for controlling and replacing the lower bit side of the access address of the operand with a predetermined bit so that the operand of the specified size does not exceed the word boundary of the memory.

For example, when the minimum unit of data specified by an address is a byte, the operand size that can be specified is a byte, halfword, or word, and the boundary of an address that specifies data in words is a word boundary, the above The selector outputs the access address of the operand as it is in response to the operand size being a byte, and when the operand size is a halfword, it replaces the least significant bit of the operand address with the bit "Oj" and changes the operand size to a word. , the lower two bits of the access address of the operand are set to bits ro and O.
It can be configured so that it is output in place of J.

In order to minimize software changes due to the addition of such selectors, microinstructions for generating control information that enable selector operations are included in the microprogram series corresponding to the bit manipulation instructions, and the bit manipulation instructions It is sufficient to provide a control means for generating a control signal for replacing a predetermined bit by the selector based on the decoding result of the operand size information included in the operand size information. Furthermore, the instruction decoder may have logic that generates control information that enables the selector to operate and a control signal for replacing a predetermined bit by the selector, based on the operation code and operand size information of the bit manipulation instruction. .

[For production]

According to the above means, the selector masks a predetermined bit of the access address of the operand calculated based on the base address and the offset with a predetermined bit in hardware according to the operand size, thereby masking the operand of the specified size. is prevented from exceeding memory word boundaries. As a result, even if the operand size handled by the bit manipulation instruction is arbitrarily specified, the access address of the operand can be obtained in a short time without placing a burden on the software.

〔Example〕

FIG. 1 shows a block diagram of an address arithmetic control device which is an embodiment of the present invention. This address arithmetic control device is included in an arithmetic execution unit and an instruction control unit of a processor or the like. A processor including this address arithmetic control device is
Although not particularly limited, it includes a 32-bit CPU (central processing unit), and is capable of performing various data and address operations using 32 bits. The size of the operand used for instruction execution by this processor is a word (32 bits).
, halfword (16 bits), and byte (8 bits) can be freely selected. Further, although not particularly limited, the processor recognizes the minimum unit of data specified by an address as a byte, and this byte address is composed of 32 bits. Therefore, if the least significant bit of the 32-bit byte address is ignored, the memory space can be understood in halfword units, and if the lower two bits are ignored, the memory space can be understood in word units. In this example,
Operands that are the targets of bit manipulation instructions are stored in a memory that inputs data in units of 32 bits, although there are no particular restrictions. Therefore, the access address of this memory is the lower 2 of the 32-bit byte address.
It is a 30-bit word address that essentially ignores bits. In such memories, word boundaries are
The boundaries of addresses that specify data in units of words, that is, the upper 30 bits of a 32-bit byte address, are the boundaries of data to be changed.

In FIG. 1, 1 is a 32-bit adder circuit, one input terminal of which is coupled with an input circuit 2, and the other input terminal of which is coupled with an input circuit 3 and a shift circuit 4 in series. The 32-bit output terminal of the addition port "N11" has the lower 2 bits passed through the selector to the output circuit 6.
The remaining 30 bits are then directly coupled to the output circuit 6,
This output circuit 6 provides a 32-bit address to an address output register 7 connected to an address bus (not shown).

When calculating the access address of data including the bit to be manipulated in order to execute a bit manipulation instruction, the input circuit 2 is given the base address BA, and the other input circuit 3 is given the access address for the data based on the base address BA. An offset 0FFSET is provided to provide the bit operation position.

The shift circuit 4 shifts the offset FF5ET to the right, that is, to the lower order, by 3 bits and converts it into a byte address. For example, as shown in FIG. 5, when the base 7 dress BA is address 10 (OazOao-130z1.0.),
When the offset 0FFSET is given as the 10th bit (0,,03°...13021,0°), the output of the shift circuit 4 is (03□O1°...0.0□011
By adding both data, the adder circuit 1 sets address 11 (o31) as the access address AA.
o3°...130.1□1°) is obtained.

When the operand size is a byte, the selector 5 applies the lower two bits of the access address AA to the output circuit 6 without changing them. When the operand size is a half word, the least significant bit of the access address AA is masked to bit "O" and provided to the output circuit 6. When the operand size is a word, the lower two bits of the access address AA are masked as ro and OJ and provided to the output circuit 6.

The mask processing according to the data size for the lower two bits of the access address AA has the meaning of preventing the access address for the operand of the specified data size from exceeding the word boundary of the memory. That is, when the operand size is a byte, by accessing the memory using the upper 30 bits of the access address AA calculated by the adder circuit 1, a byte-sized operand can be obtained with one memory access. However, when the operand size is halfword, the access address AA is address 11, 15 as shown in FIG.
When located at a word boundary such as an address, a halfword-sized operand cannot be obtained with just one memory access using the upper 30 bits of the access address AA. In such a case, if the least significant bit of the access address AA is masked to "0", if the access address AA is located on a word boundary of the memory, the address immediately before the access address AA will be changed to a new address. It acts to generate the access address AA'.

Also, if the operand size is words.

If the access address AA is located at an address other than the word boundary, such as address 8 or 12 as shown in FIG.
It is not possible to obtain a word-sized operand with only one memory access. In such a case, if the lower two bits of the access address AA are masked to ro and OJ, if the access address AA is actually located outside the word address of the memory, the access address AA will be changed to the word address of the memory. The access address AA' is converted into a new access address AA' corresponding to the access address AA'.

Note that the access address changes from AA to AA', or from AA
', the position of the target bit to be bit manipulated is changed relative to the most significant bit position of the operand to be accessed in memory, but the The change position can be obtained from the operand size information.

In FIG. 1, mask control for the selector 5 is included in the instruction control system of the processor. This command control system is
Although not particularly limited, the control unit 1 performs microprogram control, decodes macroinstructions with an instruction decoder 10, and sequentially reads out microinstructions from the microprogram 11 according to the decoding results.
2 decodes and generates control signals for each part. A bit manipulation instruction includes a corresponding instruction code, and also includes operand size information and the like. The microinstruction read out from the microprogram 11 in accordance with the decoding result of the operation code corresponding to the bit manipulation instruction includes a control code that causes the selector 5 to perform a mask processing operation. When this control code and information corresponding to the size of the operand are given to the control unit 12 from the instruction decoder 10, the control unit 12 instructs the selector 5 to select bit r for the lower two bits of the access address AA according to the operand size.
Instructs a predetermined masking process to replace OJ.

Mask control for the selector S may be performed using the output of the direct command decoder 13, as shown in FIG. In this case, decode the operation code of the bit manipulation instruction and the operand size information,
It is necessary for the instruction decoder 13 to have logic for generating control information that enables the operation of the selector 5 and a control signal for replacing predetermined bits by the selector.

As is clear from the explanation of the operation control for the selector 5, the address operation control circuit of this embodiment is not dedicated to the operation of access addresses for bit manipulation instructions, and the operation of the selector is not selected. When the adder circuit 1 is running, all bits of the address output from the adder circuit 1 are directly applied to the output circuit 6, and are also used for other address operations.

The position where the selector 5 is provided is not limited to the position shown in FIGS. 1 and 2, but may be provided after the address output register 7 as shown in FIG. It may also be provided between the circuit 6 and the address output register 7.

According to the above embodiment, the following effects can be obtained.

(1) The selector 5 masks the predetermined bits of the access address AA of the operand calculated by the adder circuit 1 based on the base address BA and the offset 0FFSET with predetermined bits in hardware according to the operand size, and includes the target bit. Since operands of the specified size are prevented from exceeding memory word boundaries, even if the operand size handled by a bit manipulation instruction is specified arbitrarily, the access address of the operand can be obtained in a short time without putting a burden on the software. can do.

(2) From the above effects, it is possible to increase the degree of freedom in the operand size handled by bit manipulation instructions while suppressing the increase in execution time of bit manipulation instructions. (3) Decoding results of operand size information included in bit manipulation instructions By providing a control means for generating a control signal for replacing a predetermined bit by the selector based on the above, the microprogram series corresponding to the bit manipulation instruction is provided with control information that enables the selector to operate according to the operand size. It is only necessary to add a microinstruction for generating the selector 5, thereby minimizing software changes due to the addition of the selector 5.

(4) Based on the operation code and operand size of the bit manipulation instruction, the instruction decoder 13 is provided with logic that generates control information that enables the operation of the selector and a control signal for replacing a predetermined bit by the selector. Although the hardware configuration of the decoder 13 itself becomes relatively complex, on the other hand, the burden on the software can be further reduced.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the operand size processed by a bit manipulation instruction is a word or a halfword.

Although the description has been made based on three types of data size and byte, the data size is not limited to these three types, and may be any combination of data sizes or other sizes.

In the above explanation, the invention made by the present inventor was mainly applied to a 32-bit processor that adopts the pick-endian system, which is the field of application that formed the background of the invention, but the present invention is not limited thereto. The present invention can be widely applied to various data processing devices such as processors that employ the little endian system, 16-bit processors, and controllers that perform other bit operations. The present invention can be applied at least to conditions for calculating the access address of data subject to bit manipulation.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, for the access address of the operand that includes the bit to be manipulated by a bit manipulation instruction, the lower side of the access address is Since a selector is provided to control the replacement of bits with predetermined bits, even if the operand size handled by a bit manipulation instruction is arbitrarily specified, the access address of the operand can be obtained in a short time without putting any burden on the software. effective.

In addition, the microprogram provides instructions that enable the selector to operate, and the mask control by the selector according to the operand size is performed according to the decoded result of the operand size information without defining it in the microprogram. By providing this, changes in the microprogram can be reduced, and an increase in the microprogram capacity can be suppressed.

Based on the operation code and operand size information of the bit manipulation instruction, the instruction decoder is provided with logic that generates control information that enables the selector to operate, as well as a control signal for replacing a predetermined bit by the selector. This has the effect that software dependence when calculating the access address of the target operand can be further reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address arithmetic control device which is an embodiment of the present invention, FIG. 2 is a block diagram of an address arithmetic control device which is another embodiment of the present invention, and FIG. 3 is a block diagram of an address arithmetic control device which is an embodiment of the present invention. A block diagram showing an embodiment in which the position of the selector is changed from the configuration in Fig. 2, Fig. 4 is a block diagram showing another embodiment in which the position of the selector is further changed, and Fig. 5 is a block diagram showing an example in which the position of the selector is changed. FIG. 6 is an explanatory diagram of an example of an access address to be accessed. FIG. 6 is an explanatory diagram of word boundaries in the memory address space. DESCRIPTION OF SYMBOLS 1... Addition circuit, 2, 3... Input circuit, 4... Shift circuit, 5... Selector, 6... Output circuit, 7...
...Address output register, 10...Instruction decoder,
11...Microprogram, 12...Control unit, 13...Instruction decoder, BA...Base address, 0FFSET...Offset, A, A', A?・
...Access address. Figure 2 Figure 1

Claims (1)

[Claims] 1. Accessing data that includes the bit to be manipulated using a base address that specifies data whose minimum unit is a set of multiple bits and an offset that provides a bit manipulation position for the data at this base address. According to the arithmetic means that generates the address and the data size information specified for the access address and operand obtained by this arithmetic means, the lower order of the access address is An address arithmetic control device comprising a selector for controlling the bit side to be replaced with a predetermined bit. 2. The above base address specifies byte data, the operand sizes that can be specified are byte, halfword, and word, the word boundary of the memory above is the boundary of the address that specifies data in word units, and the selector above is , the above access address is output as is in response to the operand size being a byte, and when the operand size is a halfword, the least significant bit of the access address is replaced with bit "0" and output, and the operand size is a word. 2. The address arithmetic control device according to claim 1, wherein the lower two bits of the access address are replaced with bits "0, 0" and outputted at some time. 3. Control memory that includes microinstructions for generating control information that enables the operation of the selector in a microprogram series corresponding to bit manipulation instructions, and based on the decoding result of operand size information included in the bit manipulation instructions. 3. The address arithmetic control device according to claim 1, further comprising control means for generating a control signal for replacing a predetermined bit by said selector. 4. An instruction decoder including logic for generating a control signal that enables the operation of the selector and a control signal for replacing a predetermined bit by the selector, based on the operation code of the bit manipulation instruction and the operand size specification information. The address arithmetic control device according to claim 1 or 2, comprising: