JPS63292678A - Mos transistor - Google Patents

Abstract

PURPOSE:To suppress the injection of hot carriers into a sidewall layer and to enhance reliability, by providing the sidewall layer comprising an insulating film on the side surface of a gate electrode, and providing a metal silicide layer directly beneath the side wall layer. CONSTITUTION:A metal silicide layer 7 forms a very low resistance layer at an interface between a sidewall layer 8 and a drain region 11 and assists the running of hot carriers into the drain region 11. Therefore, injection of the hot carriers into the sidewall layer 8 is suppressed. The metal silicide layer 7 is made to function so as not to give energy into the hot carriers in the vicinity of the drain region 11 by forming an equipotential plane directly beneath the sidewall layer 8 and by alleviating an electric field directly beneath the sidewall layer. Therefore, the injection of the hot carriers into the sidewall layer 8 is suppressed also in this respect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a MOS transistor.

[Conventional technology]

FIG. 3 shows the cross-sectional structure of a conventional MOS transistor, in which 1 is a substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a high concentration diffusion region (train region 11), 1
0 is the source area.

In a MOS transistor having this structure, as the gate length becomes shorter due to progress in miniaturization, characteristic deterioration phenomena such as punch-through phenomenon and decrease in threshold voltage (v+h) occur. Furthermore, the reduction in the effective channel length L2 due to the deep diffusion depth XJ+ of the high concentration diffusion region 4 further promoted the deterioration of the characteristics.

The transistor shown in FIG. 4 is an eleventh proposed transistor that suppresses such characteristic deterioration.
It has a Lighl, Jy Doped Drain) structure.

That is, in this transistor, after forming the gate electrode 2, a shallow low concentration diffusion region 5 with a relatively low impurity concentration is formed.
is formed, and then CVD (Chemical Vapo
An insulating film is formed on the entire surface using a method such as RI E (Reactive Jon Deposition).
A sidewall layer 8 is formed by etching, and then a high impurity concentration diffusion region 4 is formed.

In this structure, the low concentration diffusion region 5 suppresses electric field concentration in the vicinity of the train, and the effective channel length is difficult to shorten, so that the above problem does not occur.

However, the charges (carriers) traveling from the source region 10 side have to obtain the maximum energy near the train region 11 and then pass through the low concentration diffusion region 5, and at this time, they must receive sufficient energy. The obtained carriers (hot carriers) are injected into the sidewall layer 8 with a certain probability (
13) in the figure. Note that 12 is a traveling carrier path ``C''. This causes changes in the reliability and characteristics of the transistor.

In order to suppress such a phenomenon peculiar to the LDD structure, the concentration of the low concentration diffusion region 5 is slightly increased to
(Moderately Lightly Doped
Drain) structure, or as shown in FIG.
A method such as a Buried LDD (D) structure has been adopted.

[Problem that the invention seeks to solve]

However, even in these structures, an electric field exists at the interface between the sidewall layer 8 and the drain region 11, and since there is a relatively high resistance layer directly under the sidewall layer 8, hot carriers in the sidewall layer 8 injection is not completely suppressed.

This invention was made in order to solve the above-mentioned problems, and it is possible to suppress injection of hot carriers into the sidewall layer, and therefore, it is possible to suppress the injection of hot carriers into the sidewall layer.
The purpose is to obtain an S transistor.

[Means for solving problems]

The MOS transistor according to the present invention has a structure in which a sidewall layer made of an insulating film is provided on the side surface of the gate electrode, and a metal silicide layer is provided directly below the sidewall layer.

[Effect]

The metal silicide layer forms an extremely low resistance layer at the interface between the sidewall layer and the drain region, and helps hot carriers travel to the train region, thereby suppressing injection of hot carriers into the sidewall layer. In addition, the metal silicide layer forms an equipotential surface directly below the sidewall layer, which alleviates the electric field directly below the sidewall layer and prevents energy from being imparted to hot carriers near the drain region. Injection of carriers into the sidewall layer can be suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Note that the same or equivalent parts as in FIG. 4 are given the same reference numerals.

The transistor of this embodiment has an LDD structure shown in FIG.
In comparison with an OS transistor, this transistor has a structure in which a metal silicide layer 7 is provided directly under the sidewall layer 8 of the same transistor.

The method for manufacturing the transistor described above will be explained in the order of steps with reference to FIG. 2 as follows.

(1) First, a gate insulating film 3 and a polysilicon or metal gate electrode 2 are formed on a substrate 1 using techniques such as thermal oxidation, CVD, photolithography, etching, etc. (Fig. 2(a)) ).

(2) After forming a shallow low-concentration diffusion region 5 in the substrate 1 by ion implantation or the like, a thin insulating film 9 (preferably with the same thickness as the gate insulating film 3) is formed over the entire surface (see FIG. 2). b
)).

(3) This insulating film 9 is etched by RIE to leave a first sidewall layer 9 on the side surfaces of the gate electrode 2 and gate insulating film 3 (FIG. 2(C)).

(4) Titanium (Ti), molybdenum (Mo), platinum (p
A metal film 14 forming a silicide compound such as t) is formed over the entire surface (FIG. 2(d)).

(5) Immediately thereafter, heat treatment is performed to remove the gate electrode 2 portion (only in the case of polysilicon) and the source and drain regions 10.
A metal silicide layer 7 is formed on 11, and then the metal in unreacted portions is removed (FIG. 2(e)).

(6) Form an insulating film and immediately perform RIE to form a second sidewall layer 8 on the side surface of the first sidewall layer 9.
(Fig. 2(f)).

(7) Forming a deep high concentration diffusion region 4 in the substrate 1 (second
Figure (g)).

(8) Remove the metal silicide layer 7 except directly below the sidewall layer 8 (FIG. 1). Note that this step is performed as necessary.

Next, the operation based on the above configuration will be explained.

The metal wrinkle site layer 7 forms an extremely low resistance layer at the interface between the sidewall layer 8 and the drain region 11, and helps hot carriers travel to the train region 11. For this reason,
Injection of hot carriers into the sidewall layer 8 is suppressed.

Furthermore, the metal silicide layer 7 forms an equipotential surface directly below the sidewall layer 8 and functions to prevent energy from being imparted to hot carriers near the drain region 11 by relaxing the electric field directly below the sidewall layer. . Therefore, in this aspect as well, injection of hot carriers into the sidewall layer 8 is suppressed.

〔Effect of the invention〕

As described above, according to the present invention, since a low-resistance metal silicide layer is provided directly under the sidewall layer, injection of hot carriers into the sidewall layer is suppressed, and a highly reliable MO3I transistor is realized. You can get it.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS.
(g) is a cross-sectional view for explaining the manufacturing process of the MOS transistor according to the embodiment, and FIGS. 3 to 5 are conventional MOS transistors.
FIG. 2 is a cross-sectional view of a transistor. 1 is a substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a high concentration diffusion region, 5 is a low concentration diffusion region, 8 is a second sidewall layer, 9 is a first sidewall layer, 10 is a source Area 11 is a train area. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A MOS transistor characterized in that a sidewall layer made of an insulating film is provided on a side surface of a gate electrode, and a metal silicide layer is provided directly below the sidewall layer.