[go: up one dir, main page]

JPS63280222A - liquid crystal display device - Google Patents

liquid crystal display device

Info

Publication number
JPS63280222A
JPS63280222A JP62114672A JP11467287A JPS63280222A JP S63280222 A JPS63280222 A JP S63280222A JP 62114672 A JP62114672 A JP 62114672A JP 11467287 A JP11467287 A JP 11467287A JP S63280222 A JPS63280222 A JP S63280222A
Authority
JP
Japan
Prior art keywords
light
liquid crystal
source
electrode
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62114672A
Other languages
Japanese (ja)
Inventor
Kikuo Ono
記久雄 小野
Akio Mimura
三村 秋男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62114672A priority Critical patent/JPS63280222A/en
Publication of JPS63280222A publication Critical patent/JPS63280222A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To reduce a threshold voltage by shielding light at a joint between source and drain layers generating current based upon light and a channel layer in a channel semiconductor layer. CONSTITUTION:When a substrate 1 is transmission type liquid crystal display device, a glass or quartz transparent insulating substrate 1 is used. A non-doping layer 4 containing no impurity and drain and source layers 5, 6 implanting phosphorus or the like into p-Si by ion implantation e.g. and having low resistance are formed in a p-Si channel layer. When a light shielding electrode 9 is divided in the channel direction and light shielding electrode structure including an area with length L1 having no light shielding electrode is formed, light shielding capacity equivalent to a fully shielded element is obtained. Since an element having a light shielding effect, a low threshold voltage, small capacity between the source and drain and low crosstalk can be formed in said element structure, a liquid crystal display device having clear image characteristics even at the time of radiating light can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、液晶表示装置の構造に係り、光照射時に良好
な素子特性を持つ薄膜トランジスタを有し、良好な画質
特性を実現した液晶表示装置。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a liquid crystal display device, and relates to a liquid crystal display device that has thin film transistors that have good element characteristics when irradiated with light and achieves good image quality characteristics. .

〔従来の技術〕[Conventional technology]

近年、テレビやコンピュータ一端末の表示装置、あるい
は、大画面の透過型表示装置として、平面液晶表示装置
の開発が進んでいる。これらの表示装置の構造は、ガラ
スや石英のような透過率の高い基板上に、薄膜トランジ
スタや薄膜ダイオードを形成し、これを赤、青、緑のカ
ラフィルタ−を装置した上板との間に1例えば、T N
 (TwistedNematic )液晶を封入して
、基板裏面あるいは上面に光源を置き、各画素を前記の
トランジスタあるいはダイオードを液晶を駆動するスイ
ッチとして用いて表示させるものである。この装置の表
示コントラストや画質の良好さは基板上に形成する薄膜
トランジスタの特性に大きく依存する。例えば、液晶を
反転させるためには十分大きいオン電流1画面を保持す
るために十分小さいオフ電流特性があれば、コントラス
トの大きい表示装置が実現できる。トランジスタの特性
の中でオフ電流は光の影響を大きく受け、光照射時にオ
フ電流が増加して画質が低下する場合が多い。これらの
光照射時の画質の劣化を防止するには、光により電流が
増加する薄膜トランジスタのみを光の通りにくい、例え
ば、AQやCr等の金属で遮光する技術が用いられてお
り、これらの遮光構造を持った表示装置としては、従来
、ソサイアテイ フォア−インフォメーション ディス
プレイ、インターナショナル、シンポジウム、ダイジェ
スト オフテクニカル ペーパーズ、(1986年)第
289頁から第292頁(S I D 、 Inter
nationa QSymposium Digest
 of Technica Q 、Papers。
In recent years, flat liquid crystal display devices have been developed as display devices for televisions and computer terminals, or as large-screen transmissive display devices. The structure of these display devices is to form thin film transistors and thin film diodes on a substrate with high transmittance, such as glass or quartz, and to connect these thin film transistors and thin film diodes to an upper plate equipped with red, blue, and green color filters. 1 For example, T N
(Twisted Nematic) Liquid crystal is sealed, a light source is placed on the back or top of the substrate, and each pixel is displayed using the transistor or diode described above as a switch for driving the liquid crystal. The display contrast and image quality of this device largely depend on the characteristics of the thin film transistor formed on the substrate. For example, if the on-state current is large enough to invert the liquid crystal, and the off-current is small enough to maintain one screen, a display device with high contrast can be realized. Among the characteristics of a transistor, the off-state current is greatly affected by light, and in many cases, the off-state current increases during light irradiation, resulting in a decrease in image quality. In order to prevent the image quality from deteriorating when irradiated with light, a technique is used in which only thin film transistors whose current increases with light are shielded from light with a metal such as AQ or Cr, which is difficult for light to pass through. Conventionally, as a display device with a structure, there is a display device such as Society for Information Display, International Symposium, Digest Off-Technical Papers, (1986), pp. 289 to 292 (SID, Inter
nationa QSymposium Digest
of Technica Q, Papers.

(1986)pp289−292)において論じられて
いる。
(1986) pp 289-292).

従来構造の表示装置の中の薄膜トランジスタ部の素子構
造断面図を第2図に示す。第2図は薄膜トランジスタの
チャネル部の半導体層として、水素をドープしたアモル
ファスシリコン(a−3i:H)を用いたスタガ構造の
薄膜トランジスタである。
FIG. 2 shows a cross-sectional view of the element structure of a thin film transistor section in a display device having a conventional structure. FIG. 2 shows a thin film transistor with a staggered structure in which hydrogen-doped amorphous silicon (a-3i:H) is used as the semiconductor layer of the channel portion of the thin film transistor.

1は基板、2はゲート電極、3はゲート絶縁膜。1 is a substrate, 2 is a gate electrode, and 3 is a gate insulating film.

4はチャネル層でこれをa−8i:Hで形成する。4 is a channel layer formed of a-8i:H.

5.6はそれぞれソース、ドレイン層で、これはa−S
i:Hにリンが十分ドープされた高濃度の半導体層であ
る。7はソースコンタクト電極、8は保護絶縁膜、9は
遮光電極であり、図中に矢印で示した光照射をシールド
して4のチャネル層に光が直接照射されない構造を形成
している。10はドレインコンタクト電極、11は表示
電極で通常ITO(インジウムスズ酸化物)等の透明電
極で、この電極へトランジスタの電流を流して液晶を反
転させる。第2図の遮光電極構造はゲート電極に多結晶
シリコン、チャネル層に多結晶シリコンを用いた自己整
合コープレナー型の薄膜トランジスタにも容易に適用で
きる。従来技術を用いたコープレナー型薄膜トランジス
タの断面構造を第3図に示す。第3図の構造の薄膜トラ
ンジスタの半導体材料としてはa−8i:Hより形成温
度の高い多結晶シリコン(p−8i)が用いられている
。第3図の構造部の各部分の名称は第2図のそれと同じ
であり、9は遮光電極である。通常、4のチャネル部に
p−3iを用いた薄膜トランジスタで形成した液晶表示
装置では、9の遮光電極を形成していない場合が多い。
5.6 are the source and drain layers, respectively, which are a-S
i: This is a highly concentrated semiconductor layer in which H is sufficiently doped with phosphorus. Reference numeral 7 denotes a source contact electrode, 8 a protective insulating film, and 9 a light-shielding electrode, forming a structure in which the channel layer 4 is not directly irradiated with light by shielding it from light irradiation as indicated by arrows in the figure. 10 is a drain contact electrode, and 11 is a display electrode, which is usually a transparent electrode made of ITO (indium tin oxide) or the like, and a transistor current is passed through this electrode to invert the liquid crystal. The light-shielding electrode structure shown in FIG. 2 can be easily applied to a self-aligned coplanar thin film transistor using polycrystalline silicon for the gate electrode and polycrystalline silicon for the channel layer. FIG. 3 shows a cross-sectional structure of a coplanar thin film transistor using the conventional technology. Polycrystalline silicon (p-8i), which has a higher formation temperature than a-8i:H, is used as a semiconductor material for the thin film transistor having the structure shown in FIG. The names of each part of the structure in FIG. 3 are the same as those in FIG. 2, and 9 is a light-shielding electrode. Usually, in a liquid crystal display device formed with a thin film transistor using p-3i in the channel portion 4, the light shielding electrode 9 is not formed in many cases.

これはp−8iはa−8i:Hに比べて光で発生する電
流が小さいため設けていないのである。これは、現在の
用途が対角寸法がわずか2〜3インチのポケットテレビ
に限定されているためである。これが、大型の液晶装置
や強力な光源を用いる透過型のプロジエクシオン表示装
置に使用する際には9のオフ電流の仕様はきびしく遮光
電極は不可欠となる。
This is because p-8i is not provided because the current generated by light is smaller than that of a-8i:H. This is because current applications are limited to pocket televisions with diagonal dimensions of only 2 to 3 inches. When this is used in a large liquid crystal device or a transmission type display device using a powerful light source, the off-state current specification of 9 is strict and a light-shielding electrode is indispensable.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第2図の上記従来技術では9の遮光電極および7.10
のコンタクト電極により4のチャネル層7の光照射を遮
へいする効果は十分認められる。
In the prior art shown in FIG. 2, 9 light-shielding electrodes and 7.10
The effect of shielding the channel layer 7 from light irradiation by the contact electrode 4 is sufficiently recognized.

しかしながら、従来技術を用いた遮へい電極構造では、
新たに次の様な問題が起る。通常、第2図の構造のトラ
ンジスタでは、ソース・ドレイン間の距i1(第2図の
La)は5〜20μm、8の絶縁膜の厚さtFは二1μ
mである。そのため9の遮光電極を設けたことで、新た
にドレイン・ソース間容量Cos。
However, in the shielded electrode structure using conventional technology,
The following new problems arise. Normally, in a transistor having the structure shown in FIG. 2, the distance i1 between the source and drain (La in FIG. 2) is 5 to 20 μm, and the thickness tF of the insulating film 8 is 21 μm.
It is m. Therefore, by providing 9 light-shielding electrodes, a new drain-source capacitance Cos.

esc+Coc  2  tp が生じる。ここで、esc 、 Cocはそれぞれソー
スと遮光電極、Cocはドレインと遮光電極との容量、
εは8の絶縁膜の誘電率である。このようなCosが生
ずると、11の表示電極の電位が7のソース・コンタク
ト電極に接続された他の画素を駆動する信号線を伝搬す
るパルス状の信号電圧ΔVsとして電圧変動するクロス
トークが生ずる。そのため、液晶に印加する電圧が変動
する、ノイズが生ずる等で画質が低下するという問題が
生ずる。
esc+Coc 2 tp occurs. Here, esc and Coc are the capacitances of the source and light-shielding electrodes, respectively, and Coc is the capacitance of the drain and light-shielding electrodes.
ε is the dielectric constant of the insulating film of 8. When such Cos occurs, crosstalk occurs in which the potential of the display electrode No. 11 changes as a pulsed signal voltage ΔVs propagating through the signal line that drives other pixels connected to the source contact electrode No. 7. . Therefore, problems arise in that the voltage applied to the liquid crystal fluctuates, noise occurs, and image quality deteriorates.

第3図の構造の薄膜トランジスタの問題は以下の通りで
ある。クロストークについては第2図の構造同様、厚さ
tp(〜1μm)を通じての容量の問題が起る。その他
に、多結晶シリコン特有の問題が発生する。これは、出
願人本人が第3図の構造の薄膜トランジスタを作製した
新たに得られた知見である。p−Siを用いた薄膜トラ
ンジスタは、a−3i:Hに比べて膜中に結晶成分が含
まれており、その移動度が10〜100倍程度大きい、
そのためオン電流が大きくなるという利点がある。しか
し、このp−8iはその製造温度がa−3i : H+
7)300℃に比べて600℃と高い。
The problems with the thin film transistor having the structure shown in FIG. 3 are as follows. As for crosstalk, as in the structure shown in FIG. 2, a capacitance problem occurs through the thickness tp (~1 μm). In addition, problems unique to polycrystalline silicon occur. This is a new finding obtained by the applicant himself who produced a thin film transistor having the structure shown in FIG. Thin film transistors using p-Si contain crystalline components in the film compared to a-3i:H, and their mobility is about 10 to 100 times higher.
Therefore, there is an advantage that the on-state current becomes large. However, the manufacturing temperature of this p-8i is a-3i: H+
7) Higher temperature at 600°C compared to 300°C.

そのために、膜中のSiの欠陥(ダングリングボンド)
に水素を置換してその欠陥密度を膜形成時に下げる方法
は水素が400℃以上ではシリコンから離脱してしまう
ために容易にとれない。そのために、しきい値電圧がp
−Siの素子ではa−8i :Hの素子に比べて2倍以
上高く、電源電圧を上昇させてしまうという欠点がある
。そのために、通常の製造方法では400’C以上の製
造工程終了後に、例えば、第3図の素子をプラズマ水素
の放電中にさらすことでしきい値電圧を低くできる。第
3図の素子の製造工程中の最後の400℃以上の工程は
、7および10のコシタクト電極と5及び6のリンの高
濃度半導体層のコンタクトを良好に行なわせるためのア
ニール工程である。第3図の9の遮光電極は7および1
oと同じ工程で形成した、例えばAQおよびその合金で
ある。出願人本人が第3図の素子を製造し、プラズマ水
素処理を行った所、9の遮光電極のある素子はしきい値
電圧は下がらず、9のない素子はしきい値電圧が半減す
るという事実が判明した。これは水素が9の遮光電極を
通過せず4のチャネル層に水素が到達しないためである
。プラズマ水素処理を行った後に9の遮光電極を別な工
程で形成すれば問題はないが、これでは製造工程が増加
して、製造コストが上がるという欠点が生ずるという問
題がある。
Therefore, Si defects (dangling bonds) in the film
The method of substituting hydrogen with hydrogen to lower the defect density during film formation is not easy to use because hydrogen separates from silicon at temperatures above 400°C. Therefore, the threshold voltage is p
The -Si element has a disadvantage that it is more than twice as high as the a-8i:H element, increasing the power supply voltage. To this end, in a normal manufacturing method, the threshold voltage can be lowered by, for example, exposing the element shown in FIG. 3 to plasma hydrogen discharge after the manufacturing process is completed at 400'C or higher. The final step at 400° C. or higher in the manufacturing process of the device shown in FIG. 3 is an annealing step for making good contact between the cositact electrodes 7 and 10 and the high-concentration phosphorus semiconductor layers 5 and 6. The light-shielding electrode 9 in Figure 3 is 7 and 1.
For example, AQ and its alloy are formed in the same process as o. When the applicant himself manufactured the device shown in Figure 3 and subjected it to plasma hydrogen treatment, the threshold voltage of the device with the light-shielding electrode 9 did not decrease, but the threshold voltage of the device without the 9 was halved. The facts have been revealed. This is because hydrogen does not pass through the light-shielding electrode 9 and does not reach the channel layer 4. There is no problem if the light-shielding electrode 9 is formed in a separate process after the plasma hydrogen treatment, but this increases the number of manufacturing steps and increases the manufacturing cost.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、遮光電極をチャネル方向に分割する、ある
いはスリットを入れる形状にして、特に、チャネル半導
体層で光により電流の発生するソース及びドレイン層と
チャネル層との接合部分を遮光させる構造にすることで
達成される。
The above purpose is to create a structure in which the light-shielding electrode is divided in the channel direction or has a slit shape to shield the junction between the source and drain layers and the channel layer, where current is generated by light in the channel semiconductor layer. This is achieved by

〔作用〕[Effect]

遮光電極をチャネル状に分割してチャネル上で遮光電極
を分割することでソースドレイン間の容量は低減できる
。また遮光電極はソース及びドレイン層とチャネル層と
の接合部には少なくとも遮光を行っているため光による
発生電流は全面遮光した場合と同等である。又、チャネ
ル上に遮光電極のないスリット部分があるため、多結晶
シリコ。
By dividing the light-shielding electrode into channel shapes and dividing the light-shielding electrode on the channel, the capacitance between the source and drain can be reduced. Further, since the light-shielding electrode blocks light at least at the junction between the source and drain layers and the channel layer, the current generated by light is equivalent to when the entire surface is shielded. Also, since there is a slit part on the channel without a light-shielding electrode, polycrystalline silicon is used.

ンを用いた薄膜トランジスタでもプラズマ水素化処理を
行っても、水素がこのスリット部分から進入して遮光電
極が全面にある場合に比べて、しきい値電圧を低くでき
る。
Even if a plasma hydrogenation treatment is performed on a thin film transistor using hydrogen, hydrogen enters through the slit portion, and the threshold voltage can be lowered than when the light-shielding electrode is on the entire surface.

〔実施例〕 以下、本発明の一実施例を第1図の断面図により説明す
る。1は基板で透過型の液晶表示装置の場合はガラスあ
るいは石英の透明絶縁性基板を用いる。2はゲート電極
であり、自己整合型のMO3型トランジスタの場合はp
−5iであり、これはプラズマ水素中に発生した水素イ
オンや水素のラジカルを通過させ得る。4はp−5iの
チャネル層で不純物を含まないノンドープ層である。5
及び6はそれぞれp−8iに例えばイオン打込みでリン
等を打ちこんだ低抵抗のドレイン及びソース層である。
[Example] Hereinafter, an example of the present invention will be described with reference to the sectional view of FIG. Reference numeral 1 denotes a substrate, which is a transparent insulating substrate made of glass or quartz in the case of a transmission type liquid crystal display device. 2 is the gate electrode, and in the case of a self-aligned MO3 transistor, p
-5i, which allows hydrogen ions and hydrogen radicals generated in plasma hydrogen to pass through. 4 is a p-5i channel layer, which is a non-doped layer containing no impurities. 5
and 6 are low resistance drain and source layers in which, for example, phosphorus or the like is implanted into p-8i by ion implantation.

本構造素子の場合、4,5.6は同一形成のp−Siを
用い、2は別工程で形成する。
In the case of this structural element, p-Si is formed in the same manner for 4, 5.6, and 2 is formed in a separate process.

もちろん、2も5.6同様リンをイオン打込みして低抵
抗化しである。3はゲート絶縁膜である。
Of course, like 5.6, phosphorus ions are implanted in 2 to lower the resistance. 3 is a gate insulating film.

7はソースコンタクト電極、8は保護絶縁膜、9は遮光
電極、10はドレインコンタクト電極である。7,9及
び10は、例えばAQ及びその合金あるいはクロム等で
同一金属膜として形成し、ホト・エツチング工程で分離
形成する。11はITOのような透明電極を用いた表示
電極である。図中のt、pe Lo+ Lt+ LZは
各部の寸法の厚さ、長さを表わす記号である。本発明の
特徴は9の遮光電極がチャネル方向に分割され、4のチ
ャネル層上に遮光電極の無い長さLlの領域がある遮光
電極構造にある。第4図に本構造素子に光を図中の矢印
の様に照射した場合の光強度と素子のオフ電流の関係を
示す。本特性図は出願人本人が本発明構造の素子を作製
し測定したものである。白丸(0)及び実線は遮光電極
のない素子、三角(Δ)及び実線は本発明構造の素子で
、Lo=5μm、L2=10μm、Lz=40μmで素
子のチャネル長50μm、チャネル幅は10μmである
。黒丸(・)及び破線はLx=Oμmで全面に遮光電極
のある従来型の遮光素子構造素子である。オフ電流はソ
ース・ドレイン間電圧5V、ゲート電圧OVで測定、し
たものである。同図で明らかな様に、本発明の素子は全
面遮光した素子と同等の遮光能力があることがわかる。
7 is a source contact electrode, 8 is a protective insulating film, 9 is a light shielding electrode, and 10 is a drain contact electrode. 7, 9, and 10 are formed as the same metal film of AQ, its alloy, or chromium, for example, and are separated by a photo-etching process. 11 is a display electrode using a transparent electrode such as ITO. In the figure, t, pe Lo+ Lt+ LZ are symbols representing the thickness and length of each part. The present invention is characterized by a light-shielding electrode structure in which the light-shielding electrodes 9 are divided in the channel direction, and there is a region of length Ll on the channel layer 4 where there is no light-shielding electrode. FIG. 4 shows the relationship between the light intensity and the off-state current of the element when the structural element is irradiated with light in the direction of the arrow in the figure. This characteristic diagram is obtained by the applicant himself who produced and measured an element having the structure of the present invention. The white circle (0) and the solid line are the device without a light-shielding electrode, and the triangle (Δ) and the solid line are the device with the structure of the present invention, where Lo = 5 μm, L2 = 10 μm, Lz = 40 μm, the channel length of the device is 50 μm, and the channel width is 10 μm. be. The black circle (.) and the broken line indicate a conventional light-shielding element structure with Lx=0 μm and a light-shielding electrode on the entire surface. The off-state current was measured with a source-drain voltage of 5V and a gate voltage of OV. As is clear from the figure, it can be seen that the element of the present invention has the same light-shielding ability as a completely light-shielded element.

また、図中に示した3つの構造素子のプラズマ水素処理
後のしきい値電圧は、遮光の無い素子で6v、本発明素
子で6.5V、全面遮光した従来構造の素子で12Vで
あった。このことはL1=Oμmにして全面遮光した素
子では水素が4のチャネル層に到達せずしきい値が下が
らなかったためである。又、遮光電極によるソース・ド
レイン間容量は次の様に求められる。LL =Oμmの
全面遮光の場合は、ソース層と遮光電極、ドレイン層と
遮光電極の容量の直列接続になり   tp となる。ここでεOxは8の絶縁膜の誘電率である。
In addition, the threshold voltages of the three structural elements shown in the figure after plasma hydrogen treatment were 6 V for the element without light shielding, 6.5 V for the element of the present invention, and 12 V for the element with the conventional structure completely shielded from light. . This is because in the device in which light was completely shielded by setting L1=0 μm, hydrogen did not reach the channel layer 4 and the threshold value did not decrease. Further, the source-drain capacitance due to the light-shielding electrode is determined as follows. In the case of total light shielding with LL = O μm, the capacitances of the source layer and the light shielding electrode, and the drain layer and the light shielding electrode are connected in series, resulting in tp. Here, εOx is the dielectric constant of the insulating film of 8.

Llのスリットのある本発明素子では a CL・□・t。In the device of the present invention with a slit of Ll a CL・□・t.

I C2=□ ε a Cs +□・t3 となる。ここでεaは空気の誘電率で、tsは遮光電極
の厚さである。ここで、それぞれεox=4×8.85
X10−” (F/am)、tp=IX10−’国、L
o=5X10″″’cm、 εa=8.85X10″″
1番(F/am) 、 ts=o、5 X 10−’c
m、 Ll =4 X10″″3a11とした本発明構
造素子では、C1=0.885(PF)、Cz=O,0
O11(PF)となり遮光電極によるソース・ドレイン
間容量は2桁以上低減できる。以上の様に本発明を用い
た素子構造では遮光の効果がある上に、しきい値電圧が
低く、さらにソース・ドレイン間容量の小さいクロスト
ークの小さな素子が形成されるため、光照射時でも鮮明
画像特性を持つ液晶表示装置が実現できる。
I C2=□ ε a Cs +□・t3. Here, εa is the dielectric constant of air, and ts is the thickness of the light shielding electrode. Here, each εox=4×8.85
X10-” (F/am), tp=IX10-’Country, L
o=5X10''''cm, εa=8.85X10''''
No. 1 (F/am), ts=o, 5 X 10-'c
In the structural element of the present invention where m, Ll = 4 X10''''3a11, C1 = 0.885 (PF), Cz = O, 0
O11 (PF), and the source-drain capacitance due to the light-shielding electrode can be reduced by more than two orders of magnitude. As described above, the device structure using the present invention not only has a light shielding effect, but also has a low threshold voltage, and also has a low source-drain capacitance and low crosstalk, so even when irradiated with light, A liquid crystal display device with clear image characteristics can be realized.

また、本発明の素子が従来の全面遮光の素子同様の遮光
特性を持つのは光による電流の発生する領域が第1図の
12の領域のようにL2よりも狭い領域にあるためであ
る。この領域の幅は、5,6のソース・ドレイン層のリ
ンの濃度や今回はノンドープ層であるが、4のチャネル
層の濃度により変化するのでその濃度に応じてLo、L
xの長さを調整する必要がある。
Furthermore, the reason why the element of the present invention has the same light-shielding characteristics as the conventional completely light-shielding element is because the region where a current due to light is generated is narrower than L2, such as the region 12 in FIG. 1. The width of this region varies depending on the phosphorus concentration of the source/drain layers 5 and 6, and the concentration of the channel layer 4, which is a non-doped layer in this case, so depending on the concentration, Lo and L
It is necessary to adjust the length of x.

本発明の別の実施例を第5図の断面図に示す。Another embodiment of the invention is shown in cross-section in FIG.

本構造素子はスタガ構造のMO8型トランジスタであり
1通常4のチャネル層をa−8i:Hの半導体層で形成
している。本構造の発明の特徴は第1の発明同様遮光電
極を分割してスリット状にしていることで遮光電極のソ
ース・ドレイン間容量を減らしてクロス・トークを小さ
くしたことである。但し、a−5i:Hで形成する場合
は、形成温度が400℃以下であるため、4のチャネル
層には腹形成時に混入した水素が離脱せず残っているた
め1本発明素子と全面遮光した従来構造素子ではしきい
値電圧の差はない。
This structural element is an MO8 type transistor with a staggered structure, and one channel layer (usually four) is formed of an a-8i:H semiconductor layer. The feature of the invention of this structure is that, like the first invention, the light-shielding electrode is divided into slit shapes to reduce the source-drain capacitance of the light-shielding electrode and thereby reduce crosstalk. However, when forming with a-5i:H, since the formation temperature is 400°C or lower, the hydrogen mixed in during the formation of the antinode remains in the channel layer 4 without being released, so it is difficult to form the device of the present invention and the entire light shielding. There is no difference in threshold voltage in conventional structural elements.

本発明の実施例ではソース及びドレイン層にリンを打込
んだNチャネル型のMO8型素子を示したが、これはも
ちろんボロン等を打込んだPチャネルMO8にも適用で
きる。また、半導体層としてもアモルファスシリコン、
多結晶シリコンのみを用いて説明したが、これも光の影
響の大きい他の半導体を用いた素子にも同様に適用でき
る。
In the embodiment of the present invention, an N-channel MO8 type device in which phosphorus is implanted into the source and drain layers is shown, but this can of course also be applied to a P-channel MO8 device in which boron or the like is implanted. In addition, amorphous silicon can also be used as a semiconductor layer.
Although the description has been made using only polycrystalline silicon, this can be similarly applied to elements using other semiconductors that are significantly affected by light.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、従来の遮光構造を持った薄膜トランジ
スタと同等の遮光効果を持ちながら、遮光電極が分割さ
れスリット状になっているため、遮光電極によるソース
・ドレイン間容量が従来の全面遮光構造の素子に比べて
100分の1以下に低減できる上に、例えばチャネル層
をp−Siで形成した素子では水素処理によりしきい値
電圧も効果的に下げられるという利点を持ち、光照射時
にもオフ電流が小さく、クロストークが遮光電極があっ
ても小さくできるという効果がある。
According to the present invention, while having the same light-shielding effect as a thin film transistor with a conventional light-shielding structure, the light-shielding electrode is divided into slits, so that the source-drain capacitance due to the light-shielding electrode is lower than that of the conventional full-thickness structure. In addition to being able to reduce the threshold voltage to less than 1/100 of that of other devices, for example, devices whose channel layer is made of p-Si have the advantage that the threshold voltage can be effectively lowered by hydrogen treatment, and even during light irradiation. The off-state current is small, and crosstalk can be reduced even with a light-shielding electrode.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の液晶表示装置駆動用の薄膜
トランジスタの断面図、第2図は従来の薄膜トランジス
タの断面図、第3図は第2図とは異なる従来の構造の薄
膜トランジスタの断面図、第4図は本発明構造の薄膜ト
ランジスタと従来例との光によるオフ電流特性との比較
図、第5図は本発明の一実施例である。 1・・・基板、2・・・ゲート電極、4・・・チャネル
層、5# 1 の 光H射 /−J)籾 2 −−−  クシート電極 4ン”  −−−−h才ノし漫 5−−− トイ] 乙−−−/−;t4 q−y電極 #Z図 第3図 第 4 口 光域   (1,) 昇 5 口
FIG. 1 is a cross-sectional view of a thin film transistor for driving a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional thin film transistor, and FIG. 3 is a cross-sectional view of a thin film transistor with a conventional structure different from that in FIG. 4 is a comparison diagram of off-current characteristics due to light between a thin film transistor having the structure of the present invention and a conventional example, and FIG. 5 is a diagram showing an example of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate electrode, 4...Channel layer, 5#1 light radiation/-J) Rice grains 2---Cushion electrode 4''---h 5--- Toy] B---/-; t4 q-y electrode #Z diagram Figure 3 4 mouth light area (1,) rise 5 mouth

Claims (1)

【特許請求の範囲】[Claims] 1、透明基板上にゲート電極、ソース電極及びドレイン
電極を有する薄膜トランジスタを形成し、これを用いて
液晶を動作させる液晶表示装置において、少なくとも前
記薄膜トランジスタを構成する電流経路上にある半導体
層のソース領域とチャネル領域の接合部及びドレイン領
域と前記チャネル領域との接合部上遮光電極を持ち、少
なくともその遮光電極は前記チャネル領域上の1部では
切断されていることを特徴とする液晶表示装置。
1. In a liquid crystal display device in which a thin film transistor having a gate electrode, a source electrode, and a drain electrode is formed on a transparent substrate and the thin film transistor is used to operate a liquid crystal, a source region of a semiconductor layer located on a current path constituting at least the thin film transistor. A liquid crystal display device comprising a light-shielding electrode on a junction between a drain region and a channel region, and a light-shielding electrode on a junction between a drain region and the channel region, and at least a portion of the light-shielding electrode above the channel region is cut off.
JP62114672A 1987-05-13 1987-05-13 liquid crystal display device Pending JPS63280222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62114672A JPS63280222A (en) 1987-05-13 1987-05-13 liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62114672A JPS63280222A (en) 1987-05-13 1987-05-13 liquid crystal display device

Publications (1)

Publication Number Publication Date
JPS63280222A true JPS63280222A (en) 1988-11-17

Family

ID=14643716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62114672A Pending JPS63280222A (en) 1987-05-13 1987-05-13 liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS63280222A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
US6750475B1 (en) * 1999-05-18 2004-06-15 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method

Similar Documents

Publication Publication Date Title
CN1122314C (en) Thin-film semiconductor device
US5886364A (en) Semiconductor device and process for fabricating the same
JPH0132672B2 (en)
JP3072326B2 (en) Semiconductor single crystal thin film substrate light valve device and method of manufacturing the same
US7189997B2 (en) Semiconductor device and method for manufacturing the same
US10361229B2 (en) Display device
US6982194B2 (en) Semiconductor device and method for manufacturing the same
KR20080003180A (en) LCD and its manufacturing method
US6043113A (en) Method of forming self-aligned thin film transistor
JPH08160464A (en) Liquid crystal display device
JPS63280222A (en) liquid crystal display device
JP2003243658A (en) Semiconductor device, electro-optical device, electronic device, method of manufacturing semiconductor device, method of manufacturing electro-optical device
JPH0864830A (en) Active matrix substrate and method of fabrication thereof
JPH0212031B2 (en)
JPH04186737A (en) Insulation gate type field effect semiconductor device and manufacture thereof
JPH05235398A (en) Thin film optical sensor
JP3647384B2 (en) Thin film semiconductor device, manufacturing method thereof, and display panel
JP3091883B2 (en) Light valve device and semiconductor device
JPH07159809A (en) Liquid crystal display
JPH0695157A (en) Liquid crystal display device
JPH08242001A (en) Production of thin-film transistor
JP3113914B2 (en) Semiconductor single crystal thin film substrate light valve device
JP2002141359A (en) Semiconductor device and its manufacturing method
JP2005064123A (en) Thin film transistor and indicating device
JP3259769B2 (en) Thin film integrated device