JPS63268033A - data processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing technology and a technology that is particularly effective when applied to an instruction system in a program control system. This article relates to techniques that are effective for use in processor instruction systems.

[Conventional technology]

Conventionally, in Zilog's GZSO series microcomputers, as shown in FIG.
, R3B, and can perform task processing using any one register set. With this, for example, when one task using register set R8A is completed, it is possible to immediately move on to processing another task by switching the register set from R8A to R8B while leaving the contents of the register unchanged. Furthermore, when returning to the original task after the task processing is finished, by switching to register set R8, the contents of the previous task remaining in register set R8A can be inherited and executed as is. . Therefore, when changing a task, there is no need to save registers, etc., and the execution speed is high.

However, in a microprocessor having a plurality of register sets, when transitioning from one task processing to another, it may be necessary to pass arguments and execute a new process, such as in a subroutine call. However, if the register set is completely switched as shown in FIG. 7, there is a problem in that it is difficult to pass arguments.

On the other hand, RI 5C (R
Educed In5truction Set Co
mputer: A computer that has only basic simple instructions has multiple registers with a certain number of registers overlapping each other, as shown in Figure 8.
8A.

R8B, R8C, . . . are provided. Therefore, it is easy to pass arguments when jumping to a subroutine. However, if multiple register sets always overlap with each other, when a task is migrated, the overlapping registers cannot be used (in cases where it is possible to pass arguments, etc.). This has the disadvantage that the number of usable registers is limited.

[Problem that the invention seeks to solve]

SUMMARY OF THE INVENTION An object of the present invention is to improve the flexibility when switching between multiple register sets and to improve the execution speed of a data processing system.

Other objects and novel features of this invention will become apparent from the description of this specification and the accompanying drawings.

[Failure to solve the problem]

A summary of typical inventions disclosed in this application is as follows.

In other words, in a data processing system that has multiple register sets, we created a new instruction that specifies a register and transfers its contents to a register in another register set when switching register sets, and it is possible to implement this in hardware. [Operation] According to the above-described means, register sets can be switched with passing of arguments, etc., and register sets can be switched without passing of arguments, etc. As a result, high-speed task switching and subroutine calls can be achieved, improving flexibility when switching register sets.

The above objective of improving the execution speed of the system can be achieved.

〔Example〕

FIG. 1(3) to FIG. 103) show an example of the format of a register set switching instruction according to the present invention.

The format shown in FIG. 1 is suitable for an instruction to switch to an adjacent register bank among a plurality of register sets (hereinafter referred to as register banks). Operation 1 code specification field O
The PI contains a code for incrementing or decrementing the register bank number. Field R following operation code specification field OPI
is a field provided to indicate whether or not register contents are transferred, and is composed of 1 bit. If this field R is set to 0'', when switching from a certain register bank (for example, BNI) to the previous or next register bank BNi-1 or BN 1-1-1, the register bank BNi Bank switching is performed without transferring the contents of all registers in the bank.

On the other hand, if field R is set to ``1''.

This means that the contents of the register designated by the subsequent register designation field Rn-1ist are switched and delivered to the corresponding register in register bank BNi-1 or BNi+1 of t[.

Although not particularly limited, in this embodiment, assuming that each register bank is composed of 16 registers, the register specification field Rn-1ist is composed of 16 bits, and the contents are transferred in bit correspondence. It is now possible to specify the register that should be used. For example, in the example shown in Figure 1 (a), numbers 1 and 4 in the register bank in use are
This indicates that the contents of the numbered registers R1 and R4 should be delivered to the numbered registers 1 and 4 in the register bank after switching.

Use this instruction to register from register bank BNI to BN2.
The effect when switching (incrementing) to
This is shown in Figure (2). However, in this case, an instruction (denoted as IBNR) for incrementing the bank number is used. To return the register bank from BN2 to BN1-, an instruction (denoted as DBNR) for decrementing the bank number may be used, and the settings of field R and register designation field Rn-1ist may be shifted in the same manner as above.

Next, the instruction format shown in FIG. 1031 will be explained. This format is suitable for an instruction (denoted as CBNR) that switches the register bank in use to a register bank in a remote (non-adjacent) location.

This CBNR instruction has field R and register specification field Rn-1is of the instruction format shown in FIG. 1 (5).
t, there is an immediate data specification field Imm for specifying the number of the register bank after switching.
The structure is such that

With this CBNR instruction, for example, register bank B
Switching from N'O to BN2 is performed.

Moreover, at this time, as shown in FIG. 3(B), it is possible to specify any register in the bank, such as registers R1 and R4, and transfer their contents, or to switch register banks without transferring the contents at all. .

Whether or not to transfer is determined by the information in field R, and the contents of the instruction are determined by the information in operation code designation field OPZ.

Although not particularly limited, in this embodiment, the immediate data designation field 1 mm has a length of 8 bits in relation to the operation word length. by this,
It can support up to 256 register banks.

When switching register banks using this CBNR instruction, it is easier to return to the original register bank by memorizing the register pan number before switching in a stack area or the like. Therefore, in that case, an instruction (PB
NR) by bringing the original register bank number from the stack area, the above CBN
The original register bank can be restored without using the R instruction.

Next, an explanation will be given of the instruction format shown in FIG.
-1ist. No dedicated field R is provided to indicate whether or not register contents are to be transferred. Information regarding whether or not the contents of the register are to be delivered is included in the operation code specification field OP3. Although not particularly limited, the operation code designation field OP3 is composed of 8 bits.

By executing this instruction, the register set is switched as shown in FIG. 3 above.

Next, the instruction format shown in FIG. 1(D) will be explained. This format consists of an operation code specification field OP4, an immediate data specification field Imm, and a register specification field Rn-1is.
It consists of t. A dedicated field R is not provided to indicate whether or not register contents are transferred. Information regarding whether or not the register contents are to be delivered is included in the operating code specification field OP4.

By executing this instruction, the register set is switched as shown in FIG. 3 (0).

Next, FIG. 1 (instruction format shown in D) K will be explained. This format consists of an operating date code specification field OP5, a transfer/presence specification field R, an immediate data specification field Imm, a transfer source register specification field Rn-1ist (source), and a transfer destination register specification field Rn-1ist (destination). It consists of Transfer destination register specification field Rn-1ist (testation)
is 16, corresponding to the number of registers in the register bank.
It is divided into fields RLO to RL15. Each field RLO to RL15 is allocated an area of 4 bits to indicate the register number of the transfer destination. For example, field RL2 specifies the seventh register R7 in the register bank ahead of fL. Further, field RL15 specifies the 12th register RL12 in the transfer destination register bank. An example of the case where the register bank is switched based on the instruction shown in FIG. 1(E) is shown in FIG. It is specified by the information in Rn-1ist (source).The register bank number BN2 after switching is specified by the information in the immediate data specification field Imm.
By using the instruction format shown in I, it is possible to transfer between arbitrary register banks and between arbitrary registers.

Next, the command format shown in FIG. 4 [F] will be explained. This format consists of an operation code specification field OP6, an immediate data specification field Imm, and a transfer source register specification field Rn.
-1ist (source) and a transfer destination register specification field Rn-1ist' (destination field). Transfer destination register specification field Rn-1is
Unlike the format shown in FIG. 1(D), t' (destination) is divided into two fields RLa and RLb.

Each field RLa, RLb has 4 bits assigned to specify the register number within the register bank after switching. This instruction format is particularly useful when the number of passed registers is limited to two or less. This is because the total bit length of the instruction format can be shortened. For example, the transfer destination register specification field Rn-1ist (destination) in Figure 8g1 ■
is made up of 64 bits, but the destination register designation field Rn-1ist' (destination) in FIG. 1n can be made up of only 8 bits.

In addition, in the format of FIG.
It needs to be included within. That is, the transfer destination of register R2 specified by transfer source register designation field Rn-1ist (source) is specified by field RLa, and the transfer destination of register R15 is specified by register RLb. 1st
An example of the case where register banks are switched based on the instruction shown in FIG. 3(F) is shown in FIG. 3(C) above.
.

Next, an explanation will be given of the instruction format shown in FIG.
-1ist (source). Figure 1 (G
An example of a case where the register bank is switched based on the instruction shown in ) is shown in FIG. 3 (■). In this instruction format, no destination register specification field is provided. When the register bank is switched, if there are registers to be handed over, the registers RO with the lowest number in the new register bank BN2 are designated as registers. Such designation order is defined by information in the operation code designation field OPT.

Next, an example of the hardware configuration of a microprocessor that makes it possible to execute a register bank switching instruction configured in the above format will be described with reference to FIG.

The microprocessor of this embodiment includes a control section using a microprogram control system. That is, an LSI chip 1 constituting a microprocessor is provided with a micro ROM (read only memory) 2 in which a micro program is stored. The micro ROM 2 is accessed by the micro address decoder 5,
The microinstructions making up the microprogram are read out in sequence.

The microaddress decoder 5 is supplied with an address generated by the microaddress generation circuit 4 based on the operation code of the macroinstruction fetched into the instruction register 3. By decoding this, the first instruction of a series of microinstructions that executes that macroinstruction is read, and various temporary registers REG
Control signals are generated for the execution unit 6, etc., which includes I to REGn, a data buffer DB, an arithmetic logic unit ALU, and the like. The second and subsequent microinstructions in a series of microinstructions corresponding to a macroinstruction are supplied with the code of the next address field of the microinstruction that was just read out to the microaddress decoder 5. It is read out based on the next address and the address from the microaddress generation circuit 4.

In this way, the execution unit 6 is controlled by the control signal formed by reading out the series of microinstructions,
For example, a macro instruction such as an addition instruction indicated by ADD is executed.

In this embodiment, for example, 16 register banks BNO
A memory access control circuit 7 having a function of controlling a general-purpose register group 12 and a control register group 11 consisting of BN15 is provided. The above-mentioned 16 register banks BNO to BN15 are each 32-bit long register 0, as shown in FIG. 2, although not particularly limited.
~15 growls. The control register 11 is provided with a status register SR, a stack pointer SP, a bank number register bank that holds the number of the register bank currently in use, and the like. In this embodiment, the general-purpose register group 12 and the control register group 11 consisting of the register banks BNO-BN15 are constituted by RAM (random access memory),
It is connected to a data buffer DB in the execution unit 6 via an internal bus 10.

The instruction register 3 is composed of a FIFO (first-in...7.earthed-out) memory, and the macro instructions stored in the external memory are read in byte units by the memory access control circuit 7 accessing the address bus 8. is read out via the data bus 9 to the FIF
It is supplied to an instruction register 3 consisting of O memory. In this way, a plurality of operation codes and operands can be loaded into the instruction register 3 in advance.

As mentioned above, the microprocessor in this example has
Each task can be processed using one of the 16 register banks BNO to BN15.

In the instruction register 3 of the microprocessor, the information shown in Figure 1 (
When a register bank switching instruction IBNR or DBNR as shown in (to) is received, the corresponding microinstruction is read from the microROM 2. Then, the memory access control circuit 7 is controlled by the microcode, and for example, if the register bank that the memory access control circuit 7 was using until then was BNi, the BN
Switching is performed so that bank ii-1 or BNi-1 is used for subsequent processing. And at that time,
If the bit of field R is @1”, Rn-1ist
For the register designated by , the contents are transferred to a corresponding register in another bank or a specially designated register. Also.

Don't forget to change the bank number in the bank number register set.

On the other hand, when a register bank switching instruction CBNR such as CB in FIG. The data is written to the bank number register BNR, and the bank number is changed. At the same time, the specified register will be transferred. At the same time, the bank number in use, which had been stored in the bank number register BNR up to that point, is stored in the stack area of the external memory together with the contents of the program counter and the like.

Then, when the register bank switching instruction PBNR is loaded, the original register bank number saved from the stack area indicated by the stack pointer in the control register group 11 is read out and loaded into the bank number register BNR.

At the same time, the banks in use in the general-purpose register group 12 are switched and necessary register contents are transferred.

Therefore, by using the above instruction CBNR, it is possible to easily jump from the main routine to the subroutine by passing arguments etc. when calling a subroutine and execute other task processing, and at the same time, by using the PBNR instruction. This makes it possible to quickly return to the original position of the main routine and continue the original processing.

FIG. 5 shows another example of the configuration of a microprocessor capable of executing a register bank switching instruction according to the present invention.

The difference from the microprocessor shown in FIG. 4 is the control register group (1') configuration means. The control register group 11 in FIG. 4 is provided in the RAM, but the control register group CR in FIG. 5 is composed of a plurality of registers as dedicated storage means. These registers are similar to the temporary registers REGI~REGn with the same configuration.
It can be thrown into execution unit 6.

FIG. 6 shows another configuration example of a microprocessor that enables execution of the register bank switching instruction according to the present invention.

The difference from the microprocessor shown in FIG. 5 is the configuration means for register banks BNO to BN15. Fifth
Register banks BNO-BN15 in the figure are RAM
The register banks BNO to BN15 in FIG. 6 are comprised of a plurality of registers as dedicated storage means. These registers can be provided within the execution unit 6 in the same way as the temporary registers REGI-REGn having the same configuration. By providing the register banks BNO-BNI5 within the execution unit, there is no need to provide the data buffer DB within the execution unit for holding the contents of the register banks BNO-BN15. Furthermore, instead of the memory access controller 1, a register access controller 7' is provided.

Note that the register bank switching instruction proposed by the present invention is not limited to the formats shown in FIGS. Needless to say, it is possible to change the capacity of RAMH as a general-purpose register group and the number of registers in each register bank BNi.

〔effect〕

According to the present invention, in a microprocessor having multiple register sets, a new instruction is created to specify a register and pass its contents to a register in another register set when switching register sets. It is now possible to switch register sets with passing arguments, etc., or without passing arguments, etc., and this enables high-speed task switching and subroutine calls. Improved flexibility when switching register sets,
This has the effect of increasing the execution speed of the system.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the register banks BNO-BN15 may be provided outside the microprocessor 1. Further, in the above explanation, the invention made by the present inventor was mainly applied to a microprocessor, which is the field of application that is the background of the invention, but the invention is not limited thereto.
It can be used in general program-controlled data processing systems such as computers and minicomputers.

[Brief explanation of the drawing]

Figures 1 (3) to 1 (G is an explanatory diagram showing an example of the format of the register set switching instruction according to the present invention, and Figure 2 is
Figures 4 to 7 are explanatory diagrams showing examples of register bank configurations; FIG. 6 is a block diagram showing a configuration example of a microprocessor that can execute the register set switching instruction according to the present invention. FIGS. 7 and 8 are explanatory diagrams showing a register set switching method in a conventional microprocessor. It is. ALU... Arithmetic logic unit, REGI~RE Gn
...Temporary register, OP1 to OP7...Operation 1 code specification field, Rn-1ist...
・Register specification field, Imm...immediate data specification field, BNO to BN15...
Register set (register bank). Figure 1 (A) Figure 1 (8) Figure 1 CC) Figure 1 CD) OPt Imrn,'(
yt-/i5t: Figure 2

Claims (1)

[Claims] 1. It has a data processing function that specifies any register group among a plurality of register groups according to an instruction and performs predetermined data processing, and the above-mentioned instruction A data processing system comprising: information instructing switching to another register group; and information specifying one or more registers within the one register group. 2. Claim 1, wherein the instruction further includes information instructing to move the contents of the one or more registers to a register in the other register group.
Data processing system as described in Section. 3. The data processing system according to claim 2, wherein the instruction further includes information specifying a desired register within the other register group. 4. It has a plurality of register groups, is configured to execute a series of processes using any one register group according to a program, and has a register specification field that can specify a register in the register group. , a data processing system comprising an instruction for instructing switching from one register group to another register group. 5. The data according to claim 4, wherein the register specification field has the same number of bits as the number of registers in the register group, and is configured to specify registers in bit correspondence. processing system.