JPS63293638A - data processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data processing technology and a technology that is particularly effective when applied to instruction formats in program control systems. This article relates to techniques that are effective when used in configuration methods.

[Conventional technology]

Instructions for program-controlled systems include two-operand instructions that use two operands when executing instructions;
There are 1-operand instructions that use two operands and 0-operand instructions that do not require any operands. Among these, a two-operand instruction requires calculation of the effective address of the operand twice, and there have conventionally been two methods for configuring a two-operand instruction. One is.

This is a method of putting all the information necessary for calculating the operating code and two operands into one word (the unit for addressing an instruction) (Hitachi, Ltd., published September 1982, [Hitachi Micro Computer, SEMICONDUCTER DATA BOOK-
8/16-bit Microcomputer” pages 945-9
(See page 52).

[Problem that the invention seeks to solve]

When this instruction format is used, the operation code (
Since the information necessary to calculate the effective address of the operand and the operation code can be decoded at the same time, the execution speed of the two-operand instruction is fast. However, if the information necessary to calculate the two operands is included in the same word along with the operation code, the width of the operation specification section becomes narrower, resulting in a reduction in the number (types) of instructions.

In this case, to prevent a decrease in the number of instructions.

It is conceivable to increase the number of bits in the l word.

However, since the number of bits of information to be decoded at once also increases, the circuit scale of the decoder becomes extremely large.

On the other hand, as another example of a two-operand instruction configuration method, there is a method in which an operation specifying section and an operand specifying section are inserted into separate words and executed using a plurality of words. If you follow this command method.

Compared to a method in which an operation specification section and an operand specification section are placed in the same word, the field width of the operation specification section can be made larger, so there is an advantage that the number of instructions can be increased. Also, the number of bits of information that must be decoded at one time can be reduced.

The circuit scale of the decoder can be reduced.

However, the conventional method using multiple words
Alternatively, in a system of configuring a two-operand instruction, a word containing an operation specifying section, that is, an operation word, is followed by a word containing an operand specifying section.

Therefore, first, the operation word is decoded to find out that address calculation is required, and the first step is to decode the word including the operand specification part to calculate the effective address, and then fetch the operand based on the calculation result.

Furthermore, since the instructions are executed, there is a problem that the execution speed of the instructions is slow.

An object of the present invention is to provide an instruction format that allows the number of instructions (types of instructions) to be increased without reducing the instruction execution speed.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A summary of typical inventions disclosed in this application is as follows.

In other words, the instruction is divided into multiple words, and the first word contains the minimum information required to calculate the effective address of the operand, followed by a word containing the operation specification part. Allows operand effective address calculation and operand fetch to begin before decoding the word containing the part. Then, while performing this address calculation or operand fetching, the operation word is decoded so that the instruction can be executed immediately after the operand address calculation or operand fetching is completed.

[Effect]

According to the above-described means, the decoding of the word including the operation 17 specification part and the address calculation or operand fetch operation can be performed in parallel. Therefore, the execution speed of instructions requiring operands can be increased. Furthermore, since the instructions are divided into a plurality of words, the number of instructions can be increased, and furthermore, it is possible to limit the increase in the size of the decoder.

〔Example〕

FIG. 1 shows an example of an instruction format of a two-operand instruction when the present invention is applied to an instruction system in which 16 bits are the instruction reading unit.

That is, the microprocessor that executes the two-operand instruction of this embodiment uses 16 bits as a basic unit.

Therefore, the address for the instruction is also 16
Bit is the smallest unit. Inside the microprocessor, these 16 bits are always read simultaneously, so 1
The arrangement within 6 bits has no essential meaning. The minimum unit of such an instruction is called a word.

The two-operand instruction shown in FIG. 1 has a structure in which the first word at the beginning includes an operand specification section EAI in which information necessary to calculate the effective address of the first operand is encoded. The operand designation section EAI is composed of 8 bits, although this is not particularly limited.

The 8-bit code that constitutes the operand specification part EAI is
Although not particularly limited, 5 ICs are defined as shown in Table 1.

Table 1 However, in Table 1, P is an address pointer size designation bit; 0 indicates, for example, 32 bits, and 1 indicates 64 bits.

Rn is a register number designation pin), Disp is a displacement value, and Lit is a literal value, that is, an immediate value. SS indicates the bit configuration of the extension section 1, for example 01
16 bits, 10 32 bits, 11 64 bits.

In Table 1, for example, frame pointer relative seat displacement and stack pointer relative seat displacement are respectively an address mode with relative displacement from the frame pointer and an address mode with relative displacement from the stack pointer. show. Since the displacement value is 4 bits, these modes are applied when the displacement value is small. According to these modes, the displacement value is set in the operand specification section, so there is no need to set the displacement value in a portion such as the extension section.

According to the code structure in Table 1, the operands are determined as follows. For example, in stack pointer relative short displacement.

The operand consists of the contents at an address that is increased by the displacement value of the operand specification part with respect to the address value indicated by the stack pointer among the memory addresses.

In FIG. 1, the first word is provided with a class designation part CL, a mode designation part MD, and a size designation part SZI in addition to the operand designation part EAI. Class specification part CL
consists of the upper 5 bits of the 16 bits in this instruction, and the upper 5 bits are the only specific state (for example, all 11"
or °all “0”, etc.), this command is
Specifies that it is an operand instruction.

The mode designation part MD and size designation part SZI are as follows.

Each code is composed of 1 bit and 2 bits, and each code is defined as shown in Table 2, for example.

That is, the mode specifying section MD specifies whether or not to perform seven etches of operands after address calculation.

Among the instructions, there is an instruction that only performs an at-vs calculation without fetching an operand, and stores it in a desired register, so it can be identified using this pit.

Table 2 On the other hand, the size specification part SZl has an operand size of 8.
．． 16. Specifies whether the code is 32 or 64 bits, which allows you to retrieve the number of bits of data from memory or a register according to this code. Depending on the addressing mode, an extension section containing displacement (or offset), etc., may be required in one word or two or more words. Therefore, in this embodiment, the extension part EXI of the first operand is configured to continue from the second word following the first word.

The first operand extension EXIKljL<nth word contains an operation designation part OP that designates details of an operation such as addition or subtraction. However, the width of the operation group designation part OP does not require all 16 pits due to the type of instructions required.

Therefore, in this embodiment, the upper 6 bits of the n-th word are used as the operation overwrite designation part OF, and the remaining fields contain 8 bits.
A bit-width second operand specification section EA2 and a 2-bit width size specification section Sz2 indicating the size of the second operand are provided.

In this way, the operation specifying part OP and the second operand specifying part EA2 constitute the n-th word, and if necessary, the extension part EX of the second operand
2 continues from the (n+1)th word following the nth word.

FIG. 4 shows an example of the hardware configuration of a microprocessor that operates according to an instruction system having two operand instructions according to the present invention.

The microprocessor of this embodiment includes a microprogram control control section. That is, in the LSI chip 1 constituting the microprocessor, there is a micro ROM (read-only) in which a micro program is stored.
A micro ROM 2 provided with a memory (memory) 2 is accessed by a micro address generation circuit 5 and sequentially outputs micro instructions constituting a micro program.

The micro address generation circuit 5 is supplied with a signal obtained by decoding the code of the macro instruction fetched into the instruction register 3 by the instruction decoder 4. The microaddress generation circuit 5 forms a corresponding microaddress based on this signal and supplies it to the microROM 2. Since this is K,
The first instruction in the series of microinstructions that executes the macroinstruction is read. This microinstruction code enables various temporary registers and data buffers.

Control signals are generated for the execution unit 6, etc., which includes an arithmetic and logic unit (ALU), an address calculation unit AU, etc.

Reading of the second and subsequent microinstructions in a series of microinstructions corresponding to a macroinstruction is performed by supplying the code of the netast address field of the microinstruction read immediately before to the microROM 2.

That is, a microinstruction latte 9 is provided to hold the next in the immediately preceding microinstruction, and the second and subsequent microinstructions are read out based on its output and the address from the microaddress generation circuit 4.

The series of microinstructions thus read out are decoded by the microinstruction decoder 10.

The execution unit 6 is controlled by the control signal.

A macro instruction is executed.

The address calculation unit AU calculates an extension part EX for specifying the address of an operand (for example, the information of the second word shown in FIG. 1) and an address in the execution unit 6. It is supplied to the address calculation unit AU via the extension section dedicated register 11 without being decoded.
Address calculation control information I obtained by decoding an instruction containing A (for example, the first word shown in FIG. 1)
The address calculation unit AU is controlled by the NF.

In this embodiment, although not limited to I#, a buffer storage method is adopted, and a cache memory 7 is provided in the microprocessor LSI, and frequently accessed program data among the data in the external memory 8 is cached. It is registered in the memorabilia. This speeds up program import.

As mentioned above, in this embodiment, the two-operand instruction is composed of a plurality of words.

The field width of the operation designation section OF can be increased. Therefore, it is possible to have many types of instructions. Moreover, since the first word contains the information necessary to calculate the effective address of the first operand (source operand), it is possible to start calculating the address of the operand simply by fetching the first word and decoding it. can. That is, since the extension part of the second word is supplied to the address calculation unit AU without being decoded,
Address calculation can be started immediately after decoding the first word. While this address calculation is being performed, the instruction register 3 and instruction decoder 4 are vacant, so during the address calculation or the 7th etch of the first operand using this address, the nth
By importing a word, the microinstruction corresponding to the operation code can be read.

Note that operand fetch refers to storing the contents of an operand stored in the external memory 8 or the like in a predetermined register in the execution unit 6. 12 etc. The addresses of the operands are calculated by said address calculation unit AU.

FIG. 5 shows an example of the format of a two-operand instruction consisting of three words. Fifth
FIG. 4B shows an execution sequence when the microprocessor shown in FIG. 4 executes the instructions in the format shown in FIG. As shown in Figure 5, the first word contains the first operand specification field EA.
The second word is provided with an extension field EXI for specifying the first operand, and the third word is provided with an operating code specifying field OP and a second operand specifying field EA2. As shown in FIG. 5(B), first, the first word is decoded by the instruction decoder 4 shown in FIG. 4 within the period of the first machine cycle MCI (51), and the first word is Information INF, micro ROM address information, etc. are formed.

Next, in machine cycle MC2, the address of the first operand is calculated based on the information of the second word and the address calculation information INF (52).

In machine cycle MC2, the above address calculation is executed (52) and a microinstruction is read from the micro ROM (53).

When this microinstruction specifies an operand 7 etch, the operand 7 etch is executed in machine cycles MC3 and MC4 (54).

In this machine cycle MC3, in addition to the operand fetch operation (54), the third word is decoded (55), and address information of the micro ROM is formed. Based on this address information, in machine cycle MC4.

A microinstruction is read (56). This microinstruction includes control information for executing the operation specified by the operation code specification field OP. Further, since the operands necessary for executing this operation have already been busy fetched (54), the operation can be executed immediately from machine cycle MC5 (57). Note that this 3-word instruction
This is because it does not have an extension field for specifying operands.

Address calculations using this extended field are not performed. Furthermore, this embodiment shows a case where fetching of the second operand is not necessary. The case where the 7-etch of the second operand is not necessary is the case where the location of the second operand is a register within the microprocessor.

In this way, by using the instruction format of the present invention, while the microprocessor is preparing the operands necessary for executing the instruction, the address of the operand is calculated and the contents of the operand are fetched into a predetermined register. In between, the operating code can be decoded. Therefore, there is no need to provide a dedicated time for decoding the operation code, and therefore the instruction execution speed can be increased.

In the above embodiment, the third word decoding step (55) and the operand fetching step (54) overlap, but the invention is not limited to this. That is, the third word decoding stage (55) is replaced by the address calculation stage (52).
You may also overlap it with To do it like this 1 from K
For example, if there is no operand fetch stage (54).

This allows the instruction execution phase (57) to start one machine cycle earlier.

FIG. 6(A)K shows an example of the format of a two-operand instruction consisting of four words.

The first word contains the first operand specification field EAI.
The second word is provided with an extension field EXI for specifying the first operand, the third word is provided with an operation code specification field OP and the second operand specification field EA2, and the fourth word is provided with an expansion field EXI for specifying the first operand. A specification expansion field EX2 is provided. 6th
FIG. 4(B) shows an execution sequence when the microprocessor shown in FIG. 4 executes instructions in the format shown in FIG. 4(A)K. first.

The first word is the fourth word within the first machine cycle MCI.
Decoded by the instruction decoder 4 shown in the figure (61)
, the information I necessary to calculate the address of the operand
Address information of the NF and micro ROM, etc. are formed. Next, in machine cycle MC2, the address of the first operand is calculated based on the information of the second word and the address calculation information INF (62). In machine cycle MC2, the above address calculation is executed (62
), the microinstruction is read from the microROM (63). When this microinstruction specifies the 7th edge of the operand, the machine cycle M
Operand fetch is executed in C3 and MC4 (64). In this machine cycle MC3, along with the operand fetch operation (64), the third word is decoded (65) and the address of the second operand is calculated. Necessary information INF, micro ROM address information, etc. are formed.

In machine cycle MC4, based on the information of the fourth word and the address calculation information INF.

Address calculation for the second operand is performed (66).

In machine cycle MC4, the address calculation is executed (66) and the microinstruction is read from the micro ROM (67).

When this microinstruction instructs an operand fetch, the operand fetch is executed in machine cycles MC5 and MC'6 (68).

The read microinstruction (67) also includes control information for executing the operation specified by the operation code specification field OP.

Since the operands required to perform this operation have already been fetched (68, 69),
The operation can be executed immediately from machine cycle MC7 (69).

In this way, by using the instruction format of the present invention, while the microprocessor is preparing the first operand necessary for instruction execution, the address of the operand is calculated and the contents of the operand are fetched into a predetermined register. While doing so, you can decode the operation code.

Therefore, there is no need to provide dedicated time for decoding the operation code. Therefore, the execution speed of instructions can be increased.

Although the above embodiment shows the case of a two-operand instruction, the present invention can also be applied to a case of a one-operand instruction. This is because the effects of the present invention can be obtained if the operation code can be decoded in parallel while the first operand is being prepared.

In addition, the multiple instructions that operate a microprocessor are
It is not necessary that all instruction formats are composed of the instruction format K according to the present invention, and it is also possible to include an instruction format different from the present invention as necessary. Therefore, a series of instructions can be constructed using the instructions in the format shown in FIG. 1 and the instructions in the formats shown in FIGS. 2 and 3. In this case, if a period during which the microprocessor does not substantially operate is included between the execution stage of one instruction and the execution stage of the next instruction, the speed of executing the series of instructions will be reduced. Therefore, as shown in FIG. 5CB, for example, it is preferable to immediately continue the operation (54, 57) based on the next instruction after executing a certain instruction (58).

FIG. 2 shows a configuration example of a 1-operand instruction, and FIG. 3 shows a configuration example of a 0-operand instruction. These instructions have a 2-bit class designation part CL, and by this class designation part CL,
Each instruction is designated as a one-operand instruction or a zero-operand instruction.

Also, the 1-operand instruction is the nth of the 2-operand instruction.
Like a word, the operation specifying section EA and the operand size specifying section SZ are arranged in a biased manner.This allows a one-operand instruction to quickly calculate the effective address of the operand and execute the instruction. Can be done. In addition.

If the 1-operand instruction also has an extension part like the 2-operand instruction, the extension part is placed in the second word following the above word consisting of the operation specification part OP, operand specification part EA, etc. Ru. The structure of the operand specification section EA is the same as the operand specification sections EA1 and EA2 of the two-operand instruction.

On the other hand, in the 0 operand instruction, all bits other than the class specification section CL are used for the operation specification section.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained.

The instruction is divided into multiple words, and the first word contains the information necessary to calculate the effective address of the operand, followed by a word containing the operation specification part. It is possible to start calculating the effective address of the operand before decoding the word, and to decode the operation word while calculating the address and fetching the operand 7, and to execute the instruction immediately after calculating the address of the operand and fetching the operand. This ability to execute instructions has the effect of increasing the number of instructions without reducing the instruction execution speed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the format of the two-operand instruction in the case where the instruction unit is 16 bits has been described, the format of the two-operand instruction is not limited to 16 bits, but can also be applied to cases where the instruction unit is 8 bits or 32 bits. Further, according to the above embodiment, if the unit of instruction is less than 16 bits (for example, 8 bits), it becomes difficult to configure one operand instruction with one word (in this case, 8 bits). Therefore, the present invention can be applied to the construction of such a one-operand instruction so that a word containing an operand specification part is followed by a word having an operation specification part.

In the above explanation, the invention made by the present inventor was mainly applied to the instruction format of a microprocessor, which is the field of application in which the invention was made, but the invention is not limited thereto, It can be used as a general instruction format for program control type data processing systems.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of the structure of an instruction format according to the present invention. 2 and 3 are explanatory diagrams showing examples of the configuration of an l-operand instruction and an O-operand instruction, and FIG. 4 is a block diagram showing an example of the configuration of a microprocessor that executes an instruction according to the present invention. FIG. 5 is an illustration of an embodiment of the instruction format according to the present invention, and FIG. 5) is an explanatory diagram showing the execution procedure of the instruction shown in FIG. FIG. 6 is a diagram showing another embodiment of the instruction format according to the present invention. FIG. 6(B) is an explanatory diagram showing the execution procedure of the instructions shown in FIG. 6 (ARK). 1... Microprocessor, AU... Address calculation unit, ALU... Operation
・Address calculation control information. Figure 1 Figure 2 Figure 3 Figure 5 (A) Figure 5 (B)

Claims (1)

[Scope of Claims] 1. The instruction includes a decoding means for decoding an instruction, and an execution means for executing the instruction, and the instruction includes a first word containing operand specification information;
a second word containing an opcode; a first step in which the first word is decoded; a second step in which the second word is then decoded; and an instruction is executed based on the opcode. A data processing system comprising a third stage. 2. The execution means includes an address calculation means, and the step of calculating the operand address exists before the second step or overlaps with the second step. Data processing system as described in Section. 3. The execution means includes an operand fetching means, and the step in which the operand is fetched occurs after the second step or overlaps with the second step. data processing system. 4. The data processing system further comprises a microinstruction storage means, and the operand fetching means is controlled in accordance with the microinstruction read out from the microinstruction storage means. Data processing system. 5. The data processing system according to claim 4, wherein the step of reading the microinstruction from the microinstruction storage means and the step of calculating the operand address overlap. 6. The instruction comprises a third word having an extension field for specifying an operand, and the address of the operand is calculated based on information contained in the first word and the third word. A data processing system according to claim 2. 7. having a decoding means for decoding the instruction and an execution means for executing the instruction, the instruction having a first word containing operand specification information;
a second word containing an opcode; a first step in which the first word is decoded; a second step in which the second word is then decoded; and an instruction is executed based on the opcode. A microcomputer comprising a third stage. 8. The microcomputer according to claim 7, further comprising a microinstruction storage means, wherein the execution means is controlled in accordance with microinstructions read from the microinstruction storage means.