JPS63266921A - Power-on reset signal generating circuit - Google Patents

Abstract

PURPOSE:To decrease power consumption by providing a transistor (TR) connecting in series with a (TR) being a component of a reset pulse width control circuit and executing switching operation by a generated reset signal so as to reduce the steady-state current after reset. CONSTITUTION:At application of power via a capacitor 5, the level of an input of an inverter 7 rises nearly equal to a power voltage, resulting that the output Q1 rises and reaches a high level. Then an N-channel TR 9 is turned on. When the power voltage exceeds a threshold value of an N-channel TR 2, the TR 2 is turned on and a gate input of a P-channel TR 1 goes to a low level and the TR 1 is turned on. In this case, a voltage proportional to the on-resistance of the TRs 1, 2 exceeds the threshold value of the N-channel TR 4, then the TR 4 is turned on and the input of the inverter 7 goes to a low level and the output Q2 goes to a low level. Then the N-channel TR 9 is inverted to be in the OFF state to interrupt the current flowing to the TRs 1, 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset signal generating circuit, and particularly to a power-on reset signal generating circuit with low power consumption and low integration density in a semiconductor integrated circuit.

[Conventional technology]

Generally, a power-on reset signal generation circuit in a semiconductor integrated circuit is used to set the state of the semiconductor integrated circuit after power is turned on.

An example of a conventional power-on reset signal generation circuit is shown in FIG. As transistors, P-channel transistor 11 and 13% N-channel transistors 12 and 14.
15 and 16 as capacitors, 17 as inverter
and 18 are connected as shown in Figure 2.

In this circuit, when the power is turned on, the input voltage of the inverter 17 rises almost equal to the power supply voltage through the capacitor 15, and as a result, the output Q2 also rises.

Further, when the power supply voltage exceeds the threshold voltage of the N-channel transistor 12, the N-channel transistor 12 becomes ONE.
,, the gate input of P-channel transistor 11 is LOW
Level 9. P-channel transistor 11 is turned on. At this time, when the specific voltage is proportional to the ON resistance of the P-channel transistor 11 and the N-channel transistor 12 and exceeds the threshold voltage of the N-channel transistor 14, the N-channel transistor 14 is turned on and the inverter 170 input H
Is it low level and the output Q2 is also high level?G)L
Changes to OW level. In this way, the output Q2 rises to the same level as the power supply voltage and is used as a reset signal until it changes from the )ligb level to the Low level.

[Problem that the invention seeks to solve]

In the conventional power-on reset signal generation circuit described above, even after the reset signal is generated after the power is turned on, the P-channel transistor 11 and the N-channel transistor 12 remain ON.
As a result, a steady current was flowing between the power supply and GND through both terminals, leading to an increase in power consumption.

Also, in order to reduce the steady current of the above drawback.

It is necessary to increase the gate lengths of the P-channel transistor 11 and the N-channel transistor 12 to increase the ON resistance of the transistors, which lowers the degree of integration of the semiconductor integrated circuit.

The purpose of the invention is to solve the above drawbacks, reduce the steady state current after reset, and reduce power consumption.

Another object of the present invention is to provide a power-on reset signal generating circuit that can read the degree of integration of a semiconductor integrated circuit.

[Means for Solving the Problems] The power-on reset signal generating circuit of the present invention includes a transistor connected in series with a transistor constituting a reset pulse width control circuit and operating a switch based on the generated reset signal. are doing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a power-on reset signal generating circuit according to an embodiment of the present invention. In Figure 1, transistors 1 to 4
．． Capacitors 5 and 6. Inverters 7 and 8 are similar to transistors 11 to 14 . of the conventional circuit of FIG. They correspond to capacitor 15 and 16% inverters 17 and 18, respectively. Further, as a transistor, the drain and source of the N-channel transistor 9 are connected to the N-channel transistor 2.
and GND, and the gate is connected to the output Q1. 770, connect the gate of the P-channel transistor 10 to the capacitor 5 and the gate and drain of the N-channel transistor 3, and connect the source and drain with n.
I) connected to the power supply and the gate of N-channel transistor 4, the gate and drain of P-channel transistor 1, and the drain of N-channel transistor 2;

In the present invention, when the power is turned on, the input of the inverter 7 rises to approximately the same level as the power supply voltage through the capacitor 5, and as a result, the output Q1 also rises to the Righ level. This causes N-channel transistor 9 to be in an open state. Then ′:1
ttc'? When the Ii pressure exceeds the threshold voltage of N-channel transistor 2, N-channel transistor 2 turns ONL,
, the gate input of P-channel transistor 1 goes to Low level? , P-channel transistor 1 turns on. At this time, when the i voltage proportional to the ON resistance of the P-channel transistor 3t1 and the N-channel transistor 2 exceeds the threshold direct voltage of the N-channel transistor 4, the N-channel transistor 4 is turned on and the input rjLo of the inverter 7 is
w level, and output Q2 also goes from high level to low
Change in level. Since the output Q2 becomes Low level, the N-channel transistor 9 is turned off, and the current i flowing to the P-channel transistor 1 and the N-channel transistor 2 is cut off. In addition, P channel transistor 1
01-1% This is a transistor for preventing the gate input of the N-channel transistor 4 from becoming unstable due to the N-channel transistor 9 being turned off.

In the above explanation, an N-channel transistor is used as the transistor 9 as an example, but the same effect can be obtained even with a P-channel transistor whose gate is connected to the output of the inverter. can be achieved.

〔Effect of the invention〕

If the power-on reset signal generating circuit of the present invention is modified as described above, the steady current is reduced and power consumption can be reduced.

In addition, due to the above effect, it is useful to reduce the size of the transistor in the reset pulse width control circuit.

The effect of increasing the degree of integration of semiconductor integrated circuits can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the invention, and FIG. 2 is a conventional circuit diagram. 1.3.10.11.13...P channel MO
S transistor, 2, 4.9, 12, 14...
N-channel MOS transistor, 5.6, 15, 16.
...Capacitor? , 8.17.18...
・Inverter %Ql, Q2...Output terminal. Foil 1 time

Claims (1)

[Claims] A power-on reset signal generating circuit for a semiconductor integrated circuit, comprising a transistor connected in series to a reset pulse width control circuit and operated as a switch by a generated reset signal.