JPS63241791A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the test time of a memory device large in capacity, by dividing the cell array of a semiconductor memory device at the time of applying a test, applying parallel tests on divided cell arrays, and outputting tested results to an output terminal in series. CONSTITUTION:The memory cell array 1 is divided into cell array block A1-A4. Bit line information in the blocks A1-A4 selected by column decoders CD1-CD4 are read out on data lines D1-D4 respectively, and are read out on comparator circuits C1-C4, and are compared with the expected value of a reference data line 4. The outputs of the circuit C1-C4 are inputted to an OR operator 5, and also, are inputted to a shift register 6. At the time of writing test data, information to be applied on an external write terminal 8 is written on the bit lines of the arrays A1-A4 being selected by the decoders CD1-CD4 simultaneously, and a fault signal is read out by a signal CLOCK, and is outputted to an output terminal 10. Thus, it is possible to shorten the test time of the memory device large in capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a writable and readable semiconductor memory device, and provides means for realizing a large capacity storage device without increasing test time.

2. Description of the Related Art Conventionally, semiconductor memory devices (hereinafter referred to as memories) have been tested using a memory tester or a simple test device with a configuration according to external specifications for actual use. For this reason, an increase in test time for large-capacity memories in recent years, that is, an increase in test cost, has become a problem.

Memory test is 0″ for all storage cells.

Basically, it is necessary to check whether the data "1" can be written and read correctly, but it is simple to check whether the data "1" can be written and read correctly.
Merely writing and reading 1" data is considered insufficient. For this reason, various test methods (test patterns) have been devised.

MARCH is a typical test pattern.

WALKING, PINGPONG, GALLOPPI
NG etc. are well known. N2K with INGPONG and GALLOPPING with these test patterns
Ratio sequence fru.

For example, when testing a 1M bit memory with the GALLOPRNG pattern, it takes 6N2x seconds (t is the memory cycle time). If t-100 ns is used, the test time will be approximately 183 hours, which is unrealistic.

In order to deal with the above problems, the following two methods have been proposed and implemented. The first method is to simultaneously test multiple memories with the same specifications in parallel, and this has been realized by improving memory tester functionality. With this method, for example, if 10 out of 100 memories are tested in parallel, the test can be completed in 1/1 degree of the conventional time. However, it does not have the effect of shortening the test time for one memory, and cannot be expected to essentially improve the problem of increased test time due to an increase in memory capacity. On the other hand, in the second method, the memory configuration at the time of testing is different from the actual specification. For example, the internal structure of a 1 Mbit memory is divided into four parts during testing, so that four blocks of 256 bit cell arrays can be tested in parallel. Thereby, the memory capacity during testing can be kept small, and the testing time can be shortened. There are two further types of this method. Method t is a method in which the 266-bit cell array of the four blocks is provided with independent input/output circuits and external terminals, and has the disadvantage that increasing the number of blocks increases the number of external terminals.

Method B has independent input/output circuits for the four cell array blocks, but after writing the same data to the four cell arrays, when reading, the result of the exclusive OR operation of the outputs of the four cell arrays is output as one output. It outputs to the terminal, and the internal configuration can be divided and tested in parallel without increasing the number of external terminals. However, when a fault is detected using this method, it is not possible to know in which divided block the faulty cell is present. Another problem is that failure cannot be detected if all memory cells selected at the same time in the four blocks fail simultaneously.

Problems to be Solved by the Invention Method A has a problem in that the number of external terminals increases due to block division during testing. Therefore, there is a limit to the number of block divisions. Furthermore, method B has the disadvantage that it may not be possible to detect a fault, and that it cannot determine which divided block has a fault.

The above-mentioned drawbacks include serious problems such as the inability to perform failure analysis of a failed semiconductor memory device or the inability to detect defects due to fuse blowing.

Means for Solving the Problems The present invention has been made in view of the above problems, and provides a memory that can be independently tested and analyzed for each cell array without increasing the number of external terminals due to block division of the memory cell array. This is what we provide.

In order to achieve the above object, the present invention provides a decoder circuit that can simultaneously select two of the n columns for a memory cell array of m rows and n columns, and bit line information (read data) of the simultaneously selected columns. The outputs of the comparator circuits are inputted in parallel to the comparator circuits used to compare the value with the expected value, and the outputs of the comparator circuits are inputted in parallel to an arithmetic means that performs an OR operation on the outputs of the comparator circuits, and outputted in series to an external output terminal. A semiconductor memory device is constituted by a shift register circuit that performs the write operation, and write means that simultaneously applies write data to the focus lines of the columns.

Operation By using the above-described means, the bit line information of k columns can be independently tested by the comparator circuits, and the test results can be known through the OR operation means. Further, in the present invention, the output of each comparator circuit is input to a parallel input type shift register circuit. As a result, when a fault signal appears at an external terminal, by reading the contents of the shift register to the outside, it is possible to know which comparator circuit has generated the fault signal, that is, in which divided cell array the fault exists. Can be done. In this way, the outputs of the individual comparator circuits are input to the shift register circuit without being output to external terminals, making it possible to perform effective tests without increasing the number of external terminals.

Embodiment An embodiment of a semiconductor memory device according to the present invention will be described with reference to FIG.

FIG. 1 shows a configuration diagram of a semiconductor memory device according to the present invention. In FIG. 1, memory cell array 1 is A1
．． A2. A3. It is divided into four A4 cell array blocks. In this example, 1,024 columns of bit lines are
Each cell array block is composed of 266 columns of bit lines. Therefore, each cell array has an independent column decoder〇D1. CD2, CD3
．． Equipped with CD4. When reading data, the focus line information selected by each column decoder is transmitted through four data lines D1. D2. D3. It is taken out on D4.

Each data line is input to the data selector 3 and is also connected to an independent comparator circuit C1, C2,
Connected to C3 and C4. Each comparator circuit is realized by an exclusive OR operation element, and a reference data line 4 is inputted in addition to the data line. Furthermore, the outputs of these comparator circuits C1, C2, C3, and C4 are sent to an output determination circuit 6.
At the same time, it is input to the parallel input type shift register circuit 6.

On the other hand, write data is written to the bit line selected by the column decoder specified by the decoder selector 7.

Next, the normal operation of the semiconductor memory device of this embodiment will be explained. First, in a write operation, data applied to the data input terminal 8 is applied to a bit line selected by a column decoder specified by a decoder selector. In normal operation, decoder selector 7
has four columns de=r-dar CD1. CD2, CD3,
Since only one of CD4(7) is specified, memory cell array A1. A2. A3
．． It can only be written on either A4 or A4 paper.

Further, in data reading, bit line information selected by the column decoder specified by the decoder selector is read out to the read terminal 10 via the data line and the data selector 3 in the same way as the write operation. At this time, the switch circuit 9 is closed to the a side. Here, the data selector 3 connects four data lines D1. D2. D3. This is for connecting one of D4 to an external terminal,
It is controlled by the same control signal as the decoder selector 7. In FIG. 1, a sense amplifier circuit for amplifying bit line information and a main amplifier circuit for amplifying information on a data line are omitted.

The above write and read operations are exactly the same as those of conventional semiconductor memory devices as far as they are viewed from the outside.

Next, the operation of the semiconductor memory device of this embodiment during testing will be explained. At the time of testing, this semiconductor memory device is tested with the internal memory cell array divided into four. That is, the decoder selector 7 selects CD1. CD2, CD3
, CD4 are simultaneously activated.

To write the test data, the information applied to the external write terminal is sent to the column decoders CDI, CD2゜0D3,
Cell array A1. selected by CD4. A2゜A3. A4
Write to four bit lines at the same time.

After performing the desired write operation, the contents of the four cell arrays are read simultaneously. The read operation is as follows.

A1. selected by four column decoders. A2. A3゜A
The bit line information in data lines D1, D2, .
D3. D4 is read out and the comparator circuit C,,
It is input to C2, C3, and C4. Comparator circuit C
4, C2, C3, and C4 compare each input data with the expected value of the reference data i line 4, and output a low level if it matches the expected value, and output a high level if they do not match. The output of the comparator circuit is input to the OR element 6. Therefore, the comparator circuits C1, C2, C
3, C4 output high level, i.e. cell array A1. A2゜A3. If a faulty cell exists in any of A4, a high level is output to the output terminal 10. Note that at this time, the switch 9 is closed to the b side.

As described above, the four cell arrays can be tested independently and the results can be known by monitoring the output terminals. However, if the errors in C, C2, C3, and C4 have output high level, that is, cell array A1. A2. A
3. It is not possible to know in which of A4 the faulty cell exists. This has various problems. For example, when performing failure analysis, it is unclear which cell array to analyze. Furthermore, even in the event of a failure using a fuse, it is not known which fuse should be blown.

In the present invention, when a fault signal is detected at the output terminal, by sequentially shifting out the contents of the shift register, it is possible to know in which cell array the fault exists. In Figure 1, comparators C1, C2, C
3, the output of C4 is input to the OR element 5 as described above, and at the same time is also input to the parallel input type shift register 6.

The shift register input terminal connects the comparator output via switch 11. The switch 11 is closed to the a side and latches the output of each comparator every read cycle. If a failure signal appears at the output terminal 1o, close the switch 11 to the b side and switch 9 to the C side.
Close it to the side and input a clock signal to the CLOCK terminal.

Through the above operations, by monitoring whether a high level appears at the output terminal at any lock, it is possible to know which cell array has a failure. In this embodiment, the contents of the shift register circuit are output to the outside using four clocks, and at the same time the contents of the register circuit are cleared.
Ready for the next read cycle.

Effects of the Invention As described above, the present invention makes it possible to realize a large capacity semiconductor memory device without increasing test time. According to the present invention, the cell array of a semiconductor memory device during testing can be divided, parallel tests can be performed on the divided cell arrays, and the test results can be taken out to the outside as necessary. This makes it possible to perform failure analysis or detect defects due to fuse blowouts without increasing the number of external terminals.

[Brief explanation of the drawing]

The figure is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention. 1...Memory cell array, 2...Row decoder, 3...Data selector, 4...
...Reference data input terminal, 5...Output judgment circuit, 6...Parallel input type shift register circuit, 7...Decoder selector, 8...
...Data input terminal, 9...Switch circuit, 10...Output terminal, A1. A2. A3. A4
...Block cell array, CD 1. CD2.
CD3゜CD4・・・Column decoder, C1, C2
, C3, C4... Comparator circuit, Dl,
D2. D3. D4...Data line. Name of agent: Patent attorney Toshio Nakao and 1 other person +
fart

Claims (1)

[Claims] a decoder circuit that has a memory cell array of m rows and n columns and simultaneously selects k columns out of n columns; k comparator circuits that compare the bit line information of the selected k columns with an expected value; an arithmetic means for performing an OR operation on all the outputs of the k comparator circuits; a shift register circuit that inputs the outputs of the k comparator circuits in parallel and outputs them in series to an external terminal; and bits of the k columns. A semiconductor memory device comprising a write means for simultaneously applying write data to lines.