JPS63237577A - MISFET manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a MISFET manufacturing method.

[Conventional technology]

In recent years, SOI substrates (Semiconductor on
Many laminated devices using In5ulator) have been devised. As an example, a stacked CMO5 SRAM by A. H. Hah et al.
posium on VLSI Techno-1og
y Digast of Technical pap
ers)). The gate electrode 3 is made of nMO.
It can be seen that 3FET and 9MO3FET are used in common.

[Problem that the invention seeks to solve]

However, since the surface of the semiconductor film for the p-MOSFET located in the upper layer is not planarized, the exposure accuracy of the photoresist used as an ion implantation mask when forming the source/drain regions cannot be improved, and this results in This is a drawback for miniaturization.

The purpose of the present invention is to eliminate such conventional drawbacks.
An object of the present invention is to provide a FET manufacturing method.

[Means to solve the problem]

The present invention is a method for manufacturing an elbow 5FET using an SOI substrate, in which an insulating film and a gate electrode are sequentially formed on a semiconductor substrate, and then a gate insulating film is grown on the surface of the gate electrode, and the gate electrode film thickness is After forming a semiconductor film thicker than the total thickness of the gate insulating film and the gate insulating film, planarizing the surface of the semiconductor film to such an extent that the gate insulating film is not exposed,
This MISFET manufacturing method is characterized in that, after forming an ion implantation mask in a portion that will become a channel region, source and drain regions are formed by ion implantation.

〔Example〕

゛Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Here, the MISFET is an nM transistor using silicon.

This will be explained using a 5FET as an example. Silicon is also used in other semiconductor films, and in addition to n MO5FET, p MOSFE
It is also possible with T.

In FIG. 1(a), first 1μ5Si is placed on the Si substrate 1.
O□2 is formed by a thermal oxidation method. Next, n”po
After growing ly-3i by 0.5-cm by the LPCVD method, the gate electrode 3 is formed by a resist process and an etching process. Next, the gate electrode 3 is made using a thermal oxidation method.
A gate oxide film 4 is grown as an insulating film on the surface of 400 layers. Thereafter, as shown in FIG. 1(b), a Si thin film 5 having a thickness of 0.7 - is deposited. On the surface of this Si thin film 5, irregularities corresponding to the shape of the gate electrode 3 are formed. In order to flatten these irregularities, the surface of the gate oxide film 4 is polished using a mechanical chemical polishing method to such an extent that the surface of the gate oxide film 4 is not exposed.
A thin film 6 is obtained. At this time, the Si thin film 6 on the gate electrode 3
The film thickness is set to be 0.1 μm or less.

Next, as shown in FIG. 1(d), after exposing the photoresist 7 to cover the portion that will become the channel region, arsenic element is introduced by ion implantation in order to form the source region 8 and the drain region 9. .

Thereafter, as shown in FIG. 1(e), 5
In210 was grown by 0.5 μm LPcVD method, and contact holes were formed in the source region 8 and drain region 9.
A source electrode 11 and a drain electrode 12 are formed using AQ to complete the elbow 5FET.

〔Effect of the invention〕

MIS with the gate electrode of the present invention on the back surface of the SOI thin film
According to the FET manufacturing method, the surface of the SOI thin film can be flattened by polishing, etc., and the thickness of the SOI thin film that will become the channel region can be made thinner, so when miniaturizing the device, it is possible to improve the exposure process of the device and the electrical characteristics of the device. This is extremely advantageous, and since the semiconductor film that will become the channel region is made thinner by the planarization process, it is possible to make the slope of the subthreshold current steeper in the drain current-gate voltage characteristics of the MOSFET that is manufactured. can.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a conventional example. 1...Si substrate 2,10...Sin
. 3... Gate electrode 4... Gate oxide film 5
．． 6...Si thin film 7...Photoresist 8...Source region 9...Drain region 11...Source electrode 12...Drain electrode (α) (b) (C) Figure 1

Claims (1)

[Claims] (1) In a MISFET manufacturing method using an SOI substrate, an insulating film and a gate electrode are sequentially formed on a semiconductor substrate, and then a gate insulating film is grown on the surface of the gate electrode, and the thickness of the gate electrode and the gate electrode are After forming a semiconductor film that is thicker than the total thickness including the insulating film thickness, the surface of the semiconductor film is flattened to such an extent that the gate insulating film is not exposed, and then an ion implantation mask is formed in a portion that will become a channel region. A method for manufacturing a MISFET, characterized in that source and drain regions are formed by ion implantation.