JPS63233492A - Operation managing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a traffic management system for automatically creating legally defined traffic management data in the traffic management of commercial vehicles.

(Prior art) Conventionally, in a driving recorder installed in a vehicle, a disc-shaped recording paper is rotated at a constant speed by an electric motor decelerated by a gear, and a pen recorder that can take pictures in the radial direction is used to record the data necessary for driving management, i.e. A pen recorder records speed, etc. along the circumferential direction (time axis). For this reason, the legally required operation management table is created by collecting recording sheets from each vehicle when necessary for management purposes, and from these recording sheets, data necessary for managing the driver's driving time, rest time, etc. I try to collect them.

(Problems to be solved by the invention) However, in such conventional operation management,
Since the operation recorder records operation data by pen-writing on recording paper, the accuracy and resolution of the recorded data is very low, and it is difficult to extract the data necessary for management from the graph data written on the recording paper. Since the operation management table for each driver and vehicle is created by sequentially reading the data visually, there is a problem in that work efficiency is extremely low.

(Means for Solving the Problems) The present invention has been made in view of such conventional problems, and it is possible to automatically create operation management tables without the need for manually reading operation data. The purpose is to provide a traffic management system that enables

In order to achieve this object, the present invention includes a memory module having a built-in storage medium and in which predetermined operational data is recorded numerically while installed in a vehicle; A readout means for reading out stored data by: reading out operation management data such as driving time, break time, maximum speed, driving distance, etc. based on the operation data read out from the memory module by the reading means and providing information to the driver and the driver; Alternatively, a management data creation means for creating classified operation records for each vehicle is provided.

(Function) In the traffic management system of the present invention having such a configuration, when necessary for management, memory modules are collected from vehicles and set in the successive unit (reading means), thereby recording data in the memory modules. The operation data is read out, and the management data processing device calculates operation management data such as driving time, rest time, maximum driving speed, and travel distance for each driver and vehicle, and prints out an operation management table using a printer, etc. This makes it possible to perform vehicle operation management work extremely efficiently.

(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter referred to as CPU), which calculates the travel time, driver rest time, etc. necessary for operation management based on the operation record data collected from each vehicle.
Calculate operation management data such as maximum driving speed and distance traveled.

Reference numeral 2 denotes a CRT terminal equipped with a CRT and a keyboard, which instructs the CPU 1 to perform arithmetic processing necessary for creating and displaying operation management data based on collected operation record data. 3 is an external storage device, which records and saves the operation record data collected by the CPU 1 and the operation management data calculated by the CPU 1 on a recording medium such as a magnetic disk, floppy disk, or magnetic tape. It has sufficient storage capacity to accommodate the data.

Reference numeral 4 denotes a printer, which prints out the operation record data collected by the CPUI and the calculated operation management data necessary for management to create an operation management table.

Furthermore, 5 is a reading unit, which reads vehicle operation record data necessary for operation processing of operation management data in the CPU 1. Reference numeral 6 denotes a memory module that stores operation record data such as speed and engine rotational speed when installed in the vehicle.The memory module 6 is detachably installed in the vehicle operation recording device, and is used to store operation management data. When creating it, it is removed from the vehicle and set at the reading position relative to the reading unit 5.

Furthermore, the reading of the driving record data from the memory module 6 by the continuous unit 5 is performed using a non-contact coupling method using an induction coil, as will be explained later. In addition to supplying operating power to the memory module 6, bidirectional data transmission for reading operation management data is performed.

Of course, the combination of the reading unit 5 and the memory module 6 is
The connection may be made using an electrical contact instead of the non-contact connection method.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

FIG. 2 is an explanatory diagram showing an example of operation record data recorded in the memory module 6 when installed in a vehicle.

In the driving record data shown in Figure 2, one piece of memory data consists of 8 bits and 1 byte data, and the first address AO and the next address A1 are the driver ID number for identifying the driver. is memorized. Of course, if it is desired to identify the vehicle, the vehicle ID number will be stored. After the next address A2, engine rotation speed and speed data are stored in units of one minute, and addresses A2 and A2 are stored.
3 are both O, so the content is the engine rotation speed Q
rpm and speed OFa/h, which means that the vehicle is stopped at this time. At addresses A4 and A5, the engine speed at 12:58 is 2.700 rl.
)m and speed of 52KIIt/h are stored, indicating that the vehicle has started running at this point. A time mark* is stored at address 88, and this time mark is 13:00 OO.
Since the minutes are indicated, the year, month, day, and time are stored in the next addresses A9 to A12. And address A13, A
14 stores the engine rotation speed and speed at 13:00, and thereafter the engine rotation speed and speed are similarly stored in units of one minute.

When the memory module 6 storing the operation record data shown in FIG. 2 is set in the reading units I to 5,
The memory module 6 enters the operating state upon receiving power supply from the readout unit 5, and then receives readout control (designation of readout command and readout address) from the readout unit 5, and the memory module 6 starts the stored operation. The management data is read to the continuous unit 5, and the operation record data of the memory module 6 is transmitted from the continuous unit 5 to the CPU 1.

The CPU 1, which receives the operation record data of the memory module 6 from the continuous unit 5, performs a process of creating operation management data based on this operation record data.

For example, CPLll first reads the driver's ID number, identifies which driver's data is to be created, displays it, and stores it. Next, search for the time mark, that is, the leading position of the date and time written every hour. For example, if we search for the time mark (address A8) in the operation record data in Figure 2, 13:00 on March 17, 1987 will be determined from the following addresses A9 to A12, and the address A2. The data of A3 is 3 minutes earlier, that is, 12:05 on March 12, 1987.
This is 7 minutes of recorded data, and it is determined that recording has started from this point, and the recording start point is displayed and stored.

Next, the CPU 1 sequentially refers to only the speed data from the top position of the data, and calculates the running time by counting the number of data whose speed is not 0KIn/h. Also, by counting the number of speeds per hour, the rest time is calculated. However, when counting the number of OKI&/h, not only the break time but also the stop time due to traffic lights, traffic jams, etc. are counted. Therefore, by determining, for example, only a portion of 10 minutes or more, that is, a portion where 10 or more consecutive Ochi/h values are the break time, the break time can be calculated with almost no error.

Next, the CPU 1 sequentially refers to the engine speed, and counts the time when the ratio of the engine speed to the engine speed (engine speed/speed) exceeds a certain value (approximately the same value as the 1st and 2nd gear ratios). . Driving conditions in which the ratio of the engine speed to the engine speed exceeds a certain value represent driving conditions that are tiring and require the driver to pay close attention, such as on downhill slopes, in congested areas, and on narrow roads. The driving time with high driving fatigue is calculated and displayed and recorded from the time when the ratio of rotation speed to speed exceeds a certain value.

Conversely, if the speed is set to a certain value over a long period of time, for example 70 touches/
If the speed continues for more than h, this indicates that the driver was driving on the expressway without taking a break, so whether to instruct the driver to take a break based on the calculated value of the driving time exceeding this predetermined speed. It is possible to display and record the judgment data as to whether or not the application is accepted.

Furthermore, search for the maximum speed from the referenced speed data,
It is also possible to check whether the maximum speed exceeds the legal speed limit.

FIG. 3 is a circuit block diagram showing an embodiment of the successive unit and memory module of FIG. 1.

In FIG. 3, read units 1 to 5 are first provided with a read control section 5A using a CPU that controls data read, and is connected to the CPU 1 of FIG.

The input/output port for the memory module 6 of the read control unit 5A is connected to a serial interface 7, and the serial interface 7 converts parallel data from the read control unit 5A into serial data, and converts serial data from the storage module side into parallel data. Convert to data.

The read data (continuation instruction and address) sent out from the continuation control unit 5A via the serial interface 7 becomes a switching signal for the multiplexer 8. For the multiplexer 8, the oscillation circuit 9 outputs 1500KI-Iz and 17
When the multiplexer 9 receives the data bit "1" from the serial interface 7, the multiplexer 9 receives the data bit "1" from the oscillation circuit 9.
Select and output a 714K HZ clock frequency signal.

Also, the data bit “
0'', the clock frequency signal of 1500KH2 is selected and output. Therefore, the multiplexer 8 and the oscillation circuit 9 constitute an FM modulation means that converts the serial data into two different frequency signals corresponding to the data bits r1J roj.

1714KHz or 1 selected by multiplexer 8
The frequency signal of 500Kl-12 is passed through a low-pass filter 10.
is given to the signal and converted into a sine wave signal.

The frequency signal converted into a sine wave by the low-pass filter 10 is amplified by the power amplifier 11, and the induction coil 1 for transmission is amplified by the power amplifier 11.
2.

13 is an induction coil for reception, and the frequency signal obtained by the induction coil 13 is amplified by a high frequency amplifier 14 and converted to FM.
The signal is supplied to the demodulation circuit 15.

Here, the data bit is “1” from the memory module 6 side.
Since a frequency signal with a frequency of 1865KH2 and zero frequency at data bit rOJ is sent,
5 converts the 1865KH2 frequency signal into a data bit "1" and outputs it when it is input, and converts it into a data bit rOJ when the frequency becomes zero, and supplies it to the successive control unit 5A via the serial interface 7. I try to do that. As a specific example of the FM demodulation circuit 15 that converts such a frequency signal into data bits, the center frequency 1
It consists of a bandpass filter with a bandwidth of ±50Kl-1z at 860Kf-1z, and a detection circuit using a diode to detect the output of this bandpass filter, and further includes a comparator to shape the waveform of the detected output.

Next, explaining the memory module 6, reference numeral 16 is an induction coil for power supply and signal reception, which is opposed to the induction coil 12 of the reading unit 5, and is heated to 1500K by electromagnetic induction coupling.
An FM modulated signal consisting of a combination of t-1z and 1714 KHz is induced. The output of this induction coil 16 is the power supply circuit 1
7, and rectifies the frequency signal consisting of a combination of 1500 KH2 and 1714 KHz, thereby producing a power supply voltage +5■ used in the internal circuit of the memory module 6. In addition, the output of the induction coil 16 is the FM demodulation circuit 1
8 and the two signal frequencies to the data bit rlJ
Convert to rOJ. The specific configuration of the FM demodulation circuit 18 that converts these two frequency signals into data bits has a center frequency of 1714 KHz and a passband width of ±50.
It is equipped with a Kflz bandpass filter and a detection circuit using a pin diode, etc. that detects the output of the bandpass filter, and outputs a data bit "1" when receiving a frequency signal of 1714Kllz. Also, other than that,
That is, upon receiving a frequency signal of 1500KH2, the data bit "0" is output.

The data signal demodulated by the FM demodulation circuit 18 is sent to the CPU 19
supplied to The CPU 19 is equipped with an asynchronous serial communication circuit 21 as shown by the dotted line, and performs serial data transmission while synchronizing signals with the successive unit 5 using an asynchronous serial communication circuit 21. Note that the CPU 19 is of a one-deep type, and the ROM and RAM are built into the same chip.

A nonvolatile memory 20 for storing data is connected to the CPU 19. As this non-volatile memory 20,
For example, an E that can electrically rewrite data using an external signal.
An EPROM (electrically erasable FROM) is used, and a CMOS type is used to further reduce current consumption. This non-volatile memory 20 is a CP
Data can be read or written by receiving address designation by U19.

The data read out from the nonvolatile memory 20 by the CPU 19 is converted into serial data under the control of the asynchronous serial communication circuit 21 and provided to the FM modulation circuit 22 . The FM modulation circuit 22 outputs a frequency signal of 1865 KHz when receiving the data bit "1" from the CPU'19, and stops outputting the frequency signal when receiving the data bit rOJ. Specifically, it consists of an oscillation circuit with an oscillation frequency of 1865 KH2 and an AND gate that takes the logical product of the oscillation output and the data bit from the CPU 19. As a result, for successive data, the data bit "1" becomes 1.
It becomes a frequency signal of 865KH2, and the data pin 1-rO
J becomes the frequency loser signal.

The output of the FM modulation circuit 22 is supplied to an induction coil 23. This induction coil 23 is arranged opposite to the induction coils 13 of the reading units 1 to 5, and transmits the read data from the nonvolatile memory 20 by inducing a frequency signal in the induction coil 13 by the magnetic field generated by the induction coil 23. .

In addition, in the read operation from the memory module 6, prior to making a continuous request to the memory module 6, a confirmation signal is first sent and the state of electromagnetic coupling of the induction coil is checked depending on whether or not a confirmation response signal is received from the memory module 6. After receiving a normal confirmation response, data succession processing is started. Furthermore, the read control unit 5A performs an error check on successive data sent in units of, for example, 32 bytes, and when an error is detected, issues a retransmission request to the memory module 6, and a specified number of retransmission requests are issued. If error detection is also being performed, the error data is
Send to PU1.

Furthermore, the driving recorder installed in the vehicle to write the driving record data to the memory module 6 may be the same as the reading unit 5, or the g4 coil 13, high frequency amplifier 14, and FM demodulation circuit 15 of the reading unit 5 may be used. A write-only one is used.

FIG. 4 is a circuit block diagram showing another embodiment of the reading unit and memory module of FIG. 1, which is characterized by a synchronous clock communication method in place of the asynchronous communication method of FIG. 3.

First, the reading units 1 to 5 are provided with an induction coil 12 that sends operating power and a synchronous clock to the memory module 6, and an induction coil 13 that performs bidirectional transmission of successive information between the memory module 6. For the induction coil 12,
The induction coils 16 of the memory module 6 are opposed within a predetermined gap, allowing operating power and synchronization clocks to be transmitted from the readout unit 5 to the memory module 6 through non-contact inductive coupling between the induction coils 12 and 16.

In addition, due to non-contact inductive coupling between the induction coil 13 of the successive unit 5 and the induction coil 23 of the memory module 6,
Bidirectional transmission of read commands and addresses from the reading unit 5 to the memory module 6 and transmission of read data read from the memory module 6 is possible.

The memory module 6 has a built-in nonvolatile memory 25 using EEFROM.
is a memory equipped with a shift register 24 on the same chip for converting write data serially transmitted from the outside into parallel data, and also converting parallel data read from the nonvolatile memory 25 into serial data and sending it out. Examples of memory units with a built-in shift register 24 that performs serial-to-parallel conversion on the same chip include the NMC9306 manufactured by National Semiconductor and the X2404 manufactured by XICOR. EEPROM can be used.

For example, a memory unit with built-in non-volatile memory 25 (~
NMC930 manufactured by National Semiconductor
6, the shift register 24 has a shift l-clock terminal SK, a chip select terminal (enable terminal)
C3 has a serial data input terminal DI and a serial data output terminal Do, and by supplying a shift clock to the shift clock terminal SK in an enabled state with the chip select terminal C8 set to H level, the shift clock is provided to the serial data input terminal DI. Serial data is read in synchronization with the shift clock and converted into parallel data, and writing/reading control for the nonvolatile memory 25 can be performed. Furthermore, there is a write/write interface between the shift register 24 and the nonvolatile memory 25.
An instruction decoder 26 for decoding subsequent instructions and an address decoder 28 for specifying a write or read address are provided.

FIG. 5 is a time chart showing successive control over the nonvolatile memory 25 by the shift register 24 of FIG.

In this continuous control, when the chip select terminal C8 is set to the 1'' level while the shift clock is supplied to the shift clock terminal SK, an enable state is obtained in which data can be read from the serial data input terminal DI. In this state, a 3-bit read command "110" and an arbitrary 4-bit read address r are input to the serial data input terminal DI.
When A3 A2Al Ao J is given, the subsequent instruction and each bit of the read address are converted into parallel data in synchronization with the shift clock SK, the instruction decoder 26 decodes the read instruction, and the read mode is set in the nonvolatile memory 25. At the same time, the address decoder 2B decodes the read address and specifies a subsequent address in the nonvolatile memory 25. When this read command and successive address converted into parallel data by the shift register 24 are given to the nonvolatile memory 25, the nonvolatile memory 22 reads out 16 bits of read data from the specified address and transfers it to the shift register 24. The shift register 24 that has received the read data transfers the read data from the serial data output terminal Do to D15 to [) in synchronization with the shift clock SK.
It is converted into serial data in the order of 0 and output.

In the continuous unit 5 which is intended for the memory module 6 having a built-in memory unit that performs read control using the shift clock and chip select signal shown in FIG. 5, the shift register 24 in the memory unit of the memory module 6 has It is necessary to supply a shift clock and a chip select signal (enable signal) as well as operating power.

Therefore, the continuous unit 5 has a 435
A sine wave oscillator 3 that oscillates a sine wave signal of K l-1z
0, a sine wave oscillator 32 that oscillates a 450Kt-1z sine wave signal for shift clock, and 46 for enable.
A sine wave oscillator 34 that excavates a 5Kl-12 sine wave signal.
is provided. The outputs of the sine wave excavators 30, 32, and 34 are input to the multiplexer 36, and the multiplexer 36 selects one of the sine wave signals based on the control signal from the continuous control unit 38 using the CPU and outputs the selected sine wave signal to the amplifier 40. The current is supplied to the induction coil 12 for upstream signal transmission.

The read control unit 38 starts read control when receiving a read command from the CPU 1 in FIG. K HZ is selected and supplied to the induction coil 12 via the amplifier 40.

When the read control is started, when the synchronization clock for serially transmitting the read command and address is "1", the clock frequency signal 450KH2 is selected and supplied to the induction coil 12 via the amplifier 40, When the synchronization clock is “O”, the enable frequency signal 46
The switching operation of selecting 5Kl-IZ and supplying it to the induction coil 12 is repeated alternately.

That is, the multiplexer 36 converts bit "1" of the synchronized clock for transmission and reception given from the read control unit 38 to 450 bits.
It modulates with a KHz frequency signal, and also modulates the synchronized clock bit rOJ with a 465 KHz frequency signal, and further modulates the 435 K for power supply when the synchronized clock cannot be obtained.
A frequency signal of H2 is supplied to the induction coil 12. In response to frequency signals that are time-division multiplexed after being modulated with the power, clock, and enable frequencies supplied to the induction coil 12 of the successive unit 5, an induction coil is provided on the memory module 6 side. 16 is provided with means for demodulating an operating power supply, a shift clock, and an enable chip select signal from a frequency modulation signal induced by inductive coupling.

First, the output of the induction coil 16 is given to the rectifier circuit 42, which rectifies all the frequency modulation signals induced in the induction coil 16 and supplies the power supply voltage VCC to each circuit section in the memory module 6. supply.

In addition, the output of the induction coil 16 is 450 K for the clock.
Bandpass filter 4 that extracts the Hz frequency modulation signal
4, and the bandpass filter 44 has a passband band of ±2 to 2.5KHz with respect to the center frequency 450KH2, and therefore three frequency signals 435, 450, 4
Only the 450KH7 frequency modulation signal for clock can be extracted from 65Kl-1z. The output of the bandpass filter 44 is given to a detection circuit 46, which demodulates the shift clock from the 450 KHz frequency modulation signal, further shapes the waveform into a rectangular wave signal by the waveform shaping circuit 48, and performs the shift clock in the memory unit. register 2
The demodulated shift clock is supplied to the shift clock terminal SK of No. 4.

Further, the output of the induction coil 16 is input to a bandpass filter 50 for extracting the enable frequency modulation signal 465Kl-1z, and the bandpass filter 50 has a passband width of a center frequency of 465KH2±2 to 2.5KHz. 435, which is therefore induced in the induction coil 18.
Only the enable frequency modulation signal of 465 KH2 can be extracted from the three frequency modulation signals of 450 and 465 KHz. The output of the bandpass filter 50 is given to the detection circuit 52, which demodulates the enable clock signal (inverted signal of the shift clock) from the 465KH2 frequency modulation signal, and after shaping the waveform in the waveform shaping circuit 54, It is input to one side of the OR gate 56. A shift clock from the waveform shaping circuit 48 is supplied to the other side of the OR gate 56, and by logically ORing the shift clock and the enable clock in the OR gate 56, an enable signal for the chip select terminal C8 of the shift register 24 is generated. give.

That is, since the shift clock shown in FIG. 6(a) and the enable clock shown in FIG. 6(b) are input to the OR gate 56, by taking the logical sum of the two,
An enable signal to be supplied to the chip select terminal C8 shown in FIG. 6 (C>) can be generated.

Therefore, regarding the read state of the memory module 6,
The bit “1” of the same 1 clock obtained from the read control unit 38 by the multiplexer 36 provided in the successive unit 5
By selecting a frequency signal of 450 K )-1z for the clock with "" and a frequency signal of 465 K Hz for the enable with the bit rOJ of the synchronization clock,
The OR gate 56 of the memory module 12 is connected to the chip select terminal C3@H while the enable clock is obtained.
It is possible to create an enable state for reading as a level.

Next, the transmission of the continuation command and address from the continuation unit 5 to the memory module 6 will be explained.

First, the successive unit 5 is provided with a multiplexer 60 for serially converting a read command and a read address using an internal clock and converting bit data output from the read control section 38 into a frequency signal. multiplexer 6
One input terminal of 0 is 48 which represents data bit "1".
A sine wave excavator 62 for excavating a 2KH2 frequency signal is connected and the other input of multiplexer 60 is connected to ground to provide a zero frequency signal representing data bit "0". Therefore, the multiplexer 60
When it receives the data bit "1" from , it outputs a frequency signal of 482KH2, and when it receives the data bit rOJ, it outputs a signal with a frequency of zero.

That is, the multiplexer 60 represents data bits "1" and "O" depending on the presence or absence of 482 KHz.

The output of the multiplexer 60 is connected to the induction coil 13 via an amplifier 64 and an analog switch 66. The frequency modulated signal of the data bits supplied to the induction coil 13 induces a frequency modulated signal in the induction coils 23 of the memory modules 6 which are separated within a predetermined gap.

The frequency modulation signal induced in the induction coil 23 of the memory module 6 is input to the bandpass filter 72 via the analog switch 68, and the bandpass filter 72 has a frequency modulation of ±2 to 2.5KH2 with respect to the center frequency a482Kl-lz.
Therefore, only the frequency modulated signal of 4 82 Kl-1z induced in the induction coil 23 is extracted. The output of the bandpass filter 72 is given to the detection circuit 74, and the detection circuit 74 outputs 482 KHz.
The data bits are demodulated from the frequency modulated signal, further shaped into a rectangular wave signal by a waveform shaping circuit 76, and then the demodulated bit data is input to the serial data input terminal DI of the shift register 24 in the memory unit.

On the other hand, the serial data output terminal D of the shift register 24
Serial bit data (read data) sent from o
A sine wave oscillator 78 is provided which oscillates a 482K l-I Z sine wave signal to frequency modulate the bit data in order to transmit the bit data back to the reading unit 5.
The output of 8 is connected to the induction coil 23 via an amplifier 80 and an analog switch 82. The analog switch 82 connects the serial data output terminal D of the shift register 24.
The analog switch 82 is turned on and off when the data bit is "1" and supplies a 482 KHz sine wave signal to the induction coil 23, and when the data bit is rOJ, the analog switch 82 is turned on and off by the pitch data obtained from OJ. 82 is turned off, and the supply of the sine wave signal of 482K1-(Z to the induction coil 23 is cut off.The serial data of the shift register 24 is Data output terminal.

The serial bit data obtained from is 4 with bit “1”
It is converted into a frequency signal of 82KH2, and converted into a frequency loser signal at bit rOJ.

In addition, the output of the induction coil 23 is filtered through a bandpass filter 72.
The analog switch 68 connected to the serial data output terminals of shift 1 to register 24.

It is turned on and off by a signal inverted by an inverter 84, and serves as a serial data output terminal.

When the serial bit data of successive data is not output from , the analog switch 68 is on because the output of the inverter 84 is at 1 level, and the serial data output terminal Do becomes bit "1" due to the successive data.
When this happens, the output of the inverter 84 becomes L level, turning off the analog switch 68.

Analog switch 82 in this memory module 6
The output of the induction coil 13 of the readout unit 5 is connected to a bandpass filter 88 via an analog switch 86, and the bandpass filter 88 has a center frequency. It has a passband width of 482 Kl-1z±2 to 2.5 KHz, and when the analog switch 86 is on, the frequency modulated signal from the memory module 6 induced in the induction coil 13 is extracted and the data bit is detected by the detection circuit 90. It demodulates and sends the read data serial pin 1- to the read control unit 38.

The analog switches 66 and 86 that selectively connect the induction coil 13 are turned on and off 11 by the control signal from the readout control unit 38, and the control signal of the analog switch 86 is inverted by the inverter 92. When analog switch 66 is on, analog switch 86 is always off, and conversely, when analog switch 86 is on, analog switch 66 is off. The analog switch 66 is turned on when sending a read command and read address to the memory module 6, while the analog switch 86 receives read data sent from the memory module 6 after sending the read command and read address. It turns on when

According to the embodiment shown in FIG. 4, the reliability of serial data transmission is higher than that of the asynchronous communication method when transmitting and receiving synchronous clocks, and there is almost no need for error checking, so communication control is simplified. , it is possible to shorten the transmission processing time for writing and reading.

(Effects of the Invention) As explained above, according to the present invention, a memory module in which predetermined driving record data is stored as numerical data when installed in a vehicle is set in the continuous unit, and the memory module stores the data in the memory module. The management data creation means automatically calculates the travel time, break time, maximum speed, travel distance, etc. necessary for operation management based on this operation record data, and creates an operation management table. It can be created and memorized, and it is possible to not only create legally required operation management tables, but also to understand the driving fatigue of each driver and the road conditions of the areas passing through, which helps prevent accidents caused by driver overwork. At the same time, it is possible to grasp the operation status and perform highly comprehensive operation management.

[Brief explanation of drawings]

Fig. 1 is a system block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing an example of operation record data recorded in a memory module, and Fig. 3 is a system block diagram showing an example of operation record data recorded in a memory module. FIG. 4 is a circuit block diagram showing an embodiment of the module, FIG. 4 is a circuit block diagram showing a second embodiment of the read unit and memory module in FIG. 1, and FIG. 5 is a circuit block diagram showing an example of the memory module in FIG. 6 is a signal waveform diagram showing the shift clock, enable clock, and enable signal from the successive unit to the memory module of FIG. 4, and FIG. 7 is a read control of the embodiment of FIG. 4. It is a flowchart showing. 1: Central processing unit (CPU) 2: CRT terminal 3: External storage device 4: Printer 5: Reading unit 6: Memory module

Claims (2)

[Claims] (1) A memory module with a built-in storage medium and in which predetermined operation data is numerically recorded when installed in a vehicle; and a reading means for reading out stored data by setting the memory module that has been removed from the vehicle. ; Based on the operation data read out from the memory module by the reading means, operation management data such as driving time, break time, maximum driving speed, driving distance, etc. are calculated, and operation records are classified by driver and/or vehicle. A traffic management system comprising: management data processing means for creating; (2) Each of the memory module and the reading means includes an induction coil, and the reading means supplies power to the memory module and reads stored information through non-contact magnetic induction coupling by the induction coil. 2. The traffic management system according to claim 1, wherein the traffic management system is configured to transmit data to and from the vehicle.