JPS63228641A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To limit an unused wiring channel region to the minimum degree and to prevent the increase in chip area, by arrangine MOS transistors and bipolar transistors on the entire surface in a chip on a specified repeating unit basis, and appropriately using the MOS transistors and the bipolar transistors as logic elements or wiring regions. CONSTITUTION:Many CMOS basic cell lines are juxtaposed in the direction at a right angle with a basic cell line. At least one or more lines of bipolar CMOS basic cell lines are included between the CMOS basic cell lines. Namely, bipolar transistors 32 and a configuration, in which a pair of a PMOS 33 and an NMOS 34 are held between the bipolar transistors 32, are made to be one basic cell unit. Said units are repeatedly arranged on the entire surface of a chip. The basic cells are sequentially used as wiring regions with the bipolar element and the MOS element as basic units. Thus the bipolar and MOS transistors neighboring wiring channel regions can be utilized without remaining parts, and one logic element can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a master slice type gate array suitable for optimizing the width of a wiring region and increasing the degree of integration.

[Conventional technology]

For example, Japanese Patent Application Laid-Open No. 119647/1984 discloses a master slice type gate array in which basic cells made of MOS transistors are laid out in the internal region of a chip, and the cell array region can be used both as a functional element region and as a wiring region. Also, such MO
3. A method of arranging basic cells made of MOS in a gate array of the full-surface layout method is described in the July issue of Nikkei Micro Devices. However, the above MO
In the three-way gate array, the minimum unit of the wiring channel region is limited by the size of the MOS transistor. Therefore, there are restrictions on setting the channel width, and no consideration has been given to optimizing the channel width in accordance with the number of tracks. Further, a gate array in which basic cells consisting of MOS transistors and bipolar transistors are formed in a chip is disclosed in, for example, Japanese Patent Laid-Open No. 59-39060. In the gate array described above, a dedicated wiring area is provided in advance between basic cell columns consisting of MOS transistors and bipolar transistors, as shown in FIG.

Therefore, the wiring area is at least larger than the dedicated wiring area, and even in this case, no consideration has been given to optimizing the channel width according to the number of trunks.

[Problem that the invention seeks to solve]

The above conventional technology finely changes the width of the wiring channel area according to the number of tracks in the channel, and does not take into account the optimization of the channel area, resulting in unused wiring areas and increasing the chip area. There was a problem.

An object of the present invention is to enable finely changing the width of a wiring channel region and to minimize unused wiring channel regions to prevent an increase in chip area.

[Means for solving problems]

The above object is achieved by laying MoS transistors and bipolar transistors on the entire surface of the chip in predetermined repeating units as shown in FIG. 1, and using the MOS transistors and bipolar 1-transistors as appropriate logic elements or wiring areas.

[Effect]

FIG. 3(a) shows one cell row on the entire surface of the CMOS O5. 30 is PMOS, 31 is NHO2, PM
OS and NHO3 are lined up alternately.

In this example, the minimum unit used as a wiring channel is a MOS
The height is a. Therefore, the channel region is a, 2a
, 3a, . . . , it changes by an integral multiple of the MOS height a. Further, FIG. 3(b) shows a basic cell row of a bipolar/CMOS composite gate array having a dedicated wiring area. 32 is a bipolar transistor, 33 is a PMO
S and 34 are NMOS, and bipolar transistors sandwich a CMOS composed of PMOS and NHO3.

Furthermore, the shaded area 35 is a dedicated wiring area, and no logic element can be configured in this area. Therefore, the channel region is at least larger than the height C of the dedicated wiring region. When increasing the channel region, the top of the bipolar element can be used as a wiring region.

The channel region at this time is c+b, where b is the height of the bipolar transistor. When the channel region is further increased, the area above the PMOS and NMOS is used as a wiring region. In this case, the basic cell 1
Since 2c+2b+2a' is used as a wiring area, the dedicated wiring area one level above the basic cell becomes a common wiring area, and 2c+2b+2a' becomes a channel area as a whole. On the other hand, FIG. 3(c) shows a bipolar CMOS according to the present invention.
An example of cell rows in the tiling method is shown. 32 is a bipolar transistor, 33 PMOS and 34 N
It has a configuration in which a MOS pair is sandwiched between 32 bipolar transistors, and these 32, 33 degrees, 34, and 32 degrees are used as one basic cell unit and are repeatedly laid out over the entire surface of the chip. This basic cell can be sequentially used as a wiring region using bipolar elements and MO3 elements as basic units. In this case, as will be described later in the embodiment, one logic element can be formed by fully utilizing the bipolar and MOS transistors adjacent to the wiring channel region. The minimum unit of the wiring area is the height b of the bipolar transistor, which is successively 2b, 2b+a'.

The channel region can be changed finely, such as 2b+2a'... The lengths a and a' used here.

Expressing the actual length of b and c in terms of the number of pitches in the wiring, a is 8 pitches, a' is 6 pitches, b is 2 pitches,
C is 3o pitch. The reason why a and a' are both MOS sizes but have different values is that a is the MOS size used in a CMOS gate array, and a' is the MOS size used in a bipolar CMOS gate array. Therefore, the relationship is a>a'. This is because, with a MOS gate array, it is necessary to increase the MOS size to a certain extent in order to increase the load driving capability, whereas with a bipolar
In the case of a CMOS gate array, the load driving capability is increased by bipolar transistors, so the MOS size can be made smaller than that of a CMOS gate array. Here, an example of the layout of the basic cell of B1CMOS and CMOS is shown in FIG.
We will explain specifically which area this corresponds to. In FIG. 8, 80 is a BiCMOS basic cell, 81 is a CM
It shows the basic cell of the OS. 3 manpower each
It is possible to configure a logic cell equivalent to ND. In the B1CMOS cell shown in (,), 82 is a bipolar transistor, and there are two bipolar transistors per cell. 83 is PMO5 and %84 is N M
It is an OS. 85 is the gate of MOS, 3-man power N
CMOS even if the logic cell equivalent to AND is used as B1CMOS
It is laid out in such a way that it can be configured as on the other hand,
In the CMOS cell shown in (b), 86 is PMO3 and 87 is NMOS. Similar to (a), 85 is M
It is the gate of the OS, and a logic cell equivalent to a three-way NAND can be configured as a CMOS. In figure (a), 8
The area indicated by 8 is the area occupied by the bipolar transistor, corresponds to the above-mentioned symbol, and has two pitches.

That is, the area 88 has a width that allows two wires to pass through. On the other hand, the area indicated by 89 is the area occupied by the MOS transistor, and corresponds to the above-mentioned symbol a'.
It's pitchy. That is, the area 89 is PMO3, NM
This is the area width that allows six wires to pass through each OS.

In this way, the area 88 occupied by the bipolar transistor
is smaller than the occupancy 89 occupied by the MOS, and therefore, by effectively utilizing the area occupied by the bipolar transistor as a wiring area, the wiring pitch can be changed to be finer. On the other hand, in Figure (b), the area shown at 90 is M
This is the area occupied by the OS transistor, corresponds to the symbol a mentioned above, and has 8 pitches. That is, the area 90 has a width that allows eight wires to pass through. The area widths a and a' shown above.

b is a region occupied by the bipolar transistor and the MOS transistor as individual elements, and the widths of these cannot be freely changed without changing the performance of the individual elements. here.

MOS region 89 used in the B1 CMOS cell in figure (a)
However, the MOS region 90 used in the CMOS cell in FIG.
The reason why the pitch is two pitches smaller than that will be explained using FIG. FIG. 9 shows the load capacitance dependence of the signal propagation delay time of the logic cells included in the basic cell. 90 is B
91 shows the characteristics of a logic cell based on an iCMOS basic cell.
92 shows the characteristics of a logic cell using a CMOS basic cell with the same MOS size as used in the B1 CMOS cell of 90. Show characteristics. The load dependence of 90 is about - for 91 and about - for 92. In this way, CMOS is BiCMO
Since the load dependence of the delay time is greater than that of S, it is necessary to increase the MOS size as much as the area allows to increase the driving capability of the MOS. Particularly in gate arrays, low load dependence of delay time is a very important characteristic. Therefore, in order to improve the load dependence of delay time, CM
The MOS size of the OS gate array must be larger than the MOS size of the B1CMOS gate array. As is clear from the above explanation, Bj, the bipolar occupied area width of the CMOS basic cell, and the MOS occupied area width a' are the CMOS1 & the MOS occupied area width a of this cell.
Therefore, according to the B1CMOS laying method according to the present invention, it is possible to change the wiring area more finely than with the conventional method. Table 1 shows variations in wiring channels for each method.

Table 1 As described above, bipolar CMOS total O according to the present invention
In the 3-surface method, the wiring channel area can be changed more precisely than in the CMOS all-O3 surface-surface method or the fixed channel method, so it is possible to optimize the wiring channel width and prevent an increase in the chip area. Can be done.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 4, 5, and 6. Reference numeral 43 indicates a cell row portion consisting of bipolar and MOS transistors arranged inside the chip.

(,) indicates the case where no channel region is provided on the device.

32 is a bipolar transistor, 33 is a PMOS, 34
is NMO3, and as shown in the figure, bipolar and PMOS
, NMO3゜bipolar, bipolar, PMOS, NM
They are arranged regularly in the order of O3°... As shown in 40, PMOS, NMO3 and bipolar 2 sandwiching it
This constitutes one bipolar cMO3 main cell. In the cell row, bipolar CMOS basic cells 40 are repeatedly arranged. (b) shows the case where the region of the bipolar transistor indicated by the hatched portion 44 is used as the wiring channel region. At this time, one side of the wiring area 44 is 4
0 bipolar CMOS basic cell, the other side is 41 C
A MOS basic cell can be configured. The wiring channel has two pitches corresponding to one bipolar transistor.

Next, (c) shows a case where a region corresponding to two bipolar transistors (4 pitches) indicated by a hatched area 44 is used as a wiring channel region. At this time, on one side of the wiring area 44 are 41 CMOS basic cells.

The other side can similarly configure a CMOS basic cell. (d) is an area (8
This is the case when the pitch (pitch) is used as the wiring channel region. At this time, it is possible to configure a bipolar CMOS basic cell 42 with a 4o bipolar CMOS basic cell on one side and a bipolar cell placed in the center of the cell on the other side with the wiring region 44 in between. (e) shows the area (as indicated by the hatched area 44) which is the sum of two bipolar transistors and one MO3.
10 pitch) is used as the wiring channel region. At this time, one side of the wiring area 44 is C41.
MOS basic cell, the other side is 42 bipolar CMOS
Basic cells can be configured. (f) is the combined area of 2 bipolar transistors and 32 MOs, that is, the area of 1 bipolar CMOS basic cell (16 pinches)
This is the case when the area is used as the wiring channel area. At this time, one side with the wiring area in between is 40 bipolar CMOS.
The other side of the basic cell can also be configured as a bipolar CMOS basic cell.

(g) shows a case where a region (18 pitches) including three bipolar transistors and two MOS transistors indicated by a hatched area 44 is used as a wiring channel region. At this time, 41 ctios basic cells can be configured on one side across the wiring area, and 40 bipolar CMOS basic cells can be configured on the other side. Similarly, the number of wiring channels can be increased sequentially. As is clear from this example, according to the method of the present invention, it is possible to effectively utilize the element area and to finely change the wiring channel area as shown in Table 1.

FIG. 5 shows the next embodiment. Reference numeral 50 indicates a cell row portion consisting of bipolar and MOS transistors arranged inside the chip. (a) shows the case where no channel region is provided on the device.

32 to 34 indicate the transistors described above. As shown in the figure, bipolar, PMOS, NMOS, bipolar, P
They are arranged regularly in the order of MOS, NMOS, and so on. In the cell row, bipolar CMOS basic cells shown at 40 and CMOS basic cells shown at 41 are arranged alternately. (b) shows a case where a region corresponding to one bipolar transistor indicated by a hatched portion 51 is used as a wiring channel region (2 pitches). At this time, both sides of the wiring area 51 are C
A MOS basic cell can be configured. (c) shows a case where a region corresponding to two MOS transistors indicated by a hatched portion 51 is used as a wiring channel region (12 pitches). At this time, bipolar CMOS basic cells can be formed on both sides of the wiring region 51. This embodiment is a cell arrangement suitable for using CMOS basic cells or bibolar CMOS basic cells in a concentrated manner.

FIG. 6 shows a third embodiment. 63 is a MOS row in which PMOS and NMOS are alternately repeated in the X direction; 6
4 is a bipolar row in which bipolar transistors are repeated in the X direction. In this example, one bipolar row is arranged for every two MOS rows. In this arrangement, basically a CMOS basic cell 62 and a bipolar C
The MOS basic cells 61 can be arranged alternately in the X direction. In FIG. 6, the shaded area is used as the wiring area, so in the X direction there are 62 CMOS basic cells and 61
A bipolar CMOS basic cell can be constructed as shown in the figure.

In this embodiment, the minimum unit of the wiring channel region in the X direction is 6 pitches corresponding to 31 MOs, and the minimum unit of the wiring channel region in the X direction is 2 pitches corresponding to one bipolar transistor.

As is clear from the embodiments shown in FIGS. 4 to 6 above,
According to the present invention, it is possible to finely change the wiring channel region. In addition, in the above embodiment, P M OS ,
NMOS and bipolar transistors are arranged regularly at a certain ratio.

This arrangement method is not limited to the example;
For example, the most efficient arrangement can be achieved by changing the ratio of OMO3 and bipolar, or by changing the arrangement order of PMOS and NMOS. Furthermore, in the above invention and embodiments, the basic cells formed by MOS and bipolar transistors, the logic cells formed by the basic cells, and the logic blocks formed by the logic cells, or the wiring between them have two or more layers. It is effective to use a multilayer wiring structure.

FIG. 7 shows a fourth embodiment. 70 indicates a wafer. As shown in the figure, the basic self 1 is spread over the entire surface of the wafer. The basic cell 1 is a CMOS basic cell or a bipolar CMOS basic cell, and both basic cells are mixed in the wafer. A macro cell configured by combining basic cells is placed at an appropriate location in a wafer, and the position and width of a wiring channel region for connecting within the macro cell or between macro cells can be efficiently set using the present invention. Can be done.

〔Effect of the invention〕

According to the present invention, the height of a bipolar transistor or a small size MOS is used as the basic unit of the wiring channel.
Since the height of the transistor can be used, the wiring channel region can be changed finely. This makes it possible to optimize the wiring channel area according to the number of tracks in the wiring channel, which has the effect of preventing an increase in chip area.

[Brief explanation of drawings]

Figure 1 is a chip diagram of the present invention, Figure 2 is a chip diagram of a conventional example, Figures 3 (a) and (b) are explanatory diagrams of the conventional example, and Figure 3 (c).
4 and 5 are explanatory diagrams of the present invention. FIG. 6 is a cell layout diagram of an embodiment of the present invention, FIG. 7 is a diagram showing another embodiment, FIG. 8 is a diagram showing a layout example of BiCMOS and 0MO5 basic cells, and FIG. 9 is a diagram showing the basic cell layout. FIG. 3 is a diagram showing the dependence of signal propagation delay time on load capacitance of constituent logic cells. DESCRIPTION OF SYMBOLS 10... Chip, 11... I/O and pad area, 12... Basic cell, 32... Bipolar transistor. 33...PMOS, 34...NMOS, 40,
42°61... Bipolar CMOS basic cell, 41.
62...CMOS basic cell, 44.51.60...
Wiring area agent Bus psychology ± 7□1,11□ Mo7HH2B ,,t "i4 Become area Fig. 3 Fig. 1 (α): .5° High Fig. 4. (α) (b) (,C)
(d) (e) Keno ((j
- Figure 9 (α) Cb) (C) Figure 6 64 ---- /\4 Borai Commander - BnC Village O3t Le 81 --- C OS Hill 8'l-1~l Iboratra Sojisuf 33.86-P
Between 03 84.8”l ---NMO5 85-11 τ'-QO ---8 Bin→-

Claims (1)

[Claims] 1. A C with a large number of CMOS basic cells composed of PMOS and NMOS arranged side by side in one direction of the main surface on one main surface side.
Bipolar/CMOS consisting of a MOS basic cell array, PMOS, NMOS, and bipolar transistors
Bipolar CM with many basic cells arranged in one direction
In a master slice type gate array LSI that includes an OS basic cell string and multiple layers of wiring that are stacked on the main surface with an insulating film interposed therebetween and connect within the basic cells and between the basic cells, the CMOS basic cell string is At least one row of bipolar CMOS devices arranged in parallel in a direction perpendicular to the basic cell row.
A semiconductor integrated circuit device comprising a basic cell string between CMOS basic cell strings.