JPS63222863A - Driver circuit drive control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This is a drive control method for a driver circuit that simultaneously drives a large number of multiple current loads. In order to solve defects caused by stray inductance in the pattern of the driver circuit that mounts the elements, which is caused by back electromotive force that occurs when driving the driver circuits simultaneously, multiple driver elements are divided into multiple blocks, and the blocks are By configuring the drive timing to be shifted by a small amount of time between the two, it is possible to significantly reduce defects caused by back electromotive force.

[Industrial application field]

The present invention relates to a drive control method for a driver circuit that simultaneously drives multiple current loads.

When a large number of current loads, such as the coils of a 24-pin print head, are simultaneously driven in a dot printer or the like, a large instantaneous current may flow at once.

Furthermore, as the printing speed increases recently, the current value that flows at one time tends to further increase.

On the other hand, driver circuits that simultaneously drive multiple current loads, such as print head coils, tend to be densely mounted on a given printed circuit board. Therefore, the pattern on the printed board becomes thinner, and when a current is passed through such a pattern, the stray inductance increases.

In particular, when a high current is passed through such a pattern all at once, the back electromotive force generated by the stray inductance increases,
This causes an adverse effect on other circuits.

It is required to minimize factors that have such an adverse effect and simultaneously drive a large number of current loads at high speed.

[Conventional technology]

FIG. 4 is a block diagram for explaining the conventional example, and FIG. 5 is a diagram for explaining the drive timing situation in the conventional example.

FIG. 4(1) shows an example of a driver circuit 2 having one driver element TRI.

A control unit 1 in the figure turns on/off the driver element TRI to control the drive current 11 flowing through the current load.

In addition, the stray inductance of the load or the pattern connecting the inside of the driver circuit 2 (particularly the pattern between the emitter of the driver element TRI and the power supply part 21) shown by the dotted line in the figure is shown.

Further, the symbol vA indicates the potential at point (A) in the figure, the symbol ■8 indicates the potential at point CB) in the figure, and the symbol 21 indicates the power supply section.

FIG. 4(2) shows an example of a driver circuit 2a having N driver elements TRI to TRn.

In this case, the timings ATI to ATn for flowing the drive currents h to ■7 applied to each driver element TRI to TRn are as follows:
As shown in FIG. 5, they are simultaneously turned on in the control unit 1, and the driver elements TRI to TRn are simultaneously driven.

In addition, the stray inductance of the pattern at this time LXALL
is larger than the floating inductance t, x in the case of one driver element TRI. Also, the drive current IALL flowing through this floating inductance LXALL is each drive current! , ~11.

In particular, the driver circuit 2 configured as shown in FIG. 4(2)
In a, when each driver element TRI to TRn is turned on/off simultaneously, the power supply section 21 and each driver element TRI
~ Stray inductance L between emitters of TRn
A large back electromotive force is generated due to L.

Further, due to this back electromotive force, voltages vA and Vl at positions (A) and (B) become voltage V<voltage vA. Note that this is called an undershoot.

[Problem that the invention seeks to solve]

If the undershoot is large as described above, it will have an adverse effect on the control unit 1, and in the worst case, each driver element TR
This leads to the destruction of I~TRn.

That is, since the magnitude of the undershoot is proportional to the magnitude of the change in the drive current, the undershoot becomes even larger in the driver circuit 2a configured as shown in FIG. 4(2).

In order to reduce these problems as much as possible, treatments such as multilayering the printed board (not shown) on which the driver circuit 2a is mounted and adding capacitors to suppress inductance are performed.

Therefore, implementing extra measures increases costs and also causes a decrease in the reliability of the driver circuit 2a.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 includes a driver circuit 2a that simultaneously drives N (N>1) current loads (driver elements) within a predetermined time, and a control section 10 described below. It is configured with the following.

The control unit 10 of the present invention includes a basic timing generation unit 1 that generates basic timing for driving the driver circuit 2a.
1, and M pieces of N current loads (driver elements) (1<M≦N)
blocks, and multiple current loads within that block (
block-corresponding timing signal 'rt-T for simultaneously driving the driver elements).

a delay unit (delay unit) 12 that generates a current load (driver element); and a drive signal generation unit that generates drive signals HP, -HP, corresponding to the N current loads (driver elements), to drive the current loads (driver elements). 13 and delay means (delay section)
12 and the drive signals HP, ~HP, from the drive signal generator 13. part) 14.

[Effect]

N pieces (N>1) of current loads (driver elements) with 1<M≦
Divide into M blocks such that N, and set the drive timing between each block to a minute time (
By configuring the drive current of the current load (driver element) to be shifted by several hundred ns to several μs) and suppressing the magnitude of the change when the drive current of the current load (driver element) turns on and off, the back electromotive force that occurs due to the current change when on and off is It becomes possible to significantly reduce various defects caused by electric power.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining the driving situation in an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

The present embodiment shown in FIG. 2 takes a 24-bin dot printer as an example.

The delay section 12 of this embodiment shown in FIG. 2 divides the 24 drive elements TRI to TR24 into, for example, six blocks 1 to 6, and transmits timing signals T0 to T, corresponding to the six blocks 1 to 6. 5 delays 12 to generate
It consists of (1) to 12(5).

Further, the calculation unit 14 has 24 drive elements TRI to TR2.
AND circuits 14 (1) to 14 (24) corresponding to 4
It consists of

Further, the basic timing generating section 11 generates a timing signal T0 having a predetermined period. Each delay 12 (
1) to 12(5) are this timing signal T. for t time (
In this example, it is set as 500 ns).
AND circuits 14 (1) to 14 (24) that generate timing signals T, ~T, and correspond to corresponding blocks 1 to 6;
is sent to one input terminal of the .

On the other hand, the drive signal generator 13 outputs signals to each of the drive elements TR1 to TR2 according to instructions from a predetermined circuit (not shown).
The drive signals HP, -EIPta corresponding to the output signal 4 are generated and sent to the other input terminals of the corresponding AND circuits 14 (1) to 14 (24).

AND circuits 14(1) to 14(24) are timing signals T. ~TS and the drive signal HP+ -HPza are logically ANDed, and control signals ATI to ATza that turn on each of the drive elements TRI to TR24 are sent out.

Incidentally, the drive circuit 2 in the 24-pin dot printer;
When the inner drive elements TRI to TR24 are divided into six blocks and each block is shifted by 500 ns, the shift width is at a level that does not cause any problem at all when converted to the printing position.

Further, FIG. 3 shows a situation in which the blocks 1 to 6 are driven with a lag of time t.

By controlling each of the drive elements TRI to TR24 as described above, measures against stray inductance when mounting the drive circuit 2a consisting of each of the drive elements TRI to TR24 can be greatly simplified, and costs can be reduced. , we can expect an improvement in trustworthiness.

〔Effect of the invention〕

According to the present invention as described above, it is possible to significantly reduce various defects caused by back electromotive force generated due to current changes during on/off, so it is possible to simplify countermeasures against stray inductance and reduce costs. As well as being able to
We can expect an improvement in trustworthiness.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the driving situation in the embodiment of the present invention, and FIG. 4 is a conventional block diagram. FIG. 5 is a block diagram explaining an example, and FIG. 5 is a diagram explaining the drive timing situation in a conventional example. In the figure, 1.10 is a control unit, 2 and 2a are driver circuits, 11 is a basic timing generation unit, 12 is a delay unit (delay means), 12(1) to 12(5) are delays, and 13 is a drive signal generation unit. 14 is an arithmetic unit (arithmetic means), 14 (1) to 14 (24) are AND circuits, 21 is a power supply unit, 4 rows of squares are displayed between O, tZm72 diagram

Claims (1)

[Claims] In a driver circuit (2a) that simultaneously drives N current loads (N>1) within a predetermined time, the N current loads are divided into a plurality of blocks, and within the blocks delay means (1) for generating timing signals (T_0 to T_m) corresponding to the blocks for simultaneously driving multiple current loads;
2) and calculation means (14) for calculating conditions for driving the N current loads based on the timing signals (T_0 to T_m) from the delay means (12), A drive control method for a driver circuit, characterized in that drive timing (AT_0 to AT_n) between each divided block is shifted by a predetermined time within a range in which driving of all current loads is completed within a predetermined time.