JPS63220341A - Cache memory device - Google Patents

Abstract

PURPOSE:To rapidly execute an instruction by specifying the number of blocks to be transferred at the time of copying data from a main memory to a cache memory when the cache memory is not hitted, and after reading out the blocks, counting the number of cache hits. CONSTITUTION:If the cache memory 3 is not hitted, the number of blocks to be transferred is specified at the time of copying data from the main memory 10 to the cache memory 3, and after reading out the blocks, the number of cache hits is counted. When a coincidence output is not sent from a comparator 4 at the time of reading out data from the cache memory 3, a flip flop 9 is set up and the value of a block register 11 is set up in a block counter 12. When the flip flop 9 is set up, data reading from the main memory 10 is requested and read data are successively stored in the cache memory 3. Every storage of the read data in the cache memory 3, the block counter 12 counts down its contents, and when the value of the counter 12 reaches '0', the reading operation is ended.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cache memory used in an electronic computer, and more particularly to a block read method of a cache memory.

(Prior Art) Conventionally, in this type of cache memory, when the cache memory is not hit, the replacement unit (generally block size) has been fixed.

For example, in a cache memory with a block size of 16 bytes, when the central processing unit accesses a replacement unit, if the cache meme sell is not hit, 16 bytes are read from the main memory and written to the cache memory. It was.

(Problem to be solved by the invention) In the conventional cache memory described above, the block length is fixed, so if the block size is large, there is an effect of pre-reading instructions, but until the block read is completed, the cache memory The disadvantage is that it becomes unusable for a long time.

Conversely, when the block size is small, the period of block reading is short, so the unusable time due to block reading is shortened, but there is a drawback that the effect of pre-reading is lost.

An object of the present invention is to eliminate the above drawbacks by specifying the block transfer amount when copying data from the main memory to the cache memory and counting the number of cache hits after reading the block if the cache memory is not hit. However, it is an object of the present invention to provide a cache memory device configured so that the unusable time of the cache memory is shortened and a read-ahead effect can be exhibited.

(Means for Solving the Problems) A cache memory device according to the present invention includes a cache memory, a block counter, a block register, a bit counter, and counter setting means.

Cache memory is for storing a copy of some of the data stored in main memory.

The block counter is used to specify the amount of data transferred when copying data from the main memory to the cache memory when the cache memory is not hit.

The block register is for holding the initial value of the block counter.

The catch counter is for counting the number of cash hits after block reading.

The counter setting means is for setting the content value of the bit counter in the block counter by a specific instruction.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cache memory device according to the present invention.

In FIG. 1, 1 is an address register, 2 is a cache directory, 3 is a cache memory, 4 is a comparator,
5 is a data driver/receiver, 6 is a block address register, T is an instruction register, 8 is a decoder, 9 is a flip-flop, 1o is a main memory, 11 is a block register, 12 is a block counter, 13 is an OR gate, 14 is data 15 is a switching circuit, and 16 is a bit counter.

The address register 1 is for storing an address for requesting cache data, and the cache directory 2 is for specifying the υ address from the lower part of the address register 1.

The comparator 4 compares the read output of the cache directory 2 with the upper part of the address register 1. When a match output is obtained from the comparator 4, the data bus 14 and the cache memory 3 are connected to the data driver/
They are logically connected at receiver 5. cache memory 3
If a matching output from the comparator 4 is not obtained when the bladder is removed, the flip 70 knob 9 is set, and the flip 7
The output of the 0 block 9 sends a request to read data from the main memory 10.

Data read from the main memory 10 is configured to be sequentially written to cache addresses specified by the block address register 6.

The block counter 12 counts the amount of data read from the main memory 10. block counter 1
The initial value of 2 is stored in the block register 11.

The instructions stored in the instruction register T are decoded by a decoder 8, and the number of cache hits after block reading is counted by a bit counter 16. The value of the bit counter 16 is set in the block register 11 by the output of the decoder 8.

Next, the operation of the present invention will be explained in detail.

When an address is set in the address register 1 to send a data request to the cache directory 3, the upper part of the address is read from the cache directory 2 by the lower part of the address.

The read address and the upper part of the address register 1 are compared by a comparator 4 to check whether data is stored in the cache memory 3 or not. If the comparator 4 is delivering a match output, the data driver/receiver is enabled and the data in the cache memory 3 is read onto the data bus 14.

When the comparator 4 is not sending out a matching output, no data is stored in the cache memory 3, so the main memory 1
0 and the data is read and stored in the cash memory 3. If the comparator 4 does not send out a coincidence output when data is read from the cache memory 3, the value of the block register 11 is set in the block counter 12 at the same time as the flip-flop 9 is set.

When flip-flop 9 is set, main memory 1
A request is made to read data from 0, and the read data is sequentially stored in the cache memory 3.

The block counter 12 counts down each time read data is stored in the cache memory 3, and when it reaches "0", the output of the OR gate 13 becomes 10#, resets the flip-flop 9, and ends the read operation from the main memory 10. do.

When the instruction stored in the instruction register T is decoded by the decoder 8, the initial value of the block register 11 can be changed.

Since there is locality in the arrangement of data depending on the structure of the program, the content value of the instruction diversion block register 11 is increased if there is an effect of prefetching, and the content value of the block register 11 is decreased in the opposite case.

(Effects of the Invention) As explained above, the present invention specifies the block transfer amount when copying data from the main memory to the cache memory if the cache memory is not hit.
By counting the number of cache hits after a block read, the effect is that instructions can be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a cache memory device according to the present invention. 1... Address register 2... Cache directory 3... Cache memory 4... Comparator 5... Data driver/receiver 6... Block address register T... Instruction register 8... Decoder 9... Italian flip-flop 10... Main memory 11... Block register 12... Bit block counter 13... OR gate 14... Data bus 15... Switching circuit 16... Bit counter patent application Person NEC Co., Ltd. agent Patent attorney Hisashi Inoro 21

Claims (1)

[Claims] A cache memory for storing a copy of a part of the data stored in the main memory, and data transfer when copying data from the main memory to the cache memory if the cache memory is not hit. a block counter for specifying the amount; a block register for holding the initial value of the block counter; a bit counter for counting the number of cache hits after block reading; A cache memory device comprising: counter setting means for setting the content value of the bit counter.