JPH06266612A - Dma controller - Google Patents

Abstract

PURPOSE:To transfer data in high speed bus width even if a fraction byte occurs at the start side and the end side of DMA transfer. CONSTITUTION:One byte data transferred from a DMA unit whenever a transfer permission signal 32 is outputted from a control circuit 25 is latched at a byte position in a register 21, which a counter 253 shows. The counter 253 is counted up. When a counter value is changed to '0', the content of the register 21 is copied on a buffer 22. When transfer is judged to that of the fraction byte of the start side by a start address, word data on a memory, which corresponds to the address, is read into a register 23 through a high speed bus 3 with eight byte width. Then, data part subsequent to a position which lower three bits in the start address shows in the content of the register 23 is exchanged with the part of the buffer 22 by a merging circuit 24, and it is DMA-transferred through the high speed bus 3 so as to write it into an original word position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory connected to a high speed bus and a DMA device (input / output device) connected to a low speed bus.
The present invention relates to a DMA controller that controls the DMA transfer between and.

[0002]

2. Description of the Related Art A DMA controller of this type transfers data transferred from a DMA device (input / output device) such as a disk device connected to a low-speed bus to a memory connected to a high-speed bus according to a designation from a CPU, for example. In order to effectively use the high-speed bus for writing, data transfer (DMA transfer) is basically performed in units of the number of bytes matching the bus width of the high-speed bus. Therefore, for example, in a system in which the bus width of the high-speed bus is 8 bytes (64 bits) and the bus width of the low-speed bus is 1 byte (8 bits), the DMA
In order to write the data from the device to the memory, basically, the data transfer is performed by using all 8 bytes which is the bus width of the high speed bus.

However, such data transfer is possible only in the memory access (DM) specified by the CPU.
This is limited to a special case where the start position and the end position of (A transfer) coincide with the word boundary in units of 8 bytes and there is no fractional byte as shown in FIG.

Then, as shown in FIG. 5B, in a normal state in which there are fractional bytes on the start side and the end side,
D for the fractional bytes on the start and end sides
The MA controller generally transfers data in 1-byte units. In this case, the operation of acquiring (the right to use) the high-speed bus necessary for data transfer has also been performed for each fractional byte in units of 1 byte.

[0005]

As described above, in the conventional DMA controller, in the memory access for writing the data from the DMA device connected to the low speed bus to the memory connected to the high speed bus, the start side and the end side are accessed. Since it was necessary to transfer data in units of 1 byte for the fractional bytes of, the usage efficiency of the high-speed bus decreased and DM
There is a problem that the transfer rate of the entire A decreases.

The present invention has been made in consideration of the above circumstances, and an object thereof is a fraction on the start side and the end side in response to a memory access request for writing data from a DMA device to a memory connected to a high speed bus. Even if a bite occurs,
It is an object of the present invention to provide a DMA controller capable of performing data transfer with a high-speed bus width, thereby improving the use efficiency of the high-speed bus and further improving the transfer rate of the entire DMA.

[0007]

According to the present invention, a start or end of a DMA transfer is responded to a memory access request for writing data transferred from a DMA device (input / output device) to a memory connected to a high speed bus. When there is a fractional byte less than the bus width of the high-speed bus on the side, the control means for reading word data of the high-speed bus width corresponding to the transfer destination address from the memory, and the data read by this control means And a merge means for generating a write data having a high-speed bus width by rewriting the corresponding portion with a fractional byte, and the write data generated by the merge means is DMA-transferred through the high-speed bus to transfer the original data of the memory. It is characterized in that writing is performed at the word position of.

[0008]

In the above structure, the control means receives data from the DMA device connected to the low speed bus, for example, 2 ^n. When a memory access (memory write access) for writing to a memory connected to a high-speed bus having a bus width of bytes is requested, a fixed length of data, for example, between the DMA device and the DMA controller (a data register provided therein), for example, Data transfer is performed in units of 1-byte data. At the start of this data transfer, the control means checks whether the memory start address (lower n bits of the memory start address) corresponds to the start byte position (byte 0) of the high speed bus width. It is determined that there are fractional bytes on the start side of the DMA transfer. In this case, the control means reads from the memory the data at the word position on the memory designated by the memory start address (the higher address excluding the lower n bits of the data), that is, the word data having the high-speed bus width corresponding to the write destination. Keep it.

When it is determined that there are fractional bytes on the start side of the DMA transfer, the control means starts from the byte position corresponding to the memory start address to the bus width (2 ⁿ When the fractional bytes up to the final byte position of (byte) are transferred from the DMA device, the merging unit is controlled to merge the previously read word data with the fractional byte. As a result, the part corresponding to the fractional bytes in the read data was replaced with the fractional bytes.
Write data with a high-speed bus width is generated. The control means is
This write data is DMA-transferred and written in the same word position as previously read in the memory.

After that, the control means is controlled by the DMA device.
Data that is transferred sequentially in byte units is 2 ⁿ 2 ⁿ each time it becomes a byte The byte data is directly DMA-transferred via the high-speed bus and written to the memory. Then, the number of remaining transfer bytes is 1 byte or more by this DMA transfer,
Express bus width (2 ⁿ Less than a byte), the control means
Next, it is judged that the end side of the DMA transfer is present and there are fractional bytes. In this case, the control means reads the word data of the high speed bus width corresponding to the write destination from the memory.

When it is determined that there are fractional bytes on the end side of the DMA transfer, the control means controls the merging means at the time when the last 1-byte data is transferred from the DMA device, and first. The read word data is merged with the fractional bytes from the start byte position of the high speed bus width to the byte position of the last transfer byte. As a result, write data having a high-speed bus width is generated, in which a portion corresponding to a fractional byte in the read data is replaced with a fractional byte. The control means DMA-transfers this write data and writes it in the same word position as previously read in the memory.

[0012]

1 is a system configuration diagram of an information processing system including a DMA controller according to an embodiment of the present invention.

In FIG. 1, 1 is a CPU which is the center of the system, 2 is a memory (main memory) in which one word for storing programs, data, etc. is 8 bytes (main memory), 3 is a bus width (data width) of 8 bytes, for example. ) Is a highway bus. CP
U1 and the memory 2 are connected to the high speed bus 3. Four
Is a DMA device (input / output device) such as a disk device, and 5 is a low speed bus having a bus width of 1 byte, for example. The DMA device 4 is connected to the low speed bus 5.

Reference numeral 6 is a DMA controller connected to the high speed bus 3 and the low speed bus 5. DMA controller 6
Controls data transfer between the memory 2 and the DMA device 4. The DMA controller 6 in this embodiment is a DM
In response to a memory access request for writing data from the device A 4 to the memory 2, even if there are fractional bytes on the start side and end side of the requested size of data, the memory 2 via the high-speed bus 3 Data transfer between
It has a new configuration in which A transfer) is always performed with the bus width (8 bytes) of the high-speed bus 3. FIG. 2 shows the DMA controller 6
3 is a block diagram showing the configuration of FIG.

In FIG. 2, reference numeral 21 is an 8-byte data register for latching 1-byte data transferred from the DMA device 4 via the low-speed bus 5. This DM
The latch position (byte position) in the data register 21 of the 1-byte data from the A device 4 is determined by the value (any one of 0 to 7) of the byte position counter 253 in the control circuit 25 described later.

Reference numeral 22 is an 8-byte data buffer for latching the contents of the data register 21. The latch timing of the data buffer 22 is immediately after data is latched in the byte 7 (8th byte) of the data register 21 or immediately after the last byte of the transfer data is latched in any byte position of the data register 21. is there.

Reference numeral 23 is an 8-byte memory data register for holding 8-byte memory data read from the memory 2 via the high-speed bus 3. Reference numeral 24 is a merge circuit for merging the data in the data buffer 22 and the data in the memory data register 23. Is.

Reference numeral 25 is a control circuit which is the center of the DMA controller 6. The control circuit 25 generates various control signals for controlling data transfer according to the transfer request signal 31 from the DMA device 4 given via the low-speed bus 5.

The control signal generated by the control circuit 25 includes a transfer permission signal 3 for the DMA device 4.
2 and data latch signals 33-0 to 33-7. The data latch signal 33-i (i = 0 to 7) is sent to the DMA device 4
1 byte data from byte i of data register 21
Used to latch in the position. The control signal generated by the control circuit 25 further includes a data latch signal 34 to the data buffer 22, merge control information 35 for controlling the merge operation of the merge circuit 24, and a transfer request signal 36 to the high-speed bus 3. There is. A transfer end signal 37 from the high speed bus 3 for the transfer request signal 36 is input to the control circuit 25. The control circuit 25 includes a memory address register 251 and a transfer byte counter 2
52 and a byte position counter 253 are incorporated.

The memory address register 251 has a CP
The start address (memory start address) of the memory access (here, memory write access) requested by U1 is initialized. Memory address register 2
The content of 51 is incremented by "8" every time a high-speed bus width DMA transfer is performed, and the higher-order bits except the lower-order 3 bits specify the transfer destination word address on the memory 2.

The transfer byte counter 252 has a CPU 1
The memory access size (number of transfer bytes) requested by is initialized. The transfer byte counter 252 is
Each time 1-byte data is transferred from the DMA device 4 via the low-speed bus 5, it counts down to show the number of remaining transfer bytes.

In the byte position counter 253, the lower 3 bits of the above memory start address are initialized. The byte position counter 253 counts up each time 1-byte data is transferred from the DMA device 4 via the low-speed bus 5, and the latch position (byte position) in the data register 21 of the 1-byte data to be transferred next. Is specified.

Next, the operation of one embodiment of the present invention will be described with reference to CP.
According to the request from U1, the data transferred from the DMA device 4 is transferred to the high-speed bus 3 under the control of the DMA controller 6.
An example will be described in which a DMA transfer is performed to the memory 2 via.

First, the CPU 1 to the DMA controller 6
Data transferred from the DMA device 4 to the memory 2
Access to write to memory (memory write access)
Shall be requested. In this request, the memory start address (data transfer start memory address) and the transfer size (number of transfer bytes) are specified. Further, the CPU 1 requests the DMA device 4 to read the data, and the read start position (if the DMA device 4 is a disk device,
Read start disk address) and transfer size are specified.

In response to the above request from the CPU 1, the control circuit 25 in the DMA controller 6 stores the memory start address in the memory address register 251, and the transfer size (the number of transfer bytes) in the transfer byte counter 252.
And the lower 3 bits of the memory start address are set in the byte position counter 253, respectively.

Next, the control circuit 25 determines whether the value of the lower 3 bits of the memory address register 251 (the value of the lower 3 bits of the memory start address initialized in the memory address register 251) is "0". , Whether or not there is a fractional byte on the start side of DMA transfer is determined. This judgment is made by the byte position counter 25.
It is also possible to do according to a 3-bit value of 3.

If it is an example of data transfer (memory write) shown in FIG. 5B, the value of the lower 3 bits of the memory start address is "4", not "0". In this case, the control circuit 25 determines that there is a fractional byte on the start side of the DMA transfer, and outputs the read transfer request signal 36 to the high-speed bus 3 as shown in the timing chart of FIG. At the same time, the control circuit 25 sets the lower 3 bits of the memory address indicated by the memory address register 251 to 3 of all “0”.
The memory address replaced with the bit data is output to the high speed bus 3.

As a result, an 8-byte (64-bit) word specified from the memory 2 by an upper address excluding the lower 3 bits of the memory address, that is, an upper address (word address) excluding the lower 3 bits of the memory start address. The data is read, and as shown in Figure 4,
It is transferred to the DMA controller 6 via the high speed bus 3 together with the transfer end signal 37.

The 8-byte (1 word) read data from the memory 2 transferred to the DMA controller 6 is stored in the 8-byte memory data register 23 in the controller 6. The contents of the memory data register 23 at this time are, as shown in FIG.
It shall be "77".

In this way, when it is determined that there are fractional bytes on the start side of the DMA transfer, the control circuit 25 causes the memory 2 designated by the upper address (word address) excluding the lower 3 bits of the memory start address. The upper 8-byte (64-bit) word data is read in the memory data register 23.

On the other hand, the DMA device 4 performs a data read in response to the request from the CPU 1 and sends a transfer request signal 31 to the control circuit 25 in the DMA controller 6 via the low speed bus 5.

When the transfer request signal 31 is sent from the DMA device 4, the control circuit 25 returns a transfer permission signal 32 to the DMA device 4 if data can be input. The DMA device 4 responds to the transfer permission signal 32 by D
1-byte data is transferred to the MA controller 6 via the low-speed bus 5. Thus, from the DMA device 4 to D
Data transfer to the MA controller 6 requires transfer request signal 3
1 and the transfer permission signal 32.

1 byte data from the DMA device 4 is DM
It is guided to the 8-byte data register 21 in the A controller 6. At this time, the control circuit 25 activates only the data latch signal 33-i of the data latch signals 33-0 to 33-n according to the 3-bit value i (one of 0 to 7) of the byte position counter 253. To

As a result, the 1-byte data from the DMA device 4 is latched at the position of the byte i in the data register 21 (the i-th byte position). In the example of FIG. 5B, since the value (initial value) of the byte position counter 253 at the time of transferring the leading 1-byte data is “4”, the data latch signal 33-4 becomes active and The byte data is latched at the position of byte 4 in the data register 21.

When the control circuit 25 performs the latch control on the data register 21, the control byte 25 counts down the transfer byte counter 252 by 1 and the byte position counter 253 by 1.

Similarly, the DMA device 4 to the DMA
The 1-byte data transfer to the controller 6 is repeatedly performed by the transfer of the transfer request signal 31 and the transfer permission signal 32, so that the second transfer data (1 byte data) is transferred to the byte 5 position of the data register 21. 3rd transfer data at position 6 and 4 at byte 7
It is assumed that the second transfer data is latched in order.

The contents of the data register 21 at this time are shown in FIG. Note that "xx" in the figure indicates that the data is in an indefinite state, and in this example, byte 0
Each data of 3 is indefinite. Also, byte 4
"Aa" to "dd" of 7 are the first to fourth byte data of the data to be DMA-transferred to the memory 2.

When the control circuit 25 latches the fourth transfer data in the byte 7 of the data register 21, the control byte 25 counts down the transfer byte counter 252 by 1 and the byte position counter 253 by 1. At this time, the byte position counter 253
The value of changes from "7" to "0".

When the control circuit 25 detects that the value of the byte position counter 253 has changed from "7" to "0", the data is latched at the position of byte 7 of the data register 21 and transferred to the high speed bus 3. It is determined that the memory address is reached.

Then, the control circuit 25 activates the data latch signal 34 for the data buffer 22 to change the contents of the data register 21 to the data buffer 2.
Latch to 2. That is, the control circuit 25 copies the contents of the data register 21 to the data buffer 22 according to the change of the value of the byte position counter 253 from “7” to “0”.

As a result, the contents of the data buffer 22 are
As shown in FIG. 3B, the contents are the same as the contents of the data register 21 shown in FIG. At this time, "aa" to "dd" of bytes 4 to 7 of the data buffer 22 become the data to be transferred to the high speed bus 3 this time. Further, by copying the contents of the data register 21 to the data buffer 22, it becomes possible to latch subsequent data from the DMA device 4 in the data register 21.

When the control circuit 25 detects that the value of the byte position counter 253 has changed from "7" to "0" as described above, it outputs the merge control information 35 to the merge circuit 24. The merge control information 35 includes a fractional byte transfer type signal indicating whether the fractional bytes on the start side or the fractional bytes on the end side are transferred, and 3-bit boundary information indicating a merge boundary. In the case of transfer of fractional bytes on the start side, this boundary information includes the contents of the lower 3 bits of the memory address register 251 at that time, that is, the lower 3 bits of the memory start address (here, "4" indicating the value "4"). 100 ") is used, and in the case of transferring a few bytes on the end side, the contents of the byte position counter 253 are used.

The merge circuit 24 includes a control circuit 25.
When the fractional byte transfer type signal in the merge control information 35 from the above indicates transfer of fractional bytes on the start side, the value i of the 3-bit boundary information in the control information 35 (= lower 3 of the memory start address Data of bytes 0 to i−1 of the memory data register 23 and byte i of the data buffer 22 according to the bit value).
Merge the data of ~ 7.

When the fractional byte transfer type signal in the merge control information 35 indicates that the fractional byte transfer on the end side is to be performed, the merge circuit 24 determines that the 3-bit boundary information in the control information 35 is included in the merge control information 35. Value i (=
According to the value of the byte position counter 253), bytes 0 to (i-1) of the data buffer 22 and the data of bytes i to 7 of the memory data register 23 are merged.

Therefore, in the case of transferring the fractional bytes on the start side as in this example, the memory address register 2
Since the value of the lower 3 bits of the memory start address initially set to 51 is “4” (see FIG. 5B), the merge circuit 24 determines that the data of bytes 0 to 3 of the memory data register 23, That is, "00" to "33" (Fig. 3
(See (c)) and the data in bytes 4 to 7 of the data buffer 22, that is, "aa" to "dd" (see FIG. 3B), are merged to form 8 bytes (see FIG. 3D). (1 word)
Get the data (the data after the merge).

When the above merging by the merging circuit 24 is completed, the control circuit 25 outputs the transfer request signal 36 (here, the transfer request signal 36 indicating the write data transfer request) to the high-speed bus 3 again. (See Figure 4)
At the same time, the memory address obtained by replacing the lower 3 bits of the memory address indicated by the memory address register 251 with the 3-bit data of all “0” is output as the write memory address. At the same time, the merge circuit 24 transfers the 8-byte data (FIG. 3 (d)) onto the high-speed bus 3 after the merge.
(See) is output as write data.

As a result, the write memory address (memory start address) output on the high-speed bus 3 is placed on the high-speed bus 3 at the word position of the memory 2 designated by the upper address (word address) excluding the lower 3 bits. The output 8-byte write data (merged data shown in FIG. 3D) is written (rewritten), and the transfer end signal 37 is transmitted via the high-speed bus 3 to the control circuit 25 in the DMA controller 6. Transferred to.

By the above data transfer, in the transfer of the fractional bytes on the start side in which the value of the lower 3 bits of the memory start address is "4", conventionally, high-speed bus transfer for each byte of bytes 4 to 7, that is, 4 The number of high-speed bus transfers is 2 because the high-speed bus transfer is required twice, but the transfer is completed by two transfers (one read transfer and one write transfer).
You can reduce the number of times.

Note that the number of high-speed bus transfers can be reduced most compared to the conventional case when the value of the lower 3 bits of the memory start address is "1". In this case, in the past, seven transfers were required, whereas
Since the transfer is completed in two times, the number of high-speed bus transfers can be reduced by five. When the 3-bit value is "7", it is also possible to perform 1-byte high-speed bus transfer as in the conventional case so that one transfer is sufficient.
However, if both the high-speed bus width transfer and the 1-byte transfer are introduced, control and hardware configuration will be complicated.

The control circuit 25 determines the end of one DMA transfer (here, transfer of fractional bytes on the start side) by the transfer end signal 37 from the high speed bus 3 in response to the write request. In this case, the control circuit 25
The content A of the memory address register 251 is updated to A + 8. That is, the control circuit 25 updates the upper address except the lower 3 bits of the memory address held in the memory address register 251, so as to point to the next word position. The memory address register 251
Instead of, the upper address excluding the lower 3 bits of the memory start address is initialized, and a counter (word address counter) that counts up by 1 for each DMA transfer and the lower 3 bits of the memory start address are held. It is also possible to use a 3-bit register.

Thereafter, the control circuit 25 transfers the subsequent 1-byte data from the DMA device 4 to the data register 21 in the DMA controller 6 by exchanging the transfer request signal 31 and the transfer permission signal 32 with the DMA device 4. The transfer byte counter 252 is counted down by 1 and the byte position counter 253 is counted up by 1 each time.

Then, when the value of the byte position counter 253 changes from "7" to "0", the control circuit 25 latches the data at the position of byte 7 of the data register 21, and the valid data in bytes 0-7. It is determined that (8-byte data) is complete, and the contents of the register 21 are copied to the data buffer 22. Next, the control circuit 25 sends the data buffer 2 to the high-speed bus 3.
The contents of 2 are output as they are. At the same time, the control circuit 25 also outputs to the high-speed bus 3 the write transfer request signal 36 and the memory address in which the lower 3 bits of the memory address indicated by the memory address register 251 are all replaced with “0”.

To output the content of the data buffer 22 as it is, the control circuit 25 sends to the merge circuit 24 a fractional byte transfer signal indicating that the fractional bytes on the start side are transferred and the value is "0". It is sufficient to give the control information 35 consisting of the 3-bit boundary information.
Finally, the transfer of a few bytes on the end side will be described.

It is assumed that the last 1-byte data is latched in the data register 21 as a result of repeating the subsequent 1-byte data transfer from the DMA device 4 to the data register 21 in the DMA controller 6. This 1-byte data is latched at the position of byte 5 of the data register 21 in the example of the DMA transfer request data shown in FIG. At this time, the transfer byte counter 252 is counted down by 1 and its value becomes "0", and the byte position counter 253 is counted up by 1 and its value is "6" (as is apparent from FIG. 5B). It will be.

When the value of the transfer byte counter 252 becomes "0", the control circuit 25 determines that the last byte of the DMA transfer request data has been latched in the data register 21 and sets the contents of the register 21 to the data buffer 22.
To copy.

Now, the value of the byte position counter 253 when the value of the transfer byte counter 252 becomes "0",
If it is not "0" as in this example, the control circuit 2
5 judges that the transfer of a few bytes is made on the end side.

In this case, the control circuit 25 performs the same operation as in the case of transferring the fractional bytes on the start side.
The 8-byte word data indicated by the memory address register 251 is read and stored in the memory data register 23. Then, the control circuit 25 uses the merge circuit 2
4, the merge control information 35 consisting of a fractional byte transfer type signal indicating that the fractional byte transfer on the end side and 3-bit boundary information is output. In the case of transferring a few bytes on the end side, the value of the byte position counter 253 (here, “6”) is used as the 3-bit boundary information.

When the fractional byte transfer type signal in the merge control information 35 indicates that the fractional byte transfer on the end side is performed, the merge circuit 24 determines the value i of the 3-bit boundary information in the control information 35 (here Then, according to “6”), bytes 0 to i− of the data buffer 22
1 and the data in bytes i to 7 of the memory data register 23 are merged. As a result, in the example of FIG. 5B, 6 bytes of bytes 0 to 5 of the data buffer 22 and 2 bytes of bytes 6 and 7 of the memory data register 23 are merged. And 8 bytes (1 word) after this merge
Data is transferred to the memory 2 via the high-speed bus 3 and written back to the memory 2.

With the above data transfer, in the transfer of the fractional bytes on the end side where the byte position of the final 1-byte data is "5", conventionally, high-speed bus transfer for each byte of bytes 0 to 5, ie, 6 times. However, the number of high-speed bus transfers can be reduced by four because the high-speed bus transfer is required in two transfers (one read transfer and one write transfer). Here, when the byte position of the final 1-byte data is "0", it is possible to perform high-speed bus transfer of 1 byte as in the conventional case so that one transfer is sufficient.

In the above embodiment, when the value of the byte position counter 253 when the value of the transfer byte counter 252 becomes "0" is not "0", it is determined that the fractional bytes on the end side are transferred. However, the present invention is not limited to this. For example, every time one DMA transfer ends, the transfer byte counter 252 is referenced, and when the value (that is, the remaining transfer byte number) is any of “1” to “7”, the end-side fractional byte The transfer may be determined. In this case, it becomes possible to read data from the memory 2 in parallel with the transfer of the remaining byte data from the DMA device 4 to the DMA controller 6.

In the above embodiment, the DMA transfer by the DMA controller connected to the high-speed bus having a bus width (data width) of 8 bytes (64 bits) has been described, but the present invention has a high speed of other bus widths. D connected to the bus
It can also be applied to DMA transfer by the MA controller. In this case, the bus width of the high-speed bus is 2 ^n, for example. If it is a byte, an n-bit counter may be used as the byte position counter.

[0062]

As described above in detail, according to the present invention,
If there are fractional bytes less than the bus width of the high-speed bus on the start side or end side of the DMA transfer to the memory requested by the DMA device, the word data of the high-speed bus width corresponding to the transfer destination address is read from the memory. Then, the read data and the fractional bytes are merged to generate write data having a high-speed bus width, and the write data is DMA-transferred via the high-speed bus and written to the original word position of the memory. Even if fractional bytes are generated on the memory start side and the end side of the DMA transfer, the data transfer can be performed with the high speed bus width, and the use efficiency of the high speed bus and the transfer speed of the entire DMA are improved.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an information processing system including a DMA controller according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a DMA controller 6 in FIG.

FIG. 3 is a diagram showing the contents of a data register 21, a data buffer 22, and a memory data register 23 during transfer of fractional bytes on the start side, and an example of a merged result of a merge circuit 24 in comparison with each other.

FIG. 4 is a timing chart for explaining an operation during transfer of fractional bytes on the start side.

FIG. 5 is a diagram showing an example of DMA transfer request data having no fractional bytes and DMA transfer request data having fractional bytes.

[Explanation of symbols]

1 ... CPU, 2 ... Memory, 3 ... High-speed bus, 4 ... DMA device, 5 ... Low-speed bus, 6 ... DMA controller, 21 ... Data register, 22 ... Data buffer, 23 ... Memory data register, 24 ... Merge circuit, 25 ... control circuit, 251 ... memory address register, 252 ... transfer byte counter, 253 ... byte position counter.

Claims (2)

[Claims] 1. A D for controlling data transfer between a memory connected to a high speed bus and a DMA device connected to a low speed bus.
In the MA controller, which is a control means for DMA-writing write data to the memory transferred from the DMA device to the memory via the high-speed bus, the control means of the high-speed bus is provided at a start side or an end side of the DMA transfer. When there is a fractional byte less than the bus width, there is a control means for reading word data of the high-speed bus width corresponding to the transfer destination address from the memory, and the fractional byte for the data read by this control means. And a merging unit that rewrites the corresponding portion to generate write data having the high-speed bus width by means of the above-mentioned. The control unit DMA-transfers the write data generated by the merging unit via the high-speed bus. Write to the original word position of the memory. 2. The lower n bits of the memory start address of the DMA transfer to the memory (however, the high-speed bus width is 2
ⁿ Byte) is initialized and further comprises counter means for counting up each time data is transferred from the DMA device, and a memory data register for storing data of the high-speed bus width read by the control means. When transferring the fractional bytes on the start side, the merging unit replaces the data part after the position indicated by the lower n bits of the memory start address in the contents of the memory data register with the fractional bytes, and transfers the fractional bytes on the end side At times, the data portion of the contents of the memory data register before the position indicated by the count value of the counter means is replaced with the fractional bytes to generate write data of the high-speed bus width. 1. The DMA controller according to 1.