JPS63217590A - Memory access control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 4) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (a ) Description of one embodiment (Figs. 2 and 3) (b) Description of other embodiments Effects of the invention [Summary] In a memory access control system that accesses memory by supplying an address to the memory, an address register is used. A circuit that delays the contents of the address register and a switching circuit that switches the output of the delay circuit and the address register to supply it to the memory are provided, and by switching the switching circuit with a single clock mode signal, the memory can operate normally even in the single clock mode. What I did.

[Industrial application field]

The present invention relates to a memory access control method using a semiconductor memory or the like, and particularly to a memory access control method that can operate normally even in single clock mode.

Memories such as semiconductor memories are widely used as information storage means.

In such memories, an address is supplied by a clock to perform an access operation, and a high-speed access method has been developed in which the memory access time is longer than one hour for a memory visit.

Even in such an access method, it is desired that normal operation be possible during single clock mode such as diagnosis.

[Conventional technology]

FIG. 4 is an explanatory diagram of the prior art.

As shown in FIG. 4(A), the address AD for memory 2 is
An address register 1 that generates R and a read data register 3 that receives read data RD from the memory 2 are provided as part of the memory control circuit.

The timing of accessing this memory 2 is shown in Figure 4 (B).
As shown in the time chart, the address ADR output from the address register 1 is generated at clock CL "0", closes at clock CL "8", and changes to the next address.

The memory 2 is given the address ADR from the clock CL "0", and each bit of the read data RD is output from a different time due to the difference in play time of each bit of the read data RD.

That is, the bit with the minimum play time is output at time min, and the bit with the maximum play time is output at time max.

Therefore, multiple bits of read data RD are clocked at CL.
After the max time has elapsed from "0", in this example, after 7.5 clocks, all bits of data are complete and valid.

Therefore, the read data register 3 receives the clock CL"8".
The read data of the memory 2 is received using the read data clock RDC.

Therefore, read data for “n” of address ADH is transmitted from memory 2 to clock CL “7.5” (max.
) is output from the clock “9.5”, and the clock CL
"9.5" corresponds to the minimum play time when the next read address ADR "n+1" is given with the clock CL "8".

In this method, the memory access time (that is, the time from the time the read address is generated to the time the read data is received) and the memory busy time (the interval between accesses to memory 2) are the same, and the read address is read at the same time as the read address ADR is changed. Data RD is received.

In the access method shown in FIG. 4(B), if the minimum play time min for memory access exceeds one cycle time of the clock CL, the high-speed access method shown in FIG. 4(C) is used. It will be done.

That is, even if the closing timing of the address signal ADR is set to the clock CL "7", the read data register 3 can receive read data at the read data clock RDC of the clock CL "8".

As a result, the busy time of the memory can be reduced by one clock cycle, and the memory can operate at high speed.

In the access method shown in FIG. 4(C), the busy time can be smaller than the access time.

[Problem that the invention seeks to solve]

If the clock cycle of memory access is fixed as τ, there will be no problem, but when diagnosing memory etc., it is necessary to use single clock mode where the clock cycle is controlled manually from the keyboard. , the clock period may become longer.

As shown in Figure 4(D), in single clock mode,
The period of clock CL “7” and clock CL “8” is nτ
When it becomes long as shown in the figure, the address AD is
H changes and becomes 1 from 0.5 τ after the free run clock.
．． 5 After τ, the address ADH “n” paste data R
Since D becomes valid and then invalidated, even if it is synchronized with clock CL "8" or attempts to receive read data of address ADR "n" with the first data clock, it cannot be received. For this reason, there has been a problem that memory access cannot be performed normally if the busy time is shorter than the access time in the single clock mode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access control method that allows normal memory operation in single clock mode even when using an access in which the busy time is smaller than the access time.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, the same components as those shown in FIG. 4 are indicated by the same symbols, 4 is a delay circuit, and address register 1
5 is a switching circuit which receives the outputs of the address register 1 and the delay circuit 4, selects one of them according to the mode signal MS, and supplies the address to the memory 2.

[Effect]

In the present invention, since the address ADR1 of the address register 1 is supplied from the switching circuit 5 to the memory 2 in response to the mode signal MS in the normal mode, high-speed access with a busy time shorter than the access time can be realized.

On the other hand, in single clock mode, the mode signal MS
The address ADR2 of the delay circuit 4 is changed from the switching circuit 5 by
is supplied to the memory 2, the access shown in FIG. 4(B) in which the busy time and the access time are the same is performed.

Therefore, in the single clock mode, it is possible to prevent the read data from being lost before it is received, and the memory can operate normally, which can be useful for diagnosis and the like.

〔Example〕

(a) Description of one embodiment FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of one embodiment of the present invention.

In Fig. 2, the same parts as those shown in Figs. 1 and 4 are indicated by the same symbols. 6 is a sequencer, which creates memory timing using a pipeline method, and an address set. It generates a signal AS, a set signal ST, a read enable signal RES, and a mode signal MS.

Note that the delay circuit 4 is composed of a shift register, and the address register 1, shift register 4, and switching circuit 5 constitute a memory address generation circuit.

Next, the operation of the embodiment configuration shown in FIG. 2 will be explained.

The first memory access is started at clock CL "0".

That is, address ADR1 is set in address register 1 by address sent signal AS and output to switching circuit 5.

At this time, if the single clock mode is not instructed, the mode is the normal mode, so the mode signal MS of the sequencer 6 is "low" and the address register 1 is connected to the memory 2.

Therefore, the output address ADRI of the address register 1 is supplied to the memory 2 via the switching circuit 5, and the memory 2 starts the continuous readout operation.

On the other hand, the output address ADR1 of the address register 1 is also supplied to the shift register 4, and a set signal ST which is one clock slower than the address sent signal AS of the sequencer 6 is supplied.
This causes the shift register 4 to shift this address signal by one stage from ADR1 and input it to the switching circuit 5 (with a delay of one clock).

When a single clock mode instruction is given to the sequencer 6 at the time of the clock CL "5", the mode signal MS becomes "high", the switching circuit 5 is switched, and the shift register 4 is connected to the memory 2.

As a result, the memory 2 is supplied with the address output ADR2 of the shift register 4 (that is, the address output ADR1 of the address register I delayed by one clock).

The second memory access is started at clock CL "7".

In other words, the access busy time is 7 as shown in Figure 4(C).
It's Kurosoku.

When the clock CL has elapsed for seven clocks, the sequencer 6 applies an address set signal AS to the address register 1, and sets and outputs the next address ADR1''n+1''. At this time, the switching circuit 5 selects the address A of the shift register 4.
Since DR2 is selected, the address supplied to memory 2 remains "n".

At clock CL "8", the sequencer 6 issues a read enable signal RES (read clock RDC(n)) to the read data register 3, whereby read data RD from the memory 2 is set in the read data register 3.

Therefore, the access time is 8 clocks as in FIG. 4(C).

At the same time, the sequencer 6 applies a set signal ST to the shift register 4, sets the output address ADR1 of the address register 1, and the output address ADR2 of the shift register 4 changes to n+1''.

As a result, the address ADR given to memory 2 is “
n+1''.

At this time, since it is a single clock state, read data RD (n+1
) is determined before the clock CL "9" is generated.

When the single clock mode instruction is canceled by the clock CL "10" and the mode returns to normal mode, the sequencer 6 sets the mode signal MS to "low", connects the memory 2 to the address register 1, and transfers the address of the address register 1 to the memory 2. Supply ADRI.

The second access ends at clock CL "14", and the read data register 3 receives the second read data RD (n+1) at clock CL "15".

At this time, because it is in normal mode, read clock RDC (n+
The address changes one clock before 1).

In this way, even if you switch to single clock mode during normal mode operation where the busy time is smaller than the access time, the address is switched to a delayed one, preventing the read data for the address from being lost. can.

That is, in the single clock mode, for example, when a person presses the keyboard, the clock CL is generated once, and the cycle of the clock CL is arbitrary and long. Even in such a case, read data cannot be retrieved by memory access operation. The original function of the single clock mode of diagnosing the contents of the memory every time the clock CL advances can be used without any loss.

(b) Description of other embodiments In the embodiments described above, a shift register is used as a delay circuit, but a simple latch circuit may also be used. However, when reducing the busy time by n clocks in FIG. 4(B), it is sufficient to shift by one stage.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, even if the memory access time is set to be longer than one memory busy hour and high-speed access is performed, the memory busy time does not increase and the memory operates normally even in single clock mode. It is possible to realize excellent memory access in which high-speed access is possible in the normal mode and accurate memory data can be obtained in the single-clock mode.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the prior art. In the figure, 1--address register, 2--memory, 3--read data register, 4--delay circuit, 5--switching circuit.

Claims (1)

[Claims] In a memory access control method in which an address of an address register (1) is supplied to a memory (2) to access the memory (2), a delay circuit (4) that delays the address of the address register (1) is provided. ), the outputs of the address register (1) and the delay circuit (4) are input, and one of them is selected according to the mode signal,
A switching circuit (5) that supplies an address to the memory (2) is provided, and in normal mode the output of the address register (1) is connected to the output of the delay circuit (4) in the single clock mode. 2) A memory access control method characterized by supplying.