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JPS63215084A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

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Publication number
JPS63215084A
JPS63215084A JP62047597A JP4759787A JPS63215084A JP S63215084 A JPS63215084 A JP S63215084A JP 62047597 A JP62047597 A JP 62047597A JP 4759787 A JP4759787 A JP 4759787A JP S63215084 A JPS63215084 A JP S63215084A
Authority
JP
Japan
Prior art keywords
semiconductor layer
substrate
semiconductor
layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62047597A
Other languages
Japanese (ja)
Inventor
Kazuo Fukuoka
福岡 和雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62047597A priority Critical patent/JPS63215084A/en
Publication of JPS63215084A publication Critical patent/JPS63215084A/en
Pending legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To control the concentrations of a semiconductor layer, wherein a P-N junction and guard rings are formed, and a semiconductor layer having a concentration lower than that of this semiconductor layer with high precision and to improve the yield of the title element by a method wherein both semiconductor layers are formed as a substrate through a joint layer. CONSTITUTION:A P<--> semiconductor layer 2 is deposited on the surface of a P<+> Si substrate 1 and the surface is mirror-polished. Then, the surface of a P<-> Si semiconductor substrate 3 prepared separately from the substrate 1 is mirror-polished and the layer 2 and the substrate 3 are closely bonded to each other to form a composite semiconductor substrate. Subsequently, a thermal oxide film 5 is formed on the surface of the substrate 3 and after apertures are provided at the programming positions for forming guard rings, deposition of of a BSG film 7 and diffusion of B are performed to form the guard rings 6. Then, an annular channel stopper 9 and an N<+> region 10 are formed and a passivation film 11 and a rear electrode 12 are provided to complete an avalanche photo diode.

Description

【発明の詳細な説明】 〈発明の目的〉 (産業上の利用分野) 本発明は光通信の受光素子として利用されて、高速応答
ならびに増幅作用を発揮するアバランシェフォトダイオ
ードの改良に係る。
DETAILED DESCRIPTION OF THE INVENTION <Object of the Invention> (Industrial Application Field) The present invention relates to an improvement in an avalanche photodiode that is used as a light receiving element in optical communications and exhibits high-speed response and amplification.

(従来の技術) 高速での応答ならびに増幅作用を行うアバランシェフォ
トダイオードは最近では600nm〜11000n特に
800nmの波長を放射する光源に対する受光素子即ち
光通信用としての用途が拡大している。
(Prior Art) Avalanche photodiodes, which provide high-speed response and amplification, have recently been increasingly used as light-receiving elements for light sources that emit wavelengths of 600 nm to 11,000 nm, especially 800 nm, that is, for optical communications.

このアバランシェフォトダイオードの構成を第2図によ
り説明すると、Bを含有し比抵抗が約5膳Ω−cmのP
+半導体基板20を準備する。と言うのはこのダイオー
ドで必要とする良好な雑音特性は半導体単結晶における
イオン化率比によって決まる。
The structure of this avalanche photodiode will be explained with reference to FIG. 2.
+Prepare the semiconductor substrate 20. This is because the good noise characteristics required for this diode are determined by the ionization rate ratio in the semiconductor single crystal.

SLでは、電子のイオン化率が正孔のイオン化率より高
く、アバランシェ増幅領域の少数キャリアとして電子を
選ぶ必要があるため通常P導電型の半導体基板を適用す
る。
In SL, since the ionization rate of electrons is higher than the ionization rate of holes, and it is necessary to select electrons as minority carriers in the avalanche amplification region, a P conductivity type semiconductor substrate is usually used.

このP″″半導体基板20には通常のエピタキシャル成
長法によってBを含み、比抵抗が100〜300Ω−c
■のP−半導体層21を堆積し、更に増幅層として機能
するP−半導体層22を矢張りエピタキシャル成長法に
よって堆積する。このP−半導体層の比抵抗は、10〜
20Ω−amであり不純物としてBを含有する。
This P″″ semiconductor substrate 20 contains B by a normal epitaxial growth method, and has a specific resistance of 100 to 300Ω-c.
A P-semiconductor layer 21 is deposited, and a P-semiconductor layer 22 functioning as an amplification layer is further deposited by an epitaxial growth method. The specific resistance of this P-semiconductor layer is 10~
It is 20Ω-am and contains B as an impurity.

このp−半導体層の形成に先立ってP−半導体層21に
はP+埋込層23を通常の手法で設置する。具体的には
、このP−半導体層21表面を被覆する絶縁物層の所定
位置を開口して、露出するP″″半導体層21内にBを
ドーズ量2 X 10”/cm”程度注入するか。
Prior to forming this p-semiconductor layer, a P+ buried layer 23 is provided in the P-semiconductor layer 21 by a conventional method. Specifically, a predetermined position of the insulating layer covering the surface of the P-semiconductor layer 21 is opened, and B is injected into the exposed P'' semiconductor layer 21 at a dose of approximately 2 x 10''/cm''. mosquito.

このマスクとして、レジストを利用しても良く。A resist may be used as this mask.

又気相拡散でも差支えない。Also, vapor phase diffusion may be used.

このP−半導体層22にはガードリング24、チャンネ
ルストッパー25ならびにN4′領域26の形成工程に
移る。先ずP−半導体層22の表面には通常の熱酸化法
によって絶縁膜27を被覆後、P+ガードリング24の
設置予定位置を開口し、ここにBSG膜2膜製8積パタ
ーニングしてから含有するBを固相拡散して10101
9ato/cc程度の表面濃度に形成する。
A guard ring 24, a channel stopper 25, and an N4' region 26 are formed on this P-semiconductor layer 22. First, the surface of the P- semiconductor layer 22 is coated with an insulating film 27 by a normal thermal oxidation method, and then an opening is made at the position where the P+ guard ring 24 is planned to be installed, and two BSG films are patterned in eight layers and then contained. 10101 by solid phase diffusion of B
It is formed at a surface concentration of about 9ato/cc.

次に絶縁膜27の所定位置即ちチャンネルストッパー2
5の位置に対応する部分を除去してからPAsSG膜2
8を膜面8ターニング後含有するPならびにAsを固相
拡散して表面濃度約10”atoms/ccのチャンネ
ルストッパー25を形成する。
Next, the predetermined position of the insulating film 27, that is, the channel stopper 2
After removing the portion corresponding to position 5, PAsSG film 2
After turning the membrane surface 8, P and As containing P and As are solid phase diffused to form a channel stopper 25 having a surface concentration of about 10'' atoms/cc.

次にN+領域26に相当する絶縁膜27を溶除して新た
にPAsSG膜28を膜面8ターニングして、含有する
P、Asを拡散して約10”、atoms/ccのN+
領域26を形成する。ただし、このN+領域26の拡散
深さ4よチャンネルストッパー25のそれより相当水さ
い。    −更にFinal Pa5sivatio
n用としてUndop6のCVD被膜29を堆積して、
更にP+半導体基板20の裏面に電極30を設けてアバ
ランシェフォトダイオードを完成する。
Next, the insulating film 27 corresponding to the N+ region 26 is dissolved and a new PAsSG film 28 is turned by 8 film surfaces, and the contained P and As are diffused to form an N+ of about 10" atoms/cc.
A region 26 is formed. However, the diffusion depth 4 of this N+ region 26 is considerably deeper than that of the channel stopper 25. -More Final Pa5sivatio
A CVD film 29 of Undop6 was deposited for n,
Further, an electrode 30 is provided on the back surface of the P+ semiconductor substrate 20 to complete an avalanche photodiode.

(発明が解決しようとする問題点) このアバランシェフォトダイオードでは光吸収層ならび
に増幅層として動作するP−半導体層21及びP−半導
体層22を夫々エピタキシャル成長法によって独立に設
計できる利点を持っている反面、これらの各半導体層濃
度ならびに厚さはこの成長法によって決定される。
(Problems to be Solved by the Invention) This avalanche photodiode has the advantage that the P-semiconductor layer 21 and the P-semiconductor layer 22, which operate as a light absorption layer and an amplification layer, can be designed independently by epitaxial growth. , the concentration and thickness of each of these semiconductor layers are determined by this growth method.

しかも、この各半導体層21.22ならびにP+の埋込
層23は何れも濃度差が大きいので、このエピタキシャ
ル成長工程時にAuto dopingが発生し、 P
−もしくはP−半導体層にいわゆるミスフィツトが発生
し、これによる局部的なブレークダウンが起り、歩留り
が悪化する難点がある。更には、濃度制御の問題等によ
って動作電圧ならびに雑音特性の悪化をもたらして同じ
く歩留りが低下する。
Moreover, since the semiconductor layers 21, 22 and the P+ buried layer 23 have a large concentration difference, auto doping occurs during the epitaxial growth process, and the P+ buried layer 23 has a large concentration difference.
- or P- There is a problem in that so-called misfit occurs in the semiconductor layer, and this causes local breakdown, which deteriorates the yield. Furthermore, problems with concentration control and the like cause deterioration in operating voltage and noise characteristics, which also lowers yield.

本発明は上記欠点を除去する新規な半導体受光素子を提
供することを目的とする。
An object of the present invention is to provide a novel semiconductor light-receiving device that eliminates the above-mentioned drawbacks.

〈発明の構成〉 (問題点を解決するための手段) この目的を達成するために、本発明ではP+半導体基板
にP″″−半導体層をエピタキシャル法によって形成し
、一方用意したP″″半導体基板に設ける鏡面と、この
p−半導体層表面に形成する鏡面を接合して、単一の半
導体基板を構成しこのP−半導体層にN+領領域チャン
ネルストッパーならびにガードリングを形成する手法を
採用する。
<Structure of the Invention> (Means for Solving the Problems) In order to achieve this object, in the present invention, a P''''- semiconductor layer is formed on a P+ semiconductor substrate by an epitaxial method, and a P'''' semiconductor layer prepared on the other hand is A method is adopted in which a mirror surface provided on the substrate and a mirror surface formed on the surface of this p-semiconductor layer are bonded to form a single semiconductor substrate, and an N+ region channel stopper and guard ring are formed on this p-semiconductor layer. .

(作 用) ところで、含有不純物に濃度差があり、同種の導電型も
しくは導電型の相違する半導体基板を接合して一体化す
る技術はすでに開発されているが、この技術を半導体受
光素子に適用すると、その増幅作用ならびに雑音特性を
格段に向上し、その歩留りを改善する事実を基に本発明
は完成したものである。
(Function) By the way, a technology has already been developed for bonding and integrating semiconductor substrates that have different concentrations of impurities and are of the same type or different conductivity type, but this technology cannot be applied to semiconductor photodetectors. The present invention has been completed based on the fact that the amplification effect and noise characteristics are significantly improved and the yield is improved.

(実施例) 第1図により本発明に係る実施例を詳細するが、従来の
技術欄と重複する記載にも新番号を付して説明する。
(Example) An example according to the present invention will be described in detail with reference to FIG. 1, and new numbers will be assigned to descriptions that overlap with those in the conventional technology section.

Bを含有し比抵抗が5mΩ−cm位のP”Si半導体基
板1を用意し、その表面にBを含み比抵抗として100
〜300Ω−cIlのP−半導体層2を30〜40μm
堆積する。この堆積は公知のエピタキシャル成長法を利
用し、この時発生するAuto dopingは高々約
5μ腫であるので問題でない、一方矢張りBを含有して
比抵抗が10〜20Ω−ellのP−3i半導体基板3
を準備後前述の接合工程に移行する。
A P"Si semiconductor substrate 1 containing B and having a specific resistance of about 5 mΩ-cm is prepared, and the surface thereof contains B and has a specific resistance of 100 mΩ-cm.
~300Ω-cIl P-semiconductor layer 2 with a thickness of 30-40 μm
accumulate. This deposition is performed using a known epitaxial growth method, and the auto doping that occurs at this time is at most about 5 μm, so it is not a problem. 3
After preparation, proceed to the above-mentioned bonding process.

このP″″−半導体層2ならびにI”Si半導体基板3
の表面を研磨して粗さ500Å以下の鏡面とし、この研
磨工程後の表面状態によって前処理工程によって油脂分
等を溶除する。次いで清浄な水で数分程度水洗してから
、スピンナー処理のような脱水処理により前記鏡面に吸
着していると想定される水分はそのまま残し、過剰な水
分を除去するが、この吸着水分が殆んど揮散する100
0℃以上の加熱乾燥は避ける。
This P″″-semiconductor layer 2 and I″Si semiconductor substrate 3
The surface is polished to a mirror surface with a roughness of 500 Å or less, and depending on the surface condition after this polishing process, oils and fats are dissolved out in a pretreatment process. Next, after rinsing with clean water for several minutes, excess moisture is removed by dehydration treatment such as spinner treatment, leaving the moisture that is assumed to have been adsorbed on the mirror surface as it is. 100 evaporates
Avoid heating and drying above 0℃.

この処理を経たP−5i半導体基板3及びP−半導体層
2を例えばクラス1以下の清浄な大気雰囲気に設定して
、前記鏡面間に異物(ゴミ)が実質的に介在しない状態
で相互に密着接合して複合半導体基板を形成する。この
複合半導体基板を200℃以上好ましくは1000℃乃
至2000℃に加熱処理して接合強度を増すこともでき
、接合工程時の雰囲気としては大気のほかに、酸素もし
くは両者の混合雰囲気も適用可能であり、接合強度を増
す場合にもこれらの雰囲気は採用可能である。
The P-5i semiconductor substrate 3 and the P-semiconductor layer 2 that have undergone this treatment are placed in a clean atmosphere of class 1 or lower, for example, and are brought into close contact with each other with substantially no foreign matter (dust) intervening between the mirror surfaces. A composite semiconductor substrate is formed by bonding. This composite semiconductor substrate can be heat-treated at 200°C or higher, preferably 1000°C to 2000°C, to increase the bonding strength, and the atmosphere during the bonding process can be air, oxygen, or a mixture of both. These atmospheres can also be used to increase bonding strength.

ところで、この接合工程では前記鏡面に対する水洗工程
によって極性基が形成され、これによる結合によってB
ulkM織と異なる接合層4が生ずるために複合半導体
基板が得られると想定される。
By the way, in this bonding process, polar groups are formed by the water washing process on the mirror surface, and the bonding caused by this causes B
It is assumed that a composite semiconductor substrate is obtained because a bonding layer 4 different from the ulkM weave is formed.

この接合層4は付加する熱負荷に応じてその境界が変動
することも考えられるので、本発明ではその境界を画然
と区分することだけを意味するものでなく、この変動状
態を包含するものである。
Since the boundary of this bonding layer 4 may change depending on the applied heat load, the present invention does not only mean clearly dividing the boundary, but also includes this changing state. It is.

この複合半導体基板の表面即ちP−半導体基板3表面か
ら内部に向けてガードリング6、チャーンネルストッパ
ー9ならびにN+領域10の形成工程に入る。
A step of forming a guard ring 6, a channel stopper 9, and an N+ region 10 starts from the surface of this composite semiconductor substrate, that is, the surface of the P- semiconductor substrate 3 toward the inside.

このP〜半導体基板表面には通常の手法によって熱酸化
膜5を形成し、環状のピガードリング形成予定位置に対
応する位置を公知の写真食刻法によって開口し、BSG
膜7を堆積してパターニングを施し、含有するBを固相
拡散して1’O”atoms/cc程度の表面濃度とし
てガードリング6を形成する。
A thermal oxide film 5 is formed on the surface of this P ~ semiconductor substrate by a normal method, and an opening is made by a known photolithography method at a position corresponding to the position where an annular Pigard ring is to be formed.
A film 7 is deposited and patterned, and B contained therein is diffused in a solid phase to form a guard ring 6 at a surface concentration of about 1'O'' atoms/cc.

次にN“チャンネルストッパー9の形成予定位置に対応
する熱酸化膜7を常法に従って除去して露出するP″″
半導体基板にPAsSG膜8S被膜し、更にパターニン
グを行ってからP及びAsを拡散して表面濃度約101
9atoa+s/cc程度の環状チャンネルストッパー
9を形成する。
Next, the thermal oxide film 7 corresponding to the planned formation position of the N" channel stopper 9 is removed and exposed using a conventional method.
A PAsSG film 8S is coated on a semiconductor substrate, and after further patterning, P and As are diffused to a surface concentration of about 101.
An annular channel stopper 9 of approximately 9 atoa+s/cc is formed.

引続いてこのチャンネルストッパー9の中間位置に形成
されるN+領域10に対応する熱酸化膜5及びPAsS
G層を除去してから、新たにPAsSG層を被覆パター
ニングしてからこのP及びAsを同相拡散してN4″領
域10を設ける。このN+領域10の深さはチャンネル
ストッパー9のそれより遥かに小さくかつ互に連続する
形状となり、Pの含有量はAsの含有量より大きい。
Subsequently, the thermal oxide film 5 and PAsS corresponding to the N+ region 10 are formed at the middle position of this channel stopper 9.
After removing the G layer, a new PAsSG layer is coated and patterned, and the P and As are in-phase diffused to form the N4'' region 10. The depth of the N+ region 10 is far greater than that of the channel stopper 9. The shape is small and continuous, and the P content is larger than the As content.

更にFinal Pa5sivation層11として
Undope CVD被膜11を堆積し、又P+半導体
基板の裏面にAu−V−Ni電極12を設けてアバラン
シェフォトダイオードを完成する。
Further, an undoped CVD film 11 is deposited as a final Pa5sivation layer 11, and an Au-V-Ni electrode 12 is provided on the back surface of the P+ semiconductor substrate to complete an avalanche photodiode.

〈発明の効果〉 アバランシェフォトダイオードの重要な特性である動作
電圧と雑音特性は光吸収層として機能するp−成長半導
体層のパンチスルー電圧、降伏電圧及び動作電圧印加時
における増幅層即ちP−半導体基板の電圧強度に依存す
る。しかし、これらの諸特性を決めるのはこの両層によ
って得られる濃度プロファイルであるが、本発明は接合
技術の採用によって設計値に極めて近い構造が得られる
ために、この特性を満す素子が歩留り良く形成可能とな
った。
<Effects of the Invention> The operating voltage and noise characteristics, which are important characteristics of an avalanche photodiode, are determined by the punch-through voltage and breakdown voltage of the p-grown semiconductor layer, which functions as a light absorption layer, and the amplification layer, that is, the p-semiconductor, when the operating voltage is applied. Depends on the voltage strength of the board. However, it is the concentration profile obtained by these two layers that determines these characteristics, and since the present invention uses bonding technology to obtain a structure that is extremely close to the design value, devices that satisfy these characteristics have a high yield. It became possible to form it well.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体受光素子の断面図、第2図
はその従来構造を示す断面図である。
FIG. 1 is a sectional view of a semiconductor light receiving element according to the present invention, and FIG. 2 is a sectional view showing its conventional structure.

Claims (1)

【特許請求の範囲】[Claims] ある導電型を示す半導体基板と、この表面に設ける低濃
度のある導電型成長半導体層と、この成長半導体層なら
びに前記半導体基板の中間濃度をもち、この成長半導体
層に積層するある導電型半導体層と、このある導電型半
導体層及び前記ある導電型の成長半導体層の境界に設け
る接合層と、前記ある導電型半導体層表面から内部に向
けて形成する反対導電型領域と、この反対導電型領域な
らびに前記ある導電型半導体層間に形成するPN接合を
囲んで設けるガードリングとを具備することを特徴とす
る半導体受光素子。
A semiconductor substrate exhibiting a certain conductivity type, a grown semiconductor layer of a conductivity type with a low concentration provided on the surface of the semiconductor substrate, and a semiconductor layer of a certain conductivity type having a concentration intermediate between the grown semiconductor layer and the semiconductor substrate and laminated on the grown semiconductor layer. a bonding layer provided at the boundary between the semiconductor layer of a certain conductivity type and the grown semiconductor layer of the certain conductivity type; a region of the opposite conductivity type formed from the surface of the semiconductor layer of the certain conductivity type inward; and a region of the opposite conductivity type. and a guard ring provided surrounding the PN junction formed between the certain conductivity type semiconductor layers.
JP62047597A 1987-03-04 1987-03-04 Semiconductor photodetector Pending JPS63215084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62047597A JPS63215084A (en) 1987-03-04 1987-03-04 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62047597A JPS63215084A (en) 1987-03-04 1987-03-04 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPS63215084A true JPS63215084A (en) 1988-09-07

Family

ID=12779654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62047597A Pending JPS63215084A (en) 1987-03-04 1987-03-04 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPS63215084A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284711A (en) * 1997-04-10 1998-10-23 Hamamatsu Photonics Kk Light-receiving semiconductor device with built-in bicmos
JPH11230784A (en) * 1998-02-12 1999-08-27 Hamamatsu Photonics Kk Optical encoder
WO2005074043A1 (en) * 2004-01-16 2005-08-11 Eastman Kodak Company High photosensitivity cmos image sensor pixel architecture
EP2013915A1 (en) * 2006-04-19 2009-01-14 Perkinelmer Optoelectronics, Inc. Bonded wafer avalanche photodiode and method for manufacturing same
US8368159B2 (en) 2011-07-08 2013-02-05 Excelitas Canada, Inc. Photon counting UV-APD
CN108630780A (en) * 2017-03-15 2018-10-09 株式会社东芝 Photodetector

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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