[go: up one dir, main page]

JPS63213362A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPS63213362A
JPS63213362A JP62045841A JP4584187A JPS63213362A JP S63213362 A JPS63213362 A JP S63213362A JP 62045841 A JP62045841 A JP 62045841A JP 4584187 A JP4584187 A JP 4584187A JP S63213362 A JPS63213362 A JP S63213362A
Authority
JP
Japan
Prior art keywords
island
semiconductor
semiconductor device
resin
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62045841A
Other languages
Japanese (ja)
Inventor
Tatsuhiko Akiyama
龍彦 秋山
Osamu Nakagawa
治 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62045841A priority Critical patent/JPS63213362A/en
Publication of JPS63213362A publication Critical patent/JPS63213362A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable dispersion or relaxation of a stress generated in a semiconductor device, and obtain a stable quality wherein anti-stress properties are improved, by providing the whose rear of an island with an uneven surface or plural holes. CONSTITUTION:The whose rear of an island 3, on which a semiconductor element 2 is mounted, is provided with an uneven surface or a plurality of holes. Semiconductor sealing resin 6 is a solid at a room temperature, and turns into a liquid in a semiconductor sealing mold at a high temperature, so that it can easily penetrate into the inside of an unevenness 7 formed on the rear of the island 3. Accordingly, even if a shearing force or a tensile force generates between the rear surface of the island 3 and the semiconductor shielding resin 6 when the resin is solidified, the stress is dispersed by the wedge effect of the unevenness 7, and the breakdown of a bonding surface hardly generates. Thereby, the resistance against a thermal stress of the whole part of a semiconductor device 1 can be increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は樹脂封止型半導体装置に関し、特に該装置に
使用されるリードフレームの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to improvements in lead frames used in the device.

〔従来の技術〕[Conventional technology]

第4図は従来の樹脂封止型半導体装置を示す断面図であ
り、図において、1は樹脂封止型半導体装置、2は半導
体素子でアイランド3に接着され、インナーワイヤ4に
より外部リード5と電気的に導通されている。これらの
材料は半導体封止樹脂6で封止され、外部環境から保護
されている。半導体装置用リードフレームは半導体素子
2を搭載・保持するアイランド3と外部リード5および
外枠で構成される。
FIG. 4 is a sectional view showing a conventional resin-sealed semiconductor device. In the figure, 1 is a resin-sealed semiconductor device, 2 is a semiconductor element, which is bonded to an island 3, and is connected to an external lead 5 by an inner wire 4. electrically conductive. These materials are sealed with semiconductor sealing resin 6 and protected from the external environment. A lead frame for a semiconductor device is composed of an island 3 on which a semiconductor element 2 is mounted and held, an external lead 5, and an outer frame.

従来のリードフレームを製造するには、アイランド3上
に半導体素子2を搭載し、インナーワイヤ4により半導
体素子2と外部リード5とを電気的に接続し、その後、
半導体封止樹脂6にて成形封止・絶縁される。このトラ
ンスファー成形は通常180℃前後で行なわれる。上記
プロセスで製造される半導体装置は、一般に異なる線膨
張係数をもつ材料で構成される。例えば半導体用リード
フレームとして4270イを用いる場合、その熱線膨張
係数は3.5 X 10−6 /’Cであるのに対し、
シリコンを用いた半導体素子は2.3 X 10−6 
/l、半導体封止樹脂は20X10″″6/’C前後で
ある。
To manufacture a conventional lead frame, the semiconductor element 2 is mounted on the island 3, the semiconductor element 2 and the external leads 5 are electrically connected by the inner wire 4, and then,
It is molded and sealed and insulated with semiconductor sealing resin 6. This transfer molding is usually carried out at around 180°C. Semiconductor devices manufactured by the above process are generally made of materials having different coefficients of linear expansion. For example, when using 4270I as a semiconductor lead frame, its coefficient of linear thermal expansion is 3.5 x 10-6 /'C;
Semiconductor elements using silicon are 2.3 x 10-6
/l, and the semiconductor sealing resin is around 20×10″″6/′C.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の樹脂封止型半導体装置は以上のように構成されて
いるので、トランスファー成形温度から室温への冷却時
、あるいはプリント基板実装時や半導体素子の動作発熱
等、温度ストレスが半導体装置に印加した場合、線膨張
係数が異なる複合材料で構成された半導体装置にはそれ
ぞれの材料に圧縮応力、剪断応力等の内部ストレスが発
生する。
Conventional resin-sealed semiconductor devices are configured as described above, so thermal stress is not applied to the semiconductor device, such as during cooling from transfer molding temperature to room temperature, mounting on a printed circuit board, or heat generation during operation of semiconductor elements. In this case, internal stresses such as compressive stress and shear stress occur in a semiconductor device made of composite materials having different coefficients of linear expansion in each material.

複合材料において内部応力が発生した場合、各材料に加
わる応力は各材料の形状及び各材料間の接着力に大きく
依存する。半導体装置を構成する材料のうちグイパッド
・半導体封止樹脂間の接着力は半導体素子・半導体封止
樹脂間の接着力よりも弱いため、温度ストレスにより半
導体装置内部に発生した応力(剪断応力及び引張応力)
が、アイランド・半導体封止樹脂間の接合を破壊して全
ての応力がアイランド下端部に集中し、場合によっては
材料破壊、接着破壊を生ずる等の問題があった。   
゛ [問題点を解決するための手段〕 この発明に係る樹脂封止型半導体装置は、半導体素子が
搭載されるアイランドの裏面全面に凹凸面又は複数の穴
を設けたものである。
When internal stress occurs in a composite material, the stress applied to each material largely depends on the shape of each material and the adhesive force between each material. Among the materials that make up a semiconductor device, the adhesive force between the Guipad and the semiconductor encapsulating resin is weaker than the adhesive force between the semiconductor element and the semiconductor encapsulating resin, so the stress (shear stress and tensile stress) generated inside the semiconductor device due to temperature stress stress)
However, the bonding between the island and the semiconductor sealing resin is destroyed, and all the stress is concentrated at the lower end of the island, resulting in problems such as material failure and adhesive failure in some cases.
[Means for Solving the Problems] A resin-sealed semiconductor device according to the present invention has an uneven surface or a plurality of holes provided on the entire back surface of an island on which a semiconductor element is mounted.

〔作用〕[Effect]

この発明においては、アイランドの裏面全面に凹凸面又
は複数の穴を設けたので、凹凸の段差部分又は穴に半導
体封止樹脂が侵入し、その喰い込み効果によりアイラン
ド・半導体封止樹脂間に発生する剪断力及び引張力を分
散してアイランド端部への応力集中を回避することがで
きる。
In this invention, since an uneven surface or a plurality of holes are provided on the entire back surface of the island, the semiconductor encapsulating resin penetrates into the uneven step part or hole, and the biting effect causes generation between the island and the semiconductor encapsulating resin. By dispersing the shearing force and tensile force caused by the island, stress concentration at the island end can be avoided.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例による樹脂封止型半導体装
置を示し、図において、1は樹脂封止型半導体装置、2
は半導体素子で、アイランド3に接着され、インナーワ
イヤ4により外部リード5と電気的に導通されている。
FIG. 1 shows a resin-sealed semiconductor device according to an embodiment of the present invention. In the figure, 1 indicates a resin-sealed semiconductor device, and 2
is a semiconductor element, which is bonded to the island 3 and electrically connected to the external lead 5 through an inner wire 4.

これらの材料は半導体封止樹脂6で封止され外部環境か
ら保護されている。7はアイランド裏面表面に設けた凹
凸である。半導体装置用リードフレームは半導体素子を
搭載・保持するアイランド3と、外部リード5及び外枠
で構成される。アイランド3上に半導体素子を搭載しイ
ンナーワイヤ4により半導体素子2と外部リード5とを
電気的に接続した半導体装置用リードフレームは半導体
封止樹脂6により成形。
These materials are sealed with semiconductor sealing resin 6 and protected from the external environment. Reference numeral 7 indicates unevenness provided on the back surface of the island. A lead frame for a semiconductor device is composed of an island 3 for mounting and holding a semiconductor element, external leads 5, and an outer frame. A lead frame for a semiconductor device in which a semiconductor element is mounted on an island 3 and the semiconductor element 2 and external leads 5 are electrically connected by an inner wire 4 is molded with a semiconductor sealing resin 6.

封止、絶縁される。このトランスファー成形は通常18
0℃前後で行なわれる。
Sealed and insulated. This transfer molding is usually 18
It is carried out at around 0°C.

次に、本実施例装置の作用・効果について説明する。室
温で固体である半導体封止樹脂6は、高温の半導体封止
金型内で数1oocpsの粘度の液体となるので、容易
にアイランド裏面表面上に形成されている凹凸7の内部
に侵入する。従って、半導体封止樹脂6を硬化させた時
、アイランド3の裏面表面と半導体封止樹脂6との間に
剪断力又は引張力が発生しても、凹凸7のくさび効果に
より応力が分散され、接着界面の破壊が生じにくくなる
Next, the functions and effects of the device of this embodiment will be explained. The semiconductor encapsulation resin 6, which is solid at room temperature, becomes a liquid with a viscosity of several 10ocps in the high-temperature semiconductor encapsulation mold, and therefore easily penetrates into the inside of the unevenness 7 formed on the back surface of the island. Therefore, even if shearing force or tensile force is generated between the back surface of the island 3 and the semiconductor encapsulating resin 6 when the semiconductor encapsulating resin 6 is cured, the stress is dispersed due to the wedge effect of the unevenness 7. Breakage of the adhesive interface becomes less likely to occur.

このような本実施差例では、半導体装置内部にストレス
が発生した場合でも、従来構造では最も弱かった、アイ
ランド裏面表面・半導体封止樹脂間の耐熱ストレス性が
向上したことによって半導体装置全体の耐熱ストレス性
を向上することができる。
In this implementation difference example, even if stress occurs inside the semiconductor device, the heat resistance of the entire semiconductor device is improved by improving the heat stress resistance between the back surface of the island and the semiconductor sealing resin, which was the weakest in the conventional structure. Stress resistance can be improved.

なお、上記実施例では、アイランド裏面表面に凹凸を形
成した場合について示したが、これは第2図のように、
その開孔径Bがその内部の径Aよりも小さい複数個の凹
状の穴8であってもよく、この場合でも上記実施例と同
様にアイランド3裏面表面と半導体封止樹脂6の横方向
の剪断応力に対する耐性が向上するばかりでなく、縦方
向の引張り応力に対する耐性も向上することとなり、耐
熱ストレス性を向上することができる。
In the above example, the case where unevenness was formed on the back surface of the island was shown, but this is as shown in Fig. 2.
It may be a plurality of concave holes 8 whose opening diameter B is smaller than the internal diameter A, and in this case, as in the above embodiment, the back surface of the island 3 and the semiconductor sealing resin 6 are sheared in the lateral direction. Not only the resistance to stress is improved, but also the resistance to tensile stress in the longitudinal direction is improved, and the heat stress resistance can be improved.

また上記実施例の凹凸のかわりに、第3図に示すような
、その開口径が深さ方向に増大するテーパ状(COD)
の複数個の貫通穴であってもよく、この場合でも上記実
施例と同様の効果を奏する。
In addition, instead of the unevenness of the above embodiment, a tapered shape (COD) in which the opening diameter increases in the depth direction as shown in FIG. 3 is used.
A plurality of through holes may be used, and the same effects as in the above embodiment can be achieved in this case as well.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明に係る樹脂封止型半導体装置によ
れば、アイランド裏面全面に凹凸面又は複数の穴を設け
たので、アイランド裏面表面と半導体封止樹脂との界面
に発生する内部応力を機械的に補強し、分散することが
でき、これにより外部環境の変化に伴い半導体装置内部
に発生する応力の分散あるいは緩和が可能になり、耐応
力性を高め安定した品質を得ることができる効果がある
As described above, according to the resin-sealed semiconductor device according to the present invention, since the uneven surface or the plurality of holes are provided on the entire back surface of the island, the internal stress generated at the interface between the back surface of the island and the semiconductor sealing resin is reduced. It can be mechanically reinforced and dispersed, making it possible to disperse or alleviate the stress that occurs inside semiconductor devices due to changes in the external environment, increasing stress resistance and providing stable quality. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による樹脂封止型半導体装
置を示す断面図、第2図及び第3図はこの発明の他の実
施例による樹脂封止型半導体装置を示す断面図、第4図
は従来装置を示す断面図である。 図において、1は樹脂封止型半導体装置、2は半導体素
子、3はアイランド、4はインナーワイヤ、5は外部リ
ード、6は半導体封止樹脂、7はアイランド3裏面の凹
凸、8はアイランド3裏面の穴、9はアイランド3裏面
の貫通穴である。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a resin-sealed semiconductor device according to another embodiment of the invention. FIG. 4 is a sectional view showing a conventional device. In the figure, 1 is a resin-sealed semiconductor device, 2 is a semiconductor element, 3 is an island, 4 is an inner wire, 5 is an external lead, 6 is a semiconductor sealing resin, 7 is an uneven surface of the back surface of the island 3, and 8 is an island 3 The hole 9 on the back side is a through hole on the back side of the island 3. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] (1)アイランドに半導体素子を樹脂封止してなるフレ
ーム方式の樹脂封止型半導体装置において、上記アイラ
ンドの裏面には凹凸面若しくは複数の穴が形成されてい
ることを特徴とする樹脂封止型半導体装置。
(1) A frame-type resin-sealed semiconductor device in which a semiconductor element is resin-sealed in an island, characterized in that an uneven surface or a plurality of holes are formed on the back surface of the island. type semiconductor device.
(2)上記複数の穴は、その開口径がその内部径よりも
小さい凹状の穴であることを特徴とする特許請求の範囲
第1項記載の樹脂封止型半導体装置。
(2) The resin-sealed semiconductor device according to claim 1, wherein the plurality of holes are concave holes having an opening diameter smaller than an inner diameter thereof.
(3)上記複数の穴は、その開口径が深さ方向に増大す
るテーパ状の貫通穴であることを特徴とする特許請求の
範囲第1項記載の樹脂封止型半導体装置。
(3) The resin-sealed semiconductor device according to claim 1, wherein the plurality of holes are tapered through holes whose opening diameter increases in the depth direction.
JP62045841A 1987-02-27 1987-02-27 Resin sealed semiconductor device Pending JPS63213362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62045841A JPS63213362A (en) 1987-02-27 1987-02-27 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62045841A JPS63213362A (en) 1987-02-27 1987-02-27 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS63213362A true JPS63213362A (en) 1988-09-06

Family

ID=12730445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62045841A Pending JPS63213362A (en) 1987-02-27 1987-02-27 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS63213362A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129448A (en) * 1987-11-16 1989-05-22 Hitachi Ltd Lead frame
JPH04307760A (en) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp Resin-sealed semiconductor device
US5514913A (en) * 1991-12-05 1996-05-07 Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno Resin-encapsulated semiconductor device having improved adhesion
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device
US6239480B1 (en) * 1998-07-06 2001-05-29 Clear Logic, Inc. Modified lead frame for improved parallelism of a die to package
WO2016006193A1 (en) * 2014-07-11 2016-01-14 株式会社デンソー Mold package
WO2017094185A1 (en) * 2015-12-04 2017-06-08 ルネサスエレクトロニクス株式会社 Semiconductor chip, semiconductor device, and electronic device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129448A (en) * 1987-11-16 1989-05-22 Hitachi Ltd Lead frame
JPH04307760A (en) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp Resin-sealed semiconductor device
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device
US5514913A (en) * 1991-12-05 1996-05-07 Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno Resin-encapsulated semiconductor device having improved adhesion
US5766985A (en) * 1991-12-05 1998-06-16 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for encapsulating a semiconductor device having a heat sink
US6239480B1 (en) * 1998-07-06 2001-05-29 Clear Logic, Inc. Modified lead frame for improved parallelism of a die to package
WO2016006193A1 (en) * 2014-07-11 2016-01-14 株式会社デンソー Mold package
US9831146B1 (en) 2014-07-11 2017-11-28 Denso Corporation Molded package
WO2017094185A1 (en) * 2015-12-04 2017-06-08 ルネサスエレクトロニクス株式会社 Semiconductor chip, semiconductor device, and electronic device
JPWO2017094185A1 (en) * 2015-12-04 2018-09-13 ルネサスエレクトロニクス株式会社 Semiconductor chip, semiconductor device and electronic device
US10777475B2 (en) 2015-12-04 2020-09-15 Renesas Electronics Corporation Semiconductor chip, semiconductor device, and electronic device

Similar Documents

Publication Publication Date Title
US4849803A (en) Molded resin semiconductor device
US6734551B2 (en) Semiconductor device
DE102004043523B4 (en) Semiconductor device with heat radiation plate and attachment part
EP0258098A1 (en) Encapsulated semiconductor device and method of producing the same
KR950021435A (en) Resin-sealed semiconductor device and manufacturing method thereof
KR19980024503A (en) Semiconductor Package and Formation Method
JPS63213362A (en) Resin sealed semiconductor device
US4910581A (en) Internally molded isolated package
JPH04306865A (en) Semiconductor device and manufacture thereof
JPH06151657A (en) Semiconductor device and its manufacture
JPH02310954A (en) Lead frame and semiconductor device using same
JPH04307760A (en) Resin-sealed semiconductor device
JPH0254665B2 (en)
US11798868B2 (en) Metal tab for chip assembly
TWI290759B (en) Semiconductor package and its fabricating process
JPS6127909B2 (en)
JPS58199547A (en) lead frame
JPS6227548B2 (en)
JPH0329307B2 (en)
JPS61198658A (en) Resin-sealed semiconductor device
JPH11307559A (en) Manufacture of semiconductor device
JPH02202042A (en) Resin-sealed semiconductor device
JPS6123345A (en) Semiconductor device
JPS61194861A (en) Resin sealed type semiconductor device
JPS62183130A (en) Manufacture of semiconductor device sealed with resin